Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062928
Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, L. Benini, P. Hanumolu
Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with VDD, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (VDD <;0.5V). Digital PLLs (DPLLs) can operate at low VDD, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to VDD of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as VDD is varied from 0.45 to 0.7V.
{"title":"3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS","authors":"Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, L. Benini, P. Hanumolu","doi":"10.1109/ISSCC.2015.7062928","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062928","url":null,"abstract":"Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with VDD, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (VDD <;0.5V). Digital PLLs (DPLLs) can operate at low VDD, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to VDD of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as VDD is varied from 0.45 to 0.7V.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129466495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063144
M. Berkhout, A. Bakker, C. Sandner, Wentai Liu, Chin-Ming Hung, B. Redman-White
In recent years the availability of products for wireless charging of mobile devices has increased rapidly. The introduction of the Qi standard for wireless power transfer has marked the beginning of what could be a revolution in the way we charge our smartphones and tablets. Wireless power transfer is considered for use in applications ranging from biomedicai implants that require a couple of milliwatts to electrical vehicles that require kiloWatts. The vision of a future where we can conveniently, efficiently and safely charge our devices and vehicles anywhere without having to drag adapters and cables with us is gradually starting to become more realistic. This forum aims to give an overview of the state-of-the art in wireless power transfer. The fundamentals of different wireless power transfer techniques will be discussed, including not only inductive and resonant magnetic, but also capacitive power transfer and RF energy harvesting.
{"title":"F3: Cutting the last wire — Advances in wireless power","authors":"M. Berkhout, A. Bakker, C. Sandner, Wentai Liu, Chin-Ming Hung, B. Redman-White","doi":"10.1109/ISSCC.2015.7063144","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063144","url":null,"abstract":"In recent years the availability of products for wireless charging of mobile devices has increased rapidly. The introduction of the Qi standard for wireless power transfer has marked the beginning of what could be a revolution in the way we charge our smartphones and tablets. Wireless power transfer is considered for use in applications ranging from biomedicai implants that require a couple of milliwatts to electrical vehicles that require kiloWatts. The vision of a future where we can conveniently, efficiently and safely charge our devices and vehicles anywhere without having to drag adapters and cables with us is gradually starting to become more realistic. This forum aims to give an overview of the state-of-the art in wireless power transfer. The fundamentals of different wireless power transfer techniques will be discussed, including not only inductive and resonant magnetic, but also capacitive power transfer and RF energy harvesting.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121708671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063051
H. Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, D. Sun, Shin-Rung Wu, J. Liaw, Chih-Yung Lin, M. Chiang, H. Liao, Shien-Yang Wu, Jonathan Chang
FinFET technology has been adopted in the 16nm node because it provides superior lon/loff ratio, short-channel effect and local variation [1,2]. 2P-SRAM, which offers simultaneous read and write operations, is widely used for media processing because of its high operating efficiency. However, 2P-SRAM using the conventional 2P8T cell has a read-disturb issue, when both read wordline (RWL) and write word-line (WWL) are asserted simultaneously in the same row [3]. Furthermore, read-disturb becomes worse in FinFET technology compared with classical planar technology. In order to overcome these problems, we develop a disturb-current-free (DCF) 2P8T cell with PMOS write pass-gates and peripheral assist circuits to further improve its performance.
{"title":"17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies","authors":"H. Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, D. Sun, Shin-Rung Wu, J. Liaw, Chih-Yung Lin, M. Chiang, H. Liao, Shien-Yang Wu, Jonathan Chang","doi":"10.1109/ISSCC.2015.7063051","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063051","url":null,"abstract":"FinFET technology has been adopted in the 16nm node because it provides superior lon/loff ratio, short-channel effect and local variation [1,2]. 2P-SRAM, which offers simultaneous read and write operations, is widely used for media processing because of its high operating efficiency. However, 2P-SRAM using the conventional 2P8T cell has a read-disturb issue, when both read wordline (RWL) and write word-line (WWL) are asserted simultaneously in the same row [3]. Furthermore, read-disturb becomes worse in FinFET technology compared with classical planar technology. In order to overcome these problems, we develop a disturb-current-free (DCF) 2P8T cell with PMOS write pass-gates and peripheral assist circuits to further improve its performance.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062924
A. Nazemi, Kangmin Hu, B. Çatli, D. Cui, U. Singh, Tim He, Z. Huang, Bo Zhang, A. Momtaz, Jun Cao
At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s appears suboptimal in terms of both power and performance. Utilizing various modulation techniques such as PAM4, one can achieve a higher spectral efficiency [2]. To enable such transmission formats, high-speed moderate-resolution data converters are required. This paper describes a 36Gb/s transmitter based on an 18GS/s 8b DAC implemented in 28nm CMOS, compliant to the new IEEE802.3bj standard for 100G Ethernet over backplane and copper cables [3].
{"title":"3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS","authors":"A. Nazemi, Kangmin Hu, B. Çatli, D. Cui, U. Singh, Tim He, Z. Huang, Bo Zhang, A. Momtaz, Jun Cao","doi":"10.1109/ISSCC.2015.7062924","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062924","url":null,"abstract":"At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s appears suboptimal in terms of both power and performance. Utilizing various modulation techniques such as PAM4, one can achieve a higher spectral efficiency [2]. To enable such transmission formats, high-speed moderate-resolution data converters are required. This paper describes a 36Gb/s transmitter based on an 18GS/s 8b DAC implemented in 28nm CMOS, compliant to the new IEEE802.3bj standard for 100G Ethernet over backplane and copper cables [3].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130422466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063035
Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park
A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs that can alleviate the requirement on the minimum unit delay of the quantization by time-difference amplification, may be an attractive option. However these tend to be power-hungry or to require additional calibration circuitries due to the inaccuracy and PVT vulnerability of the time amplifier or time register. In this paper, we present a simple, low-power, and PVT-variation-tolerant TDC architecture without any calibration, using stochastic phase interpolation and 16× spatial redundancy.
{"title":"15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology","authors":"Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park","doi":"10.1109/ISSCC.2015.7063035","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063035","url":null,"abstract":"A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs that can alleviate the requirement on the minimum unit delay of the quantization by time-difference amplification, may be an attractive option. However these tend to be power-hungry or to require additional calibration circuitries due to the inaccuracy and PVT vulnerability of the time amplifier or time register. In this paper, we present a simple, low-power, and PVT-variation-tolerant TDC architecture without any calibration, using stochastic phase interpolation and 16× spatial redundancy.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134166092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063129
M. Brandolini, Y. Shin, K. Raviprakash, Tao Wang, R. Wu, H. M. Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, T. Li, A. Shrivastava, Yi-Chun Chen, Juo-Jung Hung, G. Cusmai, Jiangfeng Wu, M. Zhang, G. Unruh, Ardie G. Venes, H. Huang, Chun-Ying Chen
The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SAR's simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SAR's full-scale to the MDAC's. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.
{"title":"26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS","authors":"M. Brandolini, Y. Shin, K. Raviprakash, Tao Wang, R. Wu, H. M. Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, T. Li, A. Shrivastava, Yi-Chun Chen, Juo-Jung Hung, G. Cusmai, Jiangfeng Wu, M. Zhang, G. Unruh, Ardie G. Venes, H. Huang, Chun-Ying Chen","doi":"10.1109/ISSCC.2015.7063129","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063129","url":null,"abstract":"The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SAR's simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SAR's full-scale to the MDAC's. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128943500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062921
Bo Zhang, Karapet Khanoyan, H. Hatamkhani, Haitao Tong, Kangmin Hu, S. Fallahi, K. Vakilian, A. Brewster
Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-to-digital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.
{"title":"3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS","authors":"Bo Zhang, Karapet Khanoyan, H. Hatamkhani, Haitao Tong, Kangmin Hu, S. Fallahi, K. Vakilian, A. Brewster","doi":"10.1109/ISSCC.2015.7062921","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062921","url":null,"abstract":"Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-to-digital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063134
C. Ezekwe, W. Geiger, T. Ohms
Consumer-electronic (CE) gyroscopes have recently enjoyed broad deployment in high-volume applications, largely due to intuitive user interfaces in smart phones and video game controllers. For their continued expansion into more demanding CE applications, a further reduction of their noise, offset drift, and power dissipation, especially in the emerging always-on category, is mandatory. To be viable, solutions to these conflicting requirements must overcome the challenges of low cost and ever-shrinking package size. This paper describes one such solution with special emphasis on offset drift reduction. The system presented here discards the standard practice of electrically cancelling the quadrature error, and instead combines information derived from continuously monitoring the quadrature error together with a single-point temperature calibration to reduce offset drift. This paper presents the architecture and circuits used to realize a 3-axis open-loop gyroscope with a one-sigma TCO of 0.0065°/s/K.
{"title":"27.3 A 3-axis open-loop gyroscope with demodulation phase error correction","authors":"C. Ezekwe, W. Geiger, T. Ohms","doi":"10.1109/ISSCC.2015.7063134","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063134","url":null,"abstract":"Consumer-electronic (CE) gyroscopes have recently enjoyed broad deployment in high-volume applications, largely due to intuitive user interfaces in smart phones and video game controllers. For their continued expansion into more demanding CE applications, a further reduction of their noise, offset drift, and power dissipation, especially in the emerging always-on category, is mandatory. To be viable, solutions to these conflicting requirements must overcome the challenges of low cost and ever-shrinking package size. This paper describes one such solution with special emphasis on offset drift reduction. The system presented here discards the standard practice of electrically cancelling the quadrature error, and instead combines information derived from continuously monitoring the quadrature error together with a single-point temperature calibration to reduce offset drift. This paper presents the architecture and circuits used to realize a 3-axis open-loop gyroscope with a one-sigma TCO of 0.0065°/s/K.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133635579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063128
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins
Communication devices such as 60GHz-band receivers and serial links demand power-efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of ADCs is degraded by scaling up transistor widths in the building blocks for high speed, thus increasing the impact of intrinsic parasitics. Parallel schemes like multi-bit processing and interleaving [1], can ease the problems caused by scaling and lead to better efficiency if the hardware overhead is wisely reduced [2]. This paper presents a combination of 4× time interleaving and 3b/cycle multi-bit SAR ADC in 65nm CMOS, achieving a Nyquist FoM of 39fJ/conv-step for 5GS/s at 1V supply.
{"title":"26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS","authors":"Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/ISSCC.2015.7063128","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063128","url":null,"abstract":"Communication devices such as 60GHz-band receivers and serial links demand power-efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of ADCs is degraded by scaling up transistor widths in the building blocks for high speed, thus increasing the impact of intrinsic parasitics. Parallel schemes like multi-bit processing and interleaving [1], can ease the problems caused by scaling and lead to better efficiency if the hardware overhead is wisely reduced [2]. This paper presents a combination of 4× time interleaving and 3b/cycle multi-bit SAR ADC in 65nm CMOS, achieving a Nyquist FoM of 39fJ/conv-step for 5GS/s at 1V supply.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133099686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062989
Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, P. Hanumolu
In this paper, the authors present a digital frequency-tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. This ensures robust operation of the ILCM across PVT variations even with a very narrow lock-in range (ΔFL<;500ppm) and enables its implementation using large N and high-Q LC DCO. The prototype ILCM generates an output clock in the range of 6.75 to 8.25GHz by multiplying FREF by 64 and achieves 190fsrms integrated jitter while consuming 2.25mW power. The timing diagram shown in the paper illustrates the basic principle behind the proposed FTL. Because reference injection leads to a diminished phase error, ΔΦ, even in the presence of FERR, we measure ΔΦ by disabling injection periodically. In the example shown in the paper, every 4th reference edge is not injected, which results in a larger ΔΦ that can be easily measured and used to correct FERR using a simple digital feedback loop as described next.
{"title":"10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS","authors":"Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, P. Hanumolu","doi":"10.1109/ISSCC.2015.7062989","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062989","url":null,"abstract":"In this paper, the authors present a digital frequency-tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. This ensures robust operation of the ILCM across PVT variations even with a very narrow lock-in range (ΔFL<;500ppm) and enables its implementation using large N and high-Q LC DCO. The prototype ILCM generates an output clock in the range of 6.75 to 8.25GHz by multiplying FREF by 64 and achieves 190fsrms integrated jitter while consuming 2.25mW power. The timing diagram shown in the paper illustrates the basic principle behind the proposed FTL. Because reference injection leads to a diminished phase error, ΔΦ, even in the presence of FERR, we measure ΔΦ by disabling injection periodically. In the example shown in the paper, every 4th reference edge is not injected, which results in a larger ΔΦ that can be easily measured and used to correct FERR using a simple digital feedback loop as described next.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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