Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063034
Maoqiang Liu, P. Harpe, R. V. Dommele, A. Roermund
Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<;10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.
{"title":"15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation","authors":"Maoqiang Liu, P. Harpe, R. V. Dommele, A. Roermund","doi":"10.1109/ISSCC.2015.7063034","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063034","url":null,"abstract":"Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<;10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063098
Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1-3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity.
{"title":"22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization","authors":"","doi":"10.1109/ISSCC.2015.7063098","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063098","url":null,"abstract":"Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1-3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123447452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063010
Kyung-Goo Moti, F. Neri, S. Moon, Pyeongwoo Yeon, J. Yu, Y. Cheon, Yong-seong Roh, Myeonglyong Ko, Byeong-ha Park
Wireless power transfer (WPT) systems are becoming ubiquitous with applications in powering medical implants and a range of portable consumer electronic devices such as smart phones and wearable devices. Wireless power transferring methods can be classified into two types: inductive and resonant. For the resonant type, wider-range power transfer is possible, and multiple devices with different power requirements can be charged at the same time. The Alliance for Wireless Power (A4WP) has chosen the 6.78MHz ISM band as the power-transfer frequency [1]. At 6.78MHz, the associated switching loss is an order of magnitude larger than that in a typical wireless receiver based on an inductive coupling, with a carrier frequency of around 200kHz. Besides the two fundamental aspects of switching frequency and power, there is a third important parameter, notably the higher input voltage range needed for the `loosely coupled' resonant type, which is 25V maximum for this work. Ref. [2] appears to be one of few works that can be entirely related to the current work, targeting the same application. However, it does not integrate the most critical parts of the receiver, such as the AC-DC rectifier. Other works in the same frequency range are either limited to low-power applications [3] or the AC-DC rectifier is a stand-alone chip [4-5].
无线电力传输(WPT)系统在为医疗植入物和一系列便携式消费电子设备(如智能手机和可穿戴设备)供电方面正变得无处不在。无线电力传输方法可分为感应式和谐振式两种。对于谐振型，可以实现更大范围的功率传输，并且可以同时对具有不同功率要求的多个设备进行充电。无线电源联盟(Alliance for Wireless Power, A4WP)选择6.78MHz ISM频段作为功率传输频率[1]。在6.78MHz时，相关的开关损耗比基于电感耦合的典型无线接收机的开关损耗大一个数量级，载波频率约为200kHz。除了开关频率和功率这两个基本方面之外，还有第三个重要参数，特别是“松耦合”谐振类型所需的更高输入电压范围，该工作的最大输入电压为25V。Ref.[2]似乎是少数几个可以完全与当前工作相关，针对相同应用的作品之一。然而，它没有集成接收器最关键的部分，如交流-直流整流器。在同一频率范围内的其他工作要么限制在低功率应用[3]，要么交流-直流整流器是一个独立的芯片[4-5]。
{"title":"12.9 A fully integrated 6W wireless power receiver operating at 6.78MHz with magnetic resonance coupling","authors":"Kyung-Goo Moti, F. Neri, S. Moon, Pyeongwoo Yeon, J. Yu, Y. Cheon, Yong-seong Roh, Myeonglyong Ko, Byeong-ha Park","doi":"10.1109/ISSCC.2015.7063010","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063010","url":null,"abstract":"Wireless power transfer (WPT) systems are becoming ubiquitous with applications in powering medical implants and a range of portable consumer electronic devices such as smart phones and wearable devices. Wireless power transferring methods can be classified into two types: inductive and resonant. For the resonant type, wider-range power transfer is possible, and multiple devices with different power requirements can be charged at the same time. The Alliance for Wireless Power (A4WP) has chosen the 6.78MHz ISM band as the power-transfer frequency [1]. At 6.78MHz, the associated switching loss is an order of magnitude larger than that in a typical wireless receiver based on an inductive coupling, with a carrier frequency of around 200kHz. Besides the two fundamental aspects of switching frequency and power, there is a third important parameter, notably the higher input voltage range needed for the `loosely coupled' resonant type, which is 25V maximum for this work. Ref. [2] appears to be one of few works that can be entirely related to the current work, targeting the same application. However, it does not integrate the most critical parts of the receiver, such as the AC-DC rectifier. Other works in the same frequency range are either limited to low-power applications [3] or the AC-DC rectifier is a stand-alone chip [4-5].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123729317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063130
Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Hojin Park, S. Ryu
With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures made contributions in realizing high-speed single-channel ADCs with high resolution by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with power taking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept.
{"title":"26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique","authors":"Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Hojin Park, S. Ryu","doi":"10.1109/ISSCC.2015.7063130","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063130","url":null,"abstract":"With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures made contributions in realizing high-speed single-channel ADCs with high resolution by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with power taking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121922086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062976
J. Moreira, S. Leuschner, N. Stevanovic, H. Pretl, P. Pfann, R. Thüringer, M. Kastner, Christian Proll, A. Schwarz, F. Mrugalla, J. Saporiti, U. Basaran, A. Langer, T. D. Werth, T. Gossmann, B. Kapfelsperger, Johann Pletzer
The increasing complexity and cost pressure of advanced radios for mobile communication devices dictates further integration of front-end components into the transceiver (TRX) in order to reduce bill-of-material (BoM), printed-circuit-board (PCB) area and system cost. In [1] a fully-digital polar modulator is presented, which enables a SAW-less 2G/3G transmitter, in particular by solving the transmitter (TX) noise in receive (RX) band issues at various duplex distances (45/80/190/400MHz). Removing the TX SAW filter by adopting innovative transmitter topologies not only reduced the amount of external components, but also paved the way for monolithic power amplifier (PA) integration into the CMOS transceiver IC. This step poses additional challenges in terms of RX-TX cross-talk, self-heating and remodulation (unwanted frequency modulation of local oscillator by modulated output signal, very critical in IQ direct modulators, much less pronounced in polar modulators). The first integration of a PA with external matching network into a TRX SoC product has been presented in [2] for DECT cordless phones using GFSK modulation. PAs are also successfully integrated into a Wi-Fi TRX SoC, delivering linear transmit power up to 22dBm [3]. Following these earlier examples, this work proposes to fully integrate a PA capable of delivering more than 0.5W of linear RF power for the demanding 3G cellular applications.
{"title":"9.2 A single-chip HSPA transceiver with fully integrated 3G CMOS power amplifiers","authors":"J. Moreira, S. Leuschner, N. Stevanovic, H. Pretl, P. Pfann, R. Thüringer, M. Kastner, Christian Proll, A. Schwarz, F. Mrugalla, J. Saporiti, U. Basaran, A. Langer, T. D. Werth, T. Gossmann, B. Kapfelsperger, Johann Pletzer","doi":"10.1109/ISSCC.2015.7062976","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062976","url":null,"abstract":"The increasing complexity and cost pressure of advanced radios for mobile communication devices dictates further integration of front-end components into the transceiver (TRX) in order to reduce bill-of-material (BoM), printed-circuit-board (PCB) area and system cost. In [1] a fully-digital polar modulator is presented, which enables a SAW-less 2G/3G transmitter, in particular by solving the transmitter (TX) noise in receive (RX) band issues at various duplex distances (45/80/190/400MHz). Removing the TX SAW filter by adopting innovative transmitter topologies not only reduced the amount of external components, but also paved the way for monolithic power amplifier (PA) integration into the CMOS transceiver IC. This step poses additional challenges in terms of RX-TX cross-talk, self-heating and remodulation (unwanted frequency modulation of local oscillator by modulated output signal, very critical in IQ direct modulators, much less pronounced in polar modulators). The first integration of a PA with external matching network into a TRX SoC product has been presented in [2] for DECT cordless phones using GFSK modulation. PAs are also successfully integrated into a Wi-Fi TRX SoC, delivering linear transmit power up to 22dBm [3]. Following these earlier examples, this work proposes to fully integrate a PA capable of delivering more than 0.5W of linear RF power for the demanding 3G cellular applications.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126008845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063154
W. Dehaene
Technology scaling brings lower supply voltages. For advanced CMOS technology nodes of 40nm and beyond, this leads to specific challenges. In particular, analog circuits require specialized design approaches and innovative techniques. Maintaining high precision with reduced available signal swing while keeping energy consumption within reasonable bounds has presented challenges for many circuit designers. Increased technological variability and leakage only make this worse.
{"title":"SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages","authors":"W. Dehaene","doi":"10.1109/ISSCC.2015.7063154","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063154","url":null,"abstract":"Technology scaling brings lower supply voltages. For advanced CMOS technology nodes of 40nm and beyond, this leads to specific challenges. In particular, analog circuits require specialized design approaches and innovative techniques. Maintaining high precision with reduced available signal swing while keeping energy consumption within reasonable bounds has presented challenges for many circuit designers. Increased technological variability and leakage only make this worse.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063080
Xiaosen Liu, E. Sánchez-Sinencio
Compared with inductive DC-DC boost converters [1], the charge pump (CP) features no off-chip inductors and is suitable for monolithic low power energy harvesting applications such as Internet of Things (loT) smart nodes. However, the single conversion ratio (CR) CP has a narrow input voltage range. This induces a charge redistribution loss (CRL) and becomes a bottleneck preventing highly efficient energy harvesting [2]. CRL stems from two facts: 1) The operating voltages of energy sources vary with environment, and 2) Different energy sources feature a wide range of output voltages. By tuning the CR as one dimension, reconfigurable CPs can eliminate CRL; however, they need complex control algorithms, lack maximum power point tracking (MPPT) [3], and only provide fractional ratios [4]. Thus, they are not preferable for energy harvesting from various sources.
{"title":"20.7 A 0.45-to-3V reconfigurable charge-pump energy harvester with two-dimensional MPPT for Internet of Things","authors":"Xiaosen Liu, E. Sánchez-Sinencio","doi":"10.1109/ISSCC.2015.7063080","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063080","url":null,"abstract":"Compared with inductive DC-DC boost converters [1], the charge pump (CP) features no off-chip inductors and is suitable for monolithic low power energy harvesting applications such as Internet of Things (loT) smart nodes. However, the single conversion ratio (CR) CP has a narrow input voltage range. This induces a charge redistribution loss (CRL) and becomes a bottleneck preventing highly efficient energy harvesting [2]. CRL stems from two facts: 1) The operating voltages of energy sources vary with environment, and 2) Different energy sources feature a wide range of output voltages. By tuning the CR as one dimension, reconfigurable CPs can eliminate CRL; however, they need complex control algorithms, lack maximum power point tracking (MPPT) [3], and only provide fractional ratios [4]. Thus, they are not preferable for energy harvesting from various sources.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063058
Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Seongwook Park, K. Lee, Youchang Kim, H. Yoo
Smart eyeglasses or head-mounted displays (HMDs) have been gaining traction as next-generation mainstream wearable devices. However, previous HMD systems [1] have had limited application, primarily due to their lacking a smart user interface (Ul) and user experience (UX). Since HMD systems have a small compact wearable platform, their Ul requires new modalities, rather than a computer mouse or a 2D touch panel. Recent speech-recognition-based Uls require voice input to reveal the user's intention to not only HMD users but also others, which raises privacy concerns in a public space. In addition, prior works [2-3] attempted to support object recognition (OR) or augmented reality (AR) in smart eyeglasses, but consumed considerable power, >381mW, resulting in <;6 hours operation time with a 2100mWh battery.
{"title":"18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications","authors":"Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Seongwook Park, K. Lee, Youchang Kim, H. Yoo","doi":"10.1109/ISSCC.2015.7063058","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063058","url":null,"abstract":"Smart eyeglasses or head-mounted displays (HMDs) have been gaining traction as next-generation mainstream wearable devices. However, previous HMD systems [1] have had limited application, primarily due to their lacking a smart user interface (Ul) and user experience (UX). Since HMD systems have a small compact wearable platform, their Ul requires new modalities, rather than a computer mouse or a 2D touch panel. Recent speech-recognition-based Uls require voice input to reveal the user's intention to not only HMD users but also others, which raises privacy concerns in a public space. In addition, prior works [2-3] attempted to support object recognition (OR) or augmented reality (AR) in smart eyeglasses, but consumed considerable power, >381mW, resulting in <;6 hours operation time with a 2100mWh battery.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130650487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063069
R. Yazicigil, Tanbir Haque, Michael R. Whalen, Jeffrey Yuan, John Wright, P. Kinget
Mobile data traffic (driven by video over wireless, Internet of Things and machine-to-machine communications) is predicted to grow by several orders of magnitude over the coming decades, leading to severe spectrum deficits (500MHz to 1GHz in the near to long term). In 2012 the US President's Council of Advisors on Science and Technology (PCAST) recommended sharing government spectrum from 2.7GHz to 3.7GHz for public use while advocating that future systems deliver significantly improved spectrum efficiency. Cognitive radio systems with multi-tiered shared spectrum access (MTSSA) are expected to deliver such superior efficiency over existing scheduled-access systems; they have 3 or more device tiers with different access privileges. Lower tiered `smart' devices opportunistically use the underutilized spectrum and need spectrum sensing for incumbent detection and interférer avoidance. Incumbent detection will rely on database lookup or narrowband high-sensitivity sensing. Integrated interférer detectors, on the other hand, need to be fast, wideband and energy efficient while only requiring moderate sensitivity. During designated slot boundaries (10s of us), they quickly detect the presence of a few (3 or so) large interferers over e.g., a 1GHz span (2.7 to 3.7GHz) with a 20MHz RBW (i.e. 50 bins) so that the carrier-aggregating receiver can be reconfigured on a frame (10s of ms) or even slot (100s of us) basis.
{"title":"19.4 A 2.7-to-3.7GHz rapid interferer detector exploiting compressed sampling with a quadrature analog-to-information converter","authors":"R. Yazicigil, Tanbir Haque, Michael R. Whalen, Jeffrey Yuan, John Wright, P. Kinget","doi":"10.1109/ISSCC.2015.7063069","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063069","url":null,"abstract":"Mobile data traffic (driven by video over wireless, Internet of Things and machine-to-machine communications) is predicted to grow by several orders of magnitude over the coming decades, leading to severe spectrum deficits (500MHz to 1GHz in the near to long term). In 2012 the US President's Council of Advisors on Science and Technology (PCAST) recommended sharing government spectrum from 2.7GHz to 3.7GHz for public use while advocating that future systems deliver significantly improved spectrum efficiency. Cognitive radio systems with multi-tiered shared spectrum access (MTSSA) are expected to deliver such superior efficiency over existing scheduled-access systems; they have 3 or more device tiers with different access privileges. Lower tiered `smart' devices opportunistically use the underutilized spectrum and need spectrum sensing for incumbent detection and interférer avoidance. Incumbent detection will rely on database lookup or narrowband high-sensitivity sensing. Integrated interférer detectors, on the other hand, need to be fast, wideband and energy efficient while only requiring moderate sensitivity. During designated slot boundaries (10s of us), they quickly detect the presence of a few (3 or so) large interferers over e.g., a 1GHz span (2.7 to 3.7GHz) with a 20MHz RBW (i.e. 50 bins) so that the carrier-aggregating receiver can be reconfigured on a frame (10s of ms) or even slot (100s of us) basis.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130688400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063092
Muhammad Awais Bin Altaf, Chen Zhang, Jerald Yoo
Multichannel EEG seizure detection SoCs are widely used in medical practice and in research [1]-[3]. Due to huge variation in seizure patterns, patient-specific seizure detection is very crucial. [1], [2] presents 8-channel (ch) SoCs with moderate latency (~2s) but without seizure termination detection and stimulation. [3] implements a closed-loop SoC but is not patient-specific, and moreover, is invasive. This paper presents an ultra-low power 16-ch "non-invasive, patient-specific" seizure onset and termination detection SoC with channels multiplexing AFE and pulsating voltage transcranial electrical stimulation (PVTES).
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