Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063005
S. Dietrich, S. Strache, B. Mohr, Jan Henning Mueller, Leo Rolff, R. Wunderlich, S. Heinen
Today's general lighting development is driven by improvements in semiconductor-based systems. It is expected that solid-state lighting (SSL) will dominate general lighting in the near future. Two main challenges that must be met in SSL are the reduction of the bill of materials (BOM), and an increase in functionality. In [1], a floating DC-DC buck controller is presented. This controller adds to the BOM, as every device of the power path is discrete and the ASIC can only drive a single LED string. In contrast to that, [2] offers a high-current fully integrated power stage. However, several external passives are introduced and the technology inhibits stacking multiple LEDs for high luminous efficacy. To overcome this, [3] presents an integrated HV power path with only the inductor as an external component. Ina parallel development, [4] reports an LED driver similar to [3], but that uses a discrete Schottky diode for asynchronous rectification. In fact, [1-4] demonstrate single output LED drivers without additional functionality or full color spectrum. To overcome these drawbacks in light spectrum and control, [5] presents a 3-channel LED driver. However, the external passives are numerous, which significantly impairs the overall BOM.
{"title":"12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology","authors":"S. Dietrich, S. Strache, B. Mohr, Jan Henning Mueller, Leo Rolff, R. Wunderlich, S. Heinen","doi":"10.1109/ISSCC.2015.7063005","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063005","url":null,"abstract":"Today's general lighting development is driven by improvements in semiconductor-based systems. It is expected that solid-state lighting (SSL) will dominate general lighting in the near future. Two main challenges that must be met in SSL are the reduction of the bill of materials (BOM), and an increase in functionality. In [1], a floating DC-DC buck controller is presented. This controller adds to the BOM, as every device of the power path is discrete and the ASIC can only drive a single LED string. In contrast to that, [2] offers a high-current fully integrated power stage. However, several external passives are introduced and the technology inhibits stacking multiple LEDs for high luminous efficacy. To overcome this, [3] presents an integrated HV power path with only the inductor as an external component. Ina parallel development, [4] reports an LED driver similar to [3], but that uses a discrete Schottky diode for asynchronous rectification. In fact, [1-4] demonstrate single output LED drivers without additional functionality or full color spectrum. To overcome these drawbacks in light spectrum and control, [5] presents a 3-channel LED driver. However, the external passives are numerous, which significantly impairs the overall BOM.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133459915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063114
Colin Weltin-Wu, Guobi Zhao, I. Galton
Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and low supply voltages, which makes them better-suited to highly-scaled CMOS technology [1-6]. However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is because all fractional-N PLLs introduce quantization noise, and in prior digital PLLs this noise has higher power or spurious tones than in comparable analog PLLs. Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumps and ADCs that have so far limited their performance and minimum supply voltages [7,8]. This paper presents an FDC-PLL that avoids these limitations by implementing the functionality of a charge pump and ADC with a simple dual-mode ring oscillator (DMRO) and digital logic. Also demonstrated is a new quantization noise cancellation (QNC) technique that relaxes the fundamental bandwidth versus quantization noise tradeoff inherent to most fractional-TV PLLs. The new techniques enable state-of-the-art spurious tone performance and very low phase noise with a lower power dissipation and supply voltage than previously published state-of-the-art PLLs in the same class shown in Fig. 25.1.6.
{"title":"25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation","authors":"Colin Weltin-Wu, Guobi Zhao, I. Galton","doi":"10.1109/ISSCC.2015.7063114","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063114","url":null,"abstract":"Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and low supply voltages, which makes them better-suited to highly-scaled CMOS technology [1-6]. However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is because all fractional-N PLLs introduce quantization noise, and in prior digital PLLs this noise has higher power or spurious tones than in comparable analog PLLs. Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumps and ADCs that have so far limited their performance and minimum supply voltages [7,8]. This paper presents an FDC-PLL that avoids these limitations by implementing the functionality of a charge pump and ADC with a simple dual-mode ring oscillator (DMRO) and digital logic. Also demonstrated is a new quantization noise cancellation (QNC) technique that relaxes the fundamental bandwidth versus quantization noise tradeoff inherent to most fractional-TV PLLs. The new techniques enable state-of-the-art spurious tone performance and very low phase noise with a lower power dissipation and supply voltage than previously published state-of-the-art PLLs in the same class shown in Fig. 25.1.6.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122952817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062848
W. Sansen
In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.
{"title":"1.3 Analog CMOS from 5 micrometer to 5 nanometer","authors":"W. Sansen","doi":"10.1109/ISSCC.2015.7062848","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062848","url":null,"abstract":"In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117148238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062962
Chankyung Kim, K. Kwon, Chulwoo Park, Sungjin Jang, Joosun Choi
In this paper, we present a sensing scheme for STT-MRAM with 1T1MTJ common SL structure array: covalent-bonded cross-coupled current-mode sense amplifier (CBSA). The CBSA can fit in conventional DRAM array architecture and use two normal cells in adjacent BLs, one for storing data “1” and the other for storing data “0”, for generating reference currents for CBSA. There are 64 CBSAs in a row of 8k cells, where one CBSA and two references BLs are shared by adjacent 128 BLs. STT-MRAM cell is directly accessed instead of page opening as in DRAM. By introducing CBSAs as sensing schemes, read-access time can be reduced to under 10ns with strong robustness against wide random variations of MTJ cell resistances with a small TMR.
{"title":"7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array","authors":"Chankyung Kim, K. Kwon, Chulwoo Park, Sungjin Jang, Joosun Choi","doi":"10.1109/ISSCC.2015.7062962","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062962","url":null,"abstract":"In this paper, we present a sensing scheme for STT-MRAM with 1T1MTJ common SL structure array: covalent-bonded cross-coupled current-mode sense amplifier (CBSA). The CBSA can fit in conventional DRAM array architecture and use two normal cells in adjacent BLs, one for storing data “1” and the other for storing data “0”, for generating reference currents for CBSA. There are 64 CBSAs in a row of 8k cells, where one CBSA and two references BLs are shared by adjacent 128 BLs. STT-MRAM cell is directly accessed instead of page opening as in DRAM. By introducing CBSAs as sensing schemes, read-access time can be reduced to under 10ns with strong robustness against wide random variations of MTJ cell resistances with a small TMR.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117226095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063103
Marco Cignoli, Gabriele Minoia, M. Repossi, D. Baldi, A. Ghilioni, E. Temporiti, F. Svelto
In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.
{"title":"22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s","authors":"Marco Cignoli, Gabriele Minoia, M. Repossi, D. Baldi, A. Ghilioni, E. Temporiti, F. Svelto","doi":"10.1109/ISSCC.2015.7063103","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063103","url":null,"abstract":"In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115559358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063093
U. Ha, Yongsu Lee, Hyunki Kim, Taehwan Roh, Joonsung Bae, Changhyeon Kim, H. Yoo
Recently, wearable mental health management systems have been actively studied based on EEG monitoring and transcranial electrical stimulation (tES) [1]. It was reported that mental activities cause neural, vascular and autonomie domain changes in the human brain [2]. However, the previous neurofeedback system [1] used only neural domain information with low spatial resolution (~10cm) EEG signals. Furthermore, EEG signals are easily interfered by tES stimulation signal, eye-blinking and EMG signals so that it is difficult to monitor in real-time during stimulation and to avoid electromagnetic noise for accurate mental health classification.
{"title":"21.9 A wearable EEG-HEG-HRV multimodal system with real-time tES monitoring for mental health management","authors":"U. Ha, Yongsu Lee, Hyunki Kim, Taehwan Roh, Joonsung Bae, Changhyeon Kim, H. Yoo","doi":"10.1109/ISSCC.2015.7063093","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063093","url":null,"abstract":"Recently, wearable mental health management systems have been actively studied based on EEG monitoring and transcranial electrical stimulation (tES) [1]. It was reported that mental activities cause neural, vascular and autonomie domain changes in the human brain [2]. However, the previous neurofeedback system [1] used only neural domain information with low spatial resolution (~10cm) EEG signals. Furthermore, EEG signals are easily interfered by tES stimulation signal, eye-blinking and EMG signals so that it is difficult to monitor in real-time during stimulation and to avoid electromagnetic noise for accurate mental health classification.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062986
H. Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-cheol Hwang, B. Kong, Young-Hyun Jun
Emerging applications like cloud computing require high-speed low-latency access to high-volume data. In these applications, use of memory modules having multi-drop channels may be needed for time-efficient access to high-density memory data. A key design issue here is how to let interface transceivers not be affected by ISI and reflection noise generated by multi-drop channels having imperfect termination. The current-integrating decision-feedback equalizer (DFE) [1], which can cancel both high-frequency noise and post-cursor ISI simultaneously, has a limitation due to high gain-boosting and/or tap weight over-emphasis in equalizers to avoid eye closure caused by ISI-referred input pattern dependency. Duobinary signaling [2], which requires less boosting for equalizers by taking advantage of channel roll-off characteristic, is not effective in a multi-drop channel application because even a small timing or waveform variation due to high-frequency noise may cause degradation of the quality of duobinary signals. This work presents an integrating duobinary-based DFE receiver to avoid drawbacks described above and to increase the effective-data rate of multi-drop channels. A synergistic combination between the integrating equalizer and the duobinary signaling can provide advantages such as 1) lower gain-boosting for equalizers, 2) no need for precursor equalization, 3) ideally no input-pattern dependency during integration, 4) being more robust to high-frequency noise, 5) alleviated DFE critical timing, and 6) embedding DFE taps into duobinary circuits.
{"title":"10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface","authors":"H. Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-cheol Hwang, B. Kong, Young-Hyun Jun","doi":"10.1109/ISSCC.2015.7062986","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062986","url":null,"abstract":"Emerging applications like cloud computing require high-speed low-latency access to high-volume data. In these applications, use of memory modules having multi-drop channels may be needed for time-efficient access to high-density memory data. A key design issue here is how to let interface transceivers not be affected by ISI and reflection noise generated by multi-drop channels having imperfect termination. The current-integrating decision-feedback equalizer (DFE) [1], which can cancel both high-frequency noise and post-cursor ISI simultaneously, has a limitation due to high gain-boosting and/or tap weight over-emphasis in equalizers to avoid eye closure caused by ISI-referred input pattern dependency. Duobinary signaling [2], which requires less boosting for equalizers by taking advantage of channel roll-off characteristic, is not effective in a multi-drop channel application because even a small timing or waveform variation due to high-frequency noise may cause degradation of the quality of duobinary signals. This work presents an integrating duobinary-based DFE receiver to avoid drawbacks described above and to increase the effective-data rate of multi-drop channels. A synergistic combination between the integrating equalizer and the duobinary signaling can provide advantages such as 1) lower gain-boosting for equalizers, 2) no need for precursor equalization, 3) ideally no input-pattern dependency during integration, 4) being more robust to high-frequency noise, 5) alleviated DFE critical timing, and 6) embedding DFE taps into duobinary circuits.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121959277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063043
H. Fuketa, Masamune Hamamatsu, T. Yokota, Wakako Yukita, T. Someya, T. Sekitani, M. Takamiya, T. Someya, T. Sakurai
Three key requirements for wearable healthcare and biomedicai devices are the mechanical flexibility, the wireless interface, and the energy autonomy, because unobtrusive and maintenance-free devices are needed for the constant monitoring of vital human health data. Previously reported flexible healthcare and biomedicai devices, however, requires wired connection [1,2] or wireless power transmission [3,4]. A flexible energy autonomous healthcare device with a wireless interface, a fever alarm armband (FAA) integrating fully flexible solar cells, a piezoelectric speaker, a temperature detector, and 12V organic complementary FET (CFET) circuits is presented here. The system is also noteworthy for sound generation, with organic circuits driving the speaker.
{"title":"16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits","authors":"H. Fuketa, Masamune Hamamatsu, T. Yokota, Wakako Yukita, T. Someya, T. Sekitani, M. Takamiya, T. Someya, T. Sakurai","doi":"10.1109/ISSCC.2015.7063043","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063043","url":null,"abstract":"Three key requirements for wearable healthcare and biomedicai devices are the mechanical flexibility, the wireless interface, and the energy autonomy, because unobtrusive and maintenance-free devices are needed for the constant monitoring of vital human health data. Previously reported flexible healthcare and biomedicai devices, however, requires wired connection [1,2] or wireless power transmission [3,4]. A flexible energy autonomous healthcare device with a wireless interface, a fever alarm armband (FAA) integrating fully flexible solar cells, a piezoelectric speaker, a temperature detector, and 12V organic complementary FET (CFET) circuits is presented here. The system is also noteworthy for sound generation, with organic circuits driving the speaker.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063111
M. Yamaoka, C. Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
In the near future, the performance growth of Neumann-architecture computers will slow down due to the end of semiconductor scaling. Presently a new computing paradigm, so-called natural computing, which maps problems to physical models and solves the problem by its own convergence property, is expected. The analog computer using superconductivity from D-Wave [1] is one of those computers. A neuron chip [2] is also one of them. We proposed a CMOS-type Ising computer [3]. The Ising computer maps problems to an Ising model, a model to express the behavior of magnetic spins (the upper left diagram in Fig. 24.3.1), and solves the problems by ground-state search operations. The energy of the system is expressed by the formula in the diagram. Computing flows are expressed in the lower flow chart in Fig. 24.3.1. In the conventional Neumann architecture, the problem is sequentially and repeatedly calculated, and therefore, the number of computing steps drastically increases as the problem size grows. In the Ising computer, in the first step, the problem is mapped to the Ising model. In the next steps, an annealing operation, the ground-state search by interactions between spins, are activated and the state transitions to the ground state where the energy of the system is minimized. The interacting operation between spins is decided by the interaction coefficients, which are set to each connection. Here, the configuration of the interaction coefficients is decided by the problem, and therefore, the interaction coefficients are equivalent to the programming in the conventional computing paradigm. The ground state corresponds to the solution of the original problem, and the solution is acquired by observing the ground state. The interactions for the annealing are performed in parallel, and the necessary steps for the annealing are smaller than that used by a sequential computing, Neumann architecture. As the table in Fig. 24.3.1, our Ising computer uses CMOS circuits to express the Ising model, and acquires the scalability and operation at room temperature.
{"title":"24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing","authors":"M. Yamaoka, C. Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno","doi":"10.1109/ISSCC.2015.7063111","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063111","url":null,"abstract":"In the near future, the performance growth of Neumann-architecture computers will slow down due to the end of semiconductor scaling. Presently a new computing paradigm, so-called natural computing, which maps problems to physical models and solves the problem by its own convergence property, is expected. The analog computer using superconductivity from D-Wave [1] is one of those computers. A neuron chip [2] is also one of them. We proposed a CMOS-type Ising computer [3]. The Ising computer maps problems to an Ising model, a model to express the behavior of magnetic spins (the upper left diagram in Fig. 24.3.1), and solves the problems by ground-state search operations. The energy of the system is expressed by the formula in the diagram. Computing flows are expressed in the lower flow chart in Fig. 24.3.1. In the conventional Neumann architecture, the problem is sequentially and repeatedly calculated, and therefore, the number of computing steps drastically increases as the problem size grows. In the Ising computer, in the first step, the problem is mapped to the Ising model. In the next steps, an annealing operation, the ground-state search by interactions between spins, are activated and the state transitions to the ground state where the energy of the system is minimized. The interacting operation between spins is decided by the interaction coefficients, which are set to each connection. Here, the configuration of the interaction coefficients is decided by the problem, and therefore, the interaction coefficients are equivalent to the programming in the conventional computing paradigm. The ground state corresponds to the solution of the original problem, and the solution is acquired by observing the ground state. The interactions for the annealing are performed in parallel, and the necessary steps for the annealing are smaller than that used by a sequential computing, Neumann architecture. As the table in Fig. 24.3.1, our Ising computer uses CMOS circuits to express the Ising model, and acquires the scalability and operation at room temperature.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122069679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063045
Jinhong Ahn, Jeaheung Lim, S. Kim, J. Yun, Changhyun Kim, Sang-Hoon Hong, Myoung-Jin Lee, Youngjune Park
CMOS sensors using nanomaterials on the surface are very effective for early detection of diseases. Among the nanomaterials, carbon nanotube (CNT) is an ideal biosensor material since it has a small diameter (~1nm) directly comparable to the size of biomolecules and excellent electrical characteristics. Because CNT is formed chemically in a special environment, to use it in a CMOS process, many electrodes are formed as an array and the CNT solution is coated on the electrode array. However, to prevent electrical shorts between bonding pads, very complicated area-selective CNT coating processes are required. Furthermore, chip packaging steps - such as wire bonding, chip passivation against reactions to the wire, microfluidic channels on the chip, etc. - should be carefully applied [1].
{"title":"16.6 Double-side CMOS-CNT biosensor array with padless structure for simple bare-die measurements in a medical environment","authors":"Jinhong Ahn, Jeaheung Lim, S. Kim, J. Yun, Changhyun Kim, Sang-Hoon Hong, Myoung-Jin Lee, Youngjune Park","doi":"10.1109/ISSCC.2015.7063045","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063045","url":null,"abstract":"CMOS sensors using nanomaterials on the surface are very effective for early detection of diseases. Among the nanomaterials, carbon nanotube (CNT) is an ideal biosensor material since it has a small diameter (~1nm) directly comparable to the size of biomolecules and excellent electrical characteristics. Because CNT is formed chemically in a special environment, to use it in a CMOS process, many electrodes are formed as an array and the CNT solution is coated on the electrode array. However, to prevent electrical shorts between bonding pads, very complicated area-selective CNT coating processes are required. Furthermore, chip packaging steps - such as wire bonding, chip passivation against reactions to the wire, microfluidic channels on the chip, etc. - should be carefully applied [1].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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