Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063085
Hyunwoo Cho, Hyunki Kim, Minseo Kim, Jaeeun Jang, Joonsung Bae, H. Yoo
Recently, smart phones or head-mounted displays enables high definition (HD) video streaming and image data to be shared with friends while wearable smart sensors continuously monitor and send user's physiological information to a smart watch. Body channel communication (BCC), which uses the human body as the communication channel [1], has demonstrated better human-friendly interface and energy-efficient performance compared with air channel communication. However, most of the previous BCC research used only the frequency band below 100MHz and were only focused on either low data rate (<;10Mb/s) healthcare applications [2-5] or high data rate (60Mb/s) multimedia data transfer [6]. Its available channel bandwidth was limited <; 100MHz and the interference from FM radio due to body antenna effect had a significant effect on its performance. Moreover, [6] did not support full duplex communication so that the user interaction with wearable devices was not possible in live video streaming or real-time VR game applications.
{"title":"21.1 A 79pJ/b 80Mb/s full-duplex transceiver and a 42.5μW 100kb/s super-regenerative transceiver for body channel communication","authors":"Hyunwoo Cho, Hyunki Kim, Minseo Kim, Jaeeun Jang, Joonsung Bae, H. Yoo","doi":"10.1109/ISSCC.2015.7063085","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063085","url":null,"abstract":"Recently, smart phones or head-mounted displays enables high definition (HD) video streaming and image data to be shared with friends while wearable smart sensors continuously monitor and send user's physiological information to a smart watch. Body channel communication (BCC), which uses the human body as the communication channel [1], has demonstrated better human-friendly interface and energy-efficient performance compared with air channel communication. However, most of the previous BCC research used only the frequency band below 100MHz and were only focused on either low data rate (<;10Mb/s) healthcare applications [2-5] or high data rate (60Mb/s) multimedia data transfer [6]. Its available channel bandwidth was limited <; 100MHz and the interference from FM radio due to body antenna effect had a significant effect on its performance. Moreover, [6] did not support full duplex communication so that the user interaction with wearable devices was not possible in live video streaming or real-time VR game applications.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122655239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063071
H. Han, B. Yu, Tae Wook Kim
Contrary to conventional continuous-wave communication technologies, Impulse-radio Ultra-Wideband (IR-UWB) allows to have various functionalities such as communication, localization and radar by using a short pulse [1-4]. Also the short pulse occupies an extremely small period of time of the entire transmission period, so it is possible to consider a special technique for digitization of the short pulse which is essential for above applications.
{"title":"19.6 A 1.9mm-precision 20GS/S real-time sampling receiver using time-extension method for indoor localization","authors":"H. Han, B. Yu, Tae Wook Kim","doi":"10.1109/ISSCC.2015.7063071","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063071","url":null,"abstract":"Contrary to conventional continuous-wave communication technologies, Impulse-radio Ultra-Wideband (IR-UWB) allows to have various functionalities such as communication, localization and radar by using a short pulse [1-4]. Also the short pulse occupies an extremely small period of time of the entire transmission period, so it is possible to consider a special technique for digitization of the short pulse which is essential for above applications.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129865339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062922
T. Kawamoto, T. Norimatsu, K. Kogo, F. Yuki, N. Nakajima, M. Tsuge, T. Usugi, Tomofumi Hokari, H. Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, J. Kumazawa, Hiroaki Kurahashi, T. Muto, T. Yamashita, M. Hasegawa, K. Higeta
As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.
{"title":"3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS","authors":"T. Kawamoto, T. Norimatsu, K. Kogo, F. Yuki, N. Nakajima, M. Tsuge, T. Usugi, Tomofumi Hokari, H. Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, J. Kumazawa, Hiroaki Kurahashi, T. Muto, T. Yamashita, M. Hasegawa, K. Higeta","doi":"10.1109/ISSCC.2015.7062922","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062922","url":null,"abstract":"As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129677476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062923
P. Upadhyaya, J. Savoj, F. An, Ade Bekele, A. Jose, Bruce Xu, Zhaoyin Daniel Wu, D. Turker, H. A. Aslanzadeh, H. Hedayati, J. Im, Siok-Wei Lim, S. Chen, Toan Pham, Y. Frans, Ken Chang
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.
{"title":"3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS","authors":"P. Upadhyaya, J. Savoj, F. An, Ade Bekele, A. Jose, Bruce Xu, Zhaoyin Daniel Wu, D. Turker, H. A. Aslanzadeh, H. Hedayati, J. Im, Siok-Wei Lim, S. Chen, Toan Pham, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2015.7062923","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062923","url":null,"abstract":"The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131466498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063076
T. Andersen, F. Krismer, Johann W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, Matthias Braendli, P. Francese
On-chip (or fully integrated) switched-capacitor (SC) voltage regulators (SCVR) have recently received a lot of attention due to their ease of monolithic integration. The use of deep trench capacitors can lead to SCVR implementations that simultaneously achieve high efficiency, high power density, and fast response time. For the application of granular power distribution of many-core microprocessor systems, the on-chip SCVR must maintain an output voltage above a certain minimum level Uout, min in order for the microprocessor core to meet setup time requirements. Following a transient load change, the output voltage typically exhibits a droop due to parasitic inductances and resistances in the power distribution network. Therefore, the steady-state output voltage is kept high enough to ensure VOUT >Vout, min at all times, thereby introducing an output voltage overhead that leads to increased system power consumption. The output voltage droop can be reduced by implementing fast regulation and a sufficient amount of on-chip decoupling capacitance. However, a large amount of on-chip decoupling capacitance is needed to significantly reduce the droop, and it becomes impractical to implement owing to the large chip area overhead required. This paper presents a feedforward control scheme that significantly reduces the output voltage droop in the presence of a large input voltage droop following a transient event. This in turn reduces the required output voltage overhead and may lead to significant overall system power savings.
{"title":"20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS","authors":"T. Andersen, F. Krismer, Johann W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, Matthias Braendli, P. Francese","doi":"10.1109/ISSCC.2015.7063076","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063076","url":null,"abstract":"On-chip (or fully integrated) switched-capacitor (SC) voltage regulators (SCVR) have recently received a lot of attention due to their ease of monolithic integration. The use of deep trench capacitors can lead to SCVR implementations that simultaneously achieve high efficiency, high power density, and fast response time. For the application of granular power distribution of many-core microprocessor systems, the on-chip SCVR must maintain an output voltage above a certain minimum level Uout, min in order for the microprocessor core to meet setup time requirements. Following a transient load change, the output voltage typically exhibits a droop due to parasitic inductances and resistances in the power distribution network. Therefore, the steady-state output voltage is kept high enough to ensure VOUT >Vout, min at all times, thereby introducing an output voltage overhead that leads to increased system power consumption. The output voltage droop can be reduced by implementing fast regulation and a sufficient amount of on-chip decoupling capacitance. However, a large amount of on-chip decoupling capacitance is needed to significantly reduce the droop, and it becomes impractical to implement owing to the large chip area overhead required. This paper presents a feedforward control scheme that significantly reduces the output voltage droop in the presence of a large input voltage droop following a transient event. This in turn reduces the required output voltage overhead and may lead to significant overall system power savings.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062850
Hao Wu, M. Mikhemar, D. Murphy, H. Darabi, Mau-Chung Frank Chang
As there is no off-chip RF filtering available in a true Software-Defined-Radio (SDR), SDR receivers typically sufferfrom two fundamental issues when subject to large out-of-band blockers: gain compression and reciprocal mixing. Recently developed techniques based on passive mixers [1,3,4] addressed the first issue, with [1] notably achieving 0dBm blocker-tolerance and low-noise (Fig. 2.1.1 top left), yet they are still susceptible to reciprocal mixing (RM). Meanwhile, another recent work [2] showed a technique to cancel the RM by exploiting the symmetry of the phase noise (Fig. 2.1.1 top right). However, it is only capable of cancelling the RM caused by a moderate CW blocker (up to -10dBm), and lacks a front-end that is wideband, highly linear, and low-noise. In this work, we report a new architecture with phase- and thermal-noise cancellation to tackle the aforementioned challenges. The resulting design achieves 2dB small-signal NF and tolerates 0dBm blockers, yet incorporates no inductors even in the RF VCO. A low-cost wideband ring oscillator is integrated on-chip, and the phase-noise cancellation is capable of rejecting the RM when either a CW or a modulated blocker is present. This inductorless receiver achieves competitive performance compared with the state-of-the-art, breaking the traditional trade-off between LOGEN's power, phase noise, and cost commonly seen in all receivers.
{"title":"2.1 A highly linear inductorless wideband receiver with phase- and thermal-noise cancellation","authors":"Hao Wu, M. Mikhemar, D. Murphy, H. Darabi, Mau-Chung Frank Chang","doi":"10.1109/ISSCC.2015.7062850","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062850","url":null,"abstract":"As there is no off-chip RF filtering available in a true Software-Defined-Radio (SDR), SDR receivers typically sufferfrom two fundamental issues when subject to large out-of-band blockers: gain compression and reciprocal mixing. Recently developed techniques based on passive mixers [1,3,4] addressed the first issue, with [1] notably achieving 0dBm blocker-tolerance and low-noise (Fig. 2.1.1 top left), yet they are still susceptible to reciprocal mixing (RM). Meanwhile, another recent work [2] showed a technique to cancel the RM by exploiting the symmetry of the phase noise (Fig. 2.1.1 top right). However, it is only capable of cancelling the RM caused by a moderate CW blocker (up to -10dBm), and lacks a front-end that is wideband, highly linear, and low-noise. In this work, we report a new architecture with phase- and thermal-noise cancellation to tackle the aforementioned challenges. The resulting design achieves 2dB small-signal NF and tolerates 0dBm blockers, yet incorporates no inductors even in the RF VCO. A low-cost wideband ring oscillator is integrated on-chip, and the phase-noise cancellation is capable of rejecting the RM when either a CW or a modulated blocker is present. This inductorless receiver achieves competitive performance compared with the state-of-the-art, breaking the traditional trade-off between LOGEN's power, phase noise, and cost commonly seen in all receivers.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116457368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062944
Saad Bin Nasir, S. Gangopadhyay, A. Raychowdhury
This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node VREG, for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, KBARREL, of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs.
{"title":"5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range","authors":"Saad Bin Nasir, S. Gangopadhyay, A. Raychowdhury","doi":"10.1109/ISSCC.2015.7062944","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062944","url":null,"abstract":"This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node VREG, for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, KBARREL, of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063066
Jin Zhou, T. Chuang, T. Dinc, H. Krishnaswamy
In this paper, a 0.8-to-1.4GHz receiver with a tunable, reconfigurable RF SI canceller at the RX input is presented that supports >20MHz cancellation BW across a variety of antenna interfaces (nearly 10× improvement over a conventional canceller). This is accomplished by (i) a bank of tunable, reconfigurable 2nd-order high-Q RF bandpass filters in the canceller to emulate the antenna interface isolation (essentially RF frequency-domain equalization), and (ii) a linear N-path Gm-C filter implementation with embedded variable attenuation and phase shifting. For FDD, SIC enhances effective OOB IIP3 and IIP2 to +25-27d Bm and +90d Bm respectively. For SC-FD, SIC eliminates RX gain compression for as high as -8 dBm of peak in-band SI, and enhances effective in-band IIP3 and IIP2 by 22dB and 58 dB.
{"title":"19.1 Receiver with >20MHz bandwidth self-interference cancellation suitable for FDD, co-existence and full-duplex applications","authors":"Jin Zhou, T. Chuang, T. Dinc, H. Krishnaswamy","doi":"10.1109/ISSCC.2015.7063066","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063066","url":null,"abstract":"In this paper, a 0.8-to-1.4GHz receiver with a tunable, reconfigurable RF SI canceller at the RX input is presented that supports >20MHz cancellation BW across a variety of antenna interfaces (nearly 10× improvement over a conventional canceller). This is accomplished by (i) a bank of tunable, reconfigurable 2nd-order high-Q RF bandpass filters in the canceller to emulate the antenna interface isolation (essentially RF frequency-domain equalization), and (ii) a linear N-path Gm-C filter implementation with embedded variable attenuation and phase shifting. For FDD, SIC enhances effective OOB IIP3 and IIP2 to +25-27d Bm and +90d Bm respectively. For SC-FD, SIC eliminates RX gain compression for as high as -8 dBm of peak in-band SI, and enhances effective in-band IIP3 and IIP2 by 22dB and 58 dB.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062916
Seung-Chul Lee, Ji-Seon Paek, Jun-Hee Jung, Yong-Sik Youn, Sung-Jun Lee, Min-Soo Cho, JaeKwang Han, JungBum Choi, Yong-Whan Joo, Takahiro Nomiyama, Su-Ho Lee, I. Sohn, T. Cho, Byeong-ha Park, Inyup Kang
Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].
{"title":"2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power","authors":"Seung-Chul Lee, Ji-Seon Paek, Jun-Hee Jung, Yong-Sik Youn, Sung-Jun Lee, Min-Soo Cho, JaeKwang Han, JungBum Choi, Yong-Whan Joo, Takahiro Nomiyama, Su-Ho Lee, I. Sohn, T. Cho, Byeong-ha Park, Inyup Kang","doi":"10.1109/ISSCC.2015.7062916","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062916","url":null,"abstract":"Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130783746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063136
Hui Jiang, Z. Chang, M. Pertijs
Resonant sensors are a promising candidates for energy-constrained applications. For instance, the resonance frequency shift of polymer-coated MEMS resonators has been used to realize electronic nose systems for personalized health and environmental sensing [1]. Oscillator-based readout circuits for such sensors have been successfully implemented [2,3], but are relatively power-hungry, difficult to design in the presence of parasitic capacitance, and only provide information about the resonance frequency, fres, while the quality factor, Q, often includes additional valuable information.
{"title":"27.5 A 30ppm <80nJ ring-down-based readout circuit for resonant sensors","authors":"Hui Jiang, Z. Chang, M. Pertijs","doi":"10.1109/ISSCC.2015.7063136","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063136","url":null,"abstract":"Resonant sensors are a promising candidates for energy-constrained applications. For instance, the resonance frequency shift of polymer-coated MEMS resonators has been used to realize electronic nose systems for personalized health and environmental sensing [1]. Oscillator-based readout circuits for such sensors have been successfully implemented [2,3], but are relatively power-hungry, difficult to design in the presence of parasitic capacitance, and only provide information about the resonance frequency, fres, while the quality factor, Q, often includes additional valuable information.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132796951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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