Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063087
Alicia Klinefelter, N. Roberts, Y. Shakhsheer, Patricia González, A. Shrivastava, Abhishek Roy, Kyle Craig, M. Faisal, James Boley, Seunghyun Oh, Yanqing Zhang, Divya Akella, D. Wentzloff, B. Calhoun
A 1 trillion node internet of things (IoT) will require sensing platforms that support numerous applications using power harvesting to avoid the cost and scalability challenge of battery replacement in such large numbers. Previous SoCs achieve good integration and even energy harvesting [1][2][3], but they limit supported applications, need higher end-to-end harvesting efficiency, and require duty-cycling for RF communication. This paper demonstrates a highly integrated, flexible SoC platform that supports multiple sensing modalities, extracts information from data flexibly across applications, harvests and delivers power efficiently, and communicates wirelessly.
{"title":"21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios","authors":"Alicia Klinefelter, N. Roberts, Y. Shakhsheer, Patricia González, A. Shrivastava, Abhishek Roy, Kyle Craig, M. Faisal, James Boley, Seunghyun Oh, Yanqing Zhang, Divya Akella, D. Wentzloff, B. Calhoun","doi":"10.1109/ISSCC.2015.7063087","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063087","url":null,"abstract":"A 1 trillion node internet of things (IoT) will require sensing platforms that support numerous applications using power harvesting to avoid the cost and scalability challenge of battery replacement in such large numbers. Previous SoCs achieve good integration and even energy harvesting [1][2][3], but they limit supported applications, need higher end-to-end harvesting efficiency, and require duty-cycling for RF communication. This paper demonstrates a highly integrated, flexible SoC platform that supports multiple sensing modalities, extracts information from data flexibly across applications, harvests and delivers power efficiently, and communicates wirelessly.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121144560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062918
K. Datta, H. Hashemi
High speed, mm-Wave silicon transceivers with "Watt-level" output power have become necessary in recent years to support multi Gb/s communication protocols over realistic data-link lengths. However, efficient generation of power at mm-Waves is challenging in modern silicon processes with low breakdown voltages. Recent efforts have demonstrated "Watt-level" power generation using both silicon CMOS and HBT processes , but with <;10 % peak Power-Added-Efficiency (PAE) and without the ability to support modulation or power control efficiently. mm-Wave power DACs have been reported before, but with moderate output power (~ 24dBm) and low peak and average PAE (<;7%). This paper introduces a Watt-level mm-Wave digital power amplifier with significantly higher PAE at peak power level and back-off compared to existing state-of-the-art. Using highly efficient stacked Class-E amplifier unit cells, a 28.9dBm digital power amplifier is reported using a 0.13um SiGe HBT process with 18.4% peak PAE and 11% PAE at -6dB back-off with 8-level output amplitude control. Several innovative features like supply switch-less Class-E modulators to enable peak PAE, and a variable characteristic-impedance (Zchar) transmission-line-based dynamic load modulation network to maintain PAE under back-off have been demonstrated.
{"title":"2.9 A 29dBm 18.5% peak PAE mm-Wave digital power amplifier with dynamic load modulation","authors":"K. Datta, H. Hashemi","doi":"10.1109/ISSCC.2015.7062918","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062918","url":null,"abstract":"High speed, mm-Wave silicon transceivers with \"Watt-level\" output power have become necessary in recent years to support multi Gb/s communication protocols over realistic data-link lengths. However, efficient generation of power at mm-Waves is challenging in modern silicon processes with low breakdown voltages. Recent efforts have demonstrated \"Watt-level\" power generation using both silicon CMOS and HBT processes , but with <;10 % peak Power-Added-Efficiency (PAE) and without the ability to support modulation or power control efficiently. mm-Wave power DACs have been reported before, but with moderate output power (~ 24dBm) and low peak and average PAE (<;7%). This paper introduces a Watt-level mm-Wave digital power amplifier with significantly higher PAE at peak power level and back-off compared to existing state-of-the-art. Using highly efficient stacked Class-E amplifier unit cells, a 28.9dBm digital power amplifier is reported using a 0.13um SiGe HBT process with 18.4% peak PAE and 11% PAE at -6dB back-off with 8-level output amplitude control. Several innovative features like supply switch-less Class-E modulators to enable peak PAE, and a variable characteristic-impedance (Zchar) transmission-line-based dynamic load modulation network to maintain PAE under back-off have been demonstrated.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063121
A. Mostajeran, M. S. Bakhtiar, E. Afshari
For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flicker noise. The flicker noise can even degrade the PN at higher offset frequencies (~1MHz). The close-in PN is important in many communication applications. For instance, IEEE 802.11a/b/g requires a very low PN at 10kHz offset frequency [1] and the PN performance at 100kHz is critical in cellular and Wi-Fi MIMO applications. In addition to the PN performance, oscillators with lower power consumption and smaller area are always on demand.
{"title":"25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz offset frequencies in 0.13μm CMOS using an ISF manipulation technique","authors":"A. Mostajeran, M. S. Bakhtiar, E. Afshari","doi":"10.1109/ISSCC.2015.7063121","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063121","url":null,"abstract":"For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flicker noise. The flicker noise can even degrade the PN at higher offset frequencies (~1MHz). The close-in PN is important in many communication applications. For instance, IEEE 802.11a/b/g requires a very low PN at 10kHz offset frequency [1] and the PN performance at 100kHz is critical in cellular and Wi-Fi MIMO applications. In addition to the PN performance, oscillators with lower power consumption and smaller area are always on demand.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129536716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062963
H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai, S. Takaya, N. Shimomura, J. Ito, A. Kawasumi, H. Hara, S. Fujita
Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.
{"title":"7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","authors":"H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai, S. Takaya, N. Shimomura, J. Ito, A. Kawasumi, H. Hara, S. Fujita","doi":"10.1109/ISSCC.2015.7062963","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062963","url":null,"abstract":"Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062964
Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Daehoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seungwoo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj M. Rajagopal, Sang-Tae Kim, K. Kang, Jeong-Joon Park, Yongjin Kwon, Min-Jae Lee, Sunghoon Kim, Seung-Hwan Shin, Hyunggon Kim, Jin-Tae Kim, KiSeung Kim, Han-Sung Joo, Chanjin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, D. Byeon, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash.
{"title":"7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip","authors":"Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Daehoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seungwoo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj M. Rajagopal, Sang-Tae Kim, K. Kang, Jeong-Joon Park, Yongjin Kwon, Min-Jae Lee, Sunghoon Kim, Seung-Hwan Shin, Hyunggon Kim, Jin-Tae Kim, KiSeung Kim, Han-Sung Joo, Chanjin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, D. Byeon, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi","doi":"10.1109/ISSCC.2015.7062964","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062964","url":null,"abstract":"NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062977
Pedro Emiliano Paro Filho, M. Ingels, P. Wambacq, J. Craninckx
Driven by increasing data-rates, advanced mobile communication systems impose stringent requirements on every transmitter design aspect. Especially when the inter-stage SAW filter is removed, FDD operation using high-order modulation schemes (as in e.g. WCDMA, LTE) demands both remarkable noise performance and linearity, which is difficult to achieve without sacrificing power consumption. On the other hand, the increased switching speed of nanoscale MOS transistors has enabled the implementation of various digital-intensive TX architectures [1-5], that improved system robustness and reduced power and area consumption even in face of decreased supply voltages. However, in these cases reconstruction filtering is hindered by direct digital-to-RF conversion, leading to increased quantization noise and strong sampling aliases. Often addressed by increasing the converter resolution [2,3,4,6] and/or sampling frequency [2], these solutions typically become rather costly and directly affect the overall power consumption. This work introduces a TX architecture that innovates by operating in the charge domain. Its incremental - rather than absolute - signaling improves both quantization noise performance and power consumption. Using a 128MS/S 10b DAC configuration, it achieves -155dBc/Hz at 45MHz offset from a 1GHz modulated carrier, with intrinsic sampling alias attenuation.
{"title":"9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving −155dBc/Hz out-of-band noise","authors":"Pedro Emiliano Paro Filho, M. Ingels, P. Wambacq, J. Craninckx","doi":"10.1109/ISSCC.2015.7062977","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062977","url":null,"abstract":"Driven by increasing data-rates, advanced mobile communication systems impose stringent requirements on every transmitter design aspect. Especially when the inter-stage SAW filter is removed, FDD operation using high-order modulation schemes (as in e.g. WCDMA, LTE) demands both remarkable noise performance and linearity, which is difficult to achieve without sacrificing power consumption. On the other hand, the increased switching speed of nanoscale MOS transistors has enabled the implementation of various digital-intensive TX architectures [1-5], that improved system robustness and reduced power and area consumption even in face of decreased supply voltages. However, in these cases reconstruction filtering is hindered by direct digital-to-RF conversion, leading to increased quantization noise and strong sampling aliases. Often addressed by increasing the converter resolution [2,3,4,6] and/or sampling frequency [2], these solutions typically become rather costly and directly affect the overall power consumption. This work introduces a TX architecture that innovates by operating in the charge domain. Its incremental - rather than absolute - signaling improves both quantization noise performance and power consumption. Using a 128MS/S 10b DAC configuration, it achieves -155dBc/Hz at 45MHz offset from a 1GHz modulated carrier, with intrinsic sampling alias attenuation.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114915936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063028
Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park
The race to deep sub-micron CMOS technology has resulted in a change in device architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply. Downscaling trends have forced the analog semiconductor industry to move to the digital domain to maintain functionality in light of increasing short-channel effects and device mismatch. Furthermore, the main goal of the new technology is to achieve faster speed and lower cost. In leading-edge processes and design environments, conventional analog PLLs in systems-on-chip (SoCs) are being replaced by digitally operated PLLs to meet clock requirements for optimal overall system performance. While a widely used time-to-digital converter (TDC)-based digital PLL (TDC-DPLL) has a linear loop characteristic, which is simple and analogous to well-known analog PLLs, it has to overcome noise issues from TDC quantization error and phase noise from the digitally-controlled oscillator (DCO). The in-band noise floor of a TDC-DPLL is determined by the TDC resolution. Thanks to noise shaping techniques with oversampling and a pipelined architecture, noise performance can be improved. However, significant area and power must be spent to meet noise requirements. A bang-bang-based digital PLL (BB-DPLL), as the alternative type of DPLL has advantages in terms of area and power over a TDC-DPLL. However, its non-linear operation implies a longer lock time, limit-cycle noise, and high sensitivity to DCO noise. In addition, the in-band noise floor of a BB-DPLL is dominated by the input-tracking jitter, which mainly arises from the DCO noise. This paper presents a BB-DPLL in 14nm FinFET technology, combining a feed-forward delay-locked part (FFDLP) and phase-locked part (PLP) to mitigate aforementioned weaknesses.
{"title":"14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology","authors":"Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park","doi":"10.1109/ISSCC.2015.7063028","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063028","url":null,"abstract":"The race to deep sub-micron CMOS technology has resulted in a change in device architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply. Downscaling trends have forced the analog semiconductor industry to move to the digital domain to maintain functionality in light of increasing short-channel effects and device mismatch. Furthermore, the main goal of the new technology is to achieve faster speed and lower cost. In leading-edge processes and design environments, conventional analog PLLs in systems-on-chip (SoCs) are being replaced by digitally operated PLLs to meet clock requirements for optimal overall system performance. While a widely used time-to-digital converter (TDC)-based digital PLL (TDC-DPLL) has a linear loop characteristic, which is simple and analogous to well-known analog PLLs, it has to overcome noise issues from TDC quantization error and phase noise from the digitally-controlled oscillator (DCO). The in-band noise floor of a TDC-DPLL is determined by the TDC resolution. Thanks to noise shaping techniques with oversampling and a pipelined architecture, noise performance can be improved. However, significant area and power must be spent to meet noise requirements. A bang-bang-based digital PLL (BB-DPLL), as the alternative type of DPLL has advantages in terms of area and power over a TDC-DPLL. However, its non-linear operation implies a longer lock time, limit-cycle noise, and high sensitivity to DCO noise. In addition, the in-band noise floor of a BB-DPLL is dominated by the input-tracking jitter, which mainly arises from the DCO noise. This paper presents a BB-DPLL in 14nm FinFET technology, combining a feed-forward delay-locked part (FFDLP) and phase-locked part (PLP) to mitigate aforementioned weaknesses.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114311182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062980
Cellular multicarrier transmitters for communication infrastructure require both high linearity and large bandwidth (BW) at GHz frequencies. The combination of multicarrier GSM, WCDMA and LTE typically requires IMD<;-80dBc and SFDR>80dBc in a large transmit bandwidth of 300MHz and at an output frequency of up to 3.5GHz and beyond. Current-Steering (CS) Nyquist DACs have large BW, but their linearity drops for increasing output frequencies [1]. A separate mixer is therefore needed to generate an RF signal with high linearity. A Mixing-DAC integrates the function of the mixer and DAC together. Using a Mixing-DAC can result in different architecture trade-offs which potentially enable a reduction of the cost and power consumption, while improving the linearity at high frequencies. The state-of-the-art Mixing-DACs attain linearity by means of A2 modulation [2,3] or low sample rate [4], but this results in a limited BW and does not result in a linearity better than IMD=-71dBc. Even a GaAs implementation [5] only achieves IMD=-70dBc while consuming 1.2W.
{"title":"9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz","authors":"","doi":"10.1109/ISSCC.2015.7062980","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062980","url":null,"abstract":"Cellular multicarrier transmitters for communication infrastructure require both high linearity and large bandwidth (BW) at GHz frequencies. The combination of multicarrier GSM, WCDMA and LTE typically requires IMD<;-80dBc and SFDR>80dBc in a large transmit bandwidth of 300MHz and at an output frequency of up to 3.5GHz and beyond. Current-Steering (CS) Nyquist DACs have large BW, but their linearity drops for increasing output frequencies [1]. A separate mixer is therefore needed to generate an RF signal with high linearity. A Mixing-DAC integrates the function of the mixer and DAC together. Using a Mixing-DAC can result in different architecture trade-offs which potentially enable a reduction of the cost and power consumption, while improving the linearity at high frequencies. The state-of-the-art Mixing-DACs attain linearity by means of A2 modulation [2,3] or low sample rate [4], but this results in a limited BW and does not result in a linearity better than IMD=-71dBc. Even a GaAs implementation [5] only achieves IMD=-70dBc while consuming 1.2W.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063048
T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, T. Atsumi, Y. Shionoiri, K. Kato, T. Okuda, Yoshitaka Yamamoto, Masahiro Fujita, J. Koyama, S. Yamazaki
As the number of devices connected to the Internet increases, servers and mobile devices must process increasingly large volumes of data, and also accommodate the increasing demand for high-speed and large-capacity working memory keeping the power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change RAM, and MRAM [1], which realize high-speed, high-density and nonvolatile memory, significantly enhancing the performance of CPUs with integrated memories.
{"title":"16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method","authors":"T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, T. Atsumi, Y. Shionoiri, K. Kato, T. Okuda, Yoshitaka Yamamoto, Masahiro Fujita, J. Koyama, S. Yamazaki","doi":"10.1109/ISSCC.2015.7063048","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063048","url":null,"abstract":"As the number of devices connected to the Internet increases, servers and mobile devices must process increasingly large volumes of data, and also accommodate the increasing demand for high-speed and large-capacity working memory keeping the power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change RAM, and MRAM [1], which realize high-speed, high-density and nonvolatile memory, significantly enhancing the performance of CPUs with integrated memories.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116440009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062955
M. Hamaguchi, Michiaki Takeda, M. Miyamoto
A mutual-capacitance touch-sensing architecture and a system that enables concurrent usage of multiple active styluses having different properties such as color, thickness, shape, etc., are developed and verified with use of an existing touch controller [1]. An extension of the architecture to handle wireless active styluses is also developed and verified with an analog front-end (AFE) IC.
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