Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062972
Stephen T. Kim, Y. Shih, K. Mazumdar, Rinkle Jain, J. Ryan, Carlos Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De
A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VM!N, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR enables high power density and is area efficient, as it can use existing power headers originally employed for bypass/sleep modes, it suffers from efficiency loss at low VOUT. An SCVR, on the other hand, has improved conversion efficiency across a wide VOUT range. In an area-constrained design, however, the limited size of the SCVR's fly capacitors and associated configurable power stages sets an upper bound on the SCVR's maximum power density, restricting its use to lower VOUT. This LDO/SCVR combination delivers the power required by the core at a high VOUT of 0.92V with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN. Compared to a shared-rail scheme, the hybrid VR enables 26% to 82% reduction in core energy versus 26% to 67% if solely the LDO is used.
{"title":"8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation","authors":"Stephen T. Kim, Y. Shih, K. Mazumdar, Rinkle Jain, J. Ryan, Carlos Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De","doi":"10.1109/ISSCC.2015.7062972","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062972","url":null,"abstract":"A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VM!N, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR enables high power density and is area efficient, as it can use existing power headers originally employed for bypass/sleep modes, it suffers from efficiency loss at low VOUT. An SCVR, on the other hand, has improved conversion efficiency across a wide VOUT range. In an area-constrained design, however, the limited size of the SCVR's fly capacitors and associated configurable power stages sets an upper bound on the SCVR's maximum power density, restricting its use to lower VOUT. This LDO/SCVR combination delivers the power required by the core at a high VOUT of 0.92V with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN. Compared to a shared-rail scheme, the hybrid VR enables 26% to 82% reduction in core energy versus 26% to 67% if solely the LDO is used.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115879306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063075
C. Schaef, K. Kesarwani, J. Stauth
Switched-capacitor (SC) converters have shown significant promise for monolithic integration in a variety of mobile computing applications due to the relatively high energy-densities of modern capacitor technologies and the emergence of deep-trench technology [1-4]. Compared to more traditional buck and boost topologies, the SC approach provides better utilization of active and passive components, and is especially favorable when using submicron or deep-submicron CMOS technology because low-voltage devices can be configured in cascaded or hierarchical structures to interface across wide conversion ratios [5].
{"title":"20.2 A variable-conversion-ratio 3-phase resonant switched capacitor converter with 85% efficiency at 0.91W/mm2 using 1.1nH PCB-trace inductors","authors":"C. Schaef, K. Kesarwani, J. Stauth","doi":"10.1109/ISSCC.2015.7063075","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063075","url":null,"abstract":"Switched-capacitor (SC) converters have shown significant promise for monolithic integration in a variety of mobile computing applications due to the relatively high energy-densities of modern capacitor technologies and the emergence of deep-trench technology [1-4]. Compared to more traditional buck and boost topologies, the SC approach provides better utilization of active and passive components, and is especially favorable when using submicron or deep-submicron CMOS technology because low-voltage devices can be configured in cascaded or hierarchical structures to interface across wide conversion ratios [5].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063118
R. Han, Chen Jiang, A. Mostajeran, Mohammad Emadi, Hamidreza Aghasi, H. Sherry, A. Cathelin, E. Afshari
Non-ionizing terahertz imaging using solid-state integrated electronics has been gaining increasing attention over the past few years. However, there are currently several factors that deter the implementations of fully-integrated imaging systems. Due to the lack of low-noise amplification above fmax, the sensitivity of THz pixels on silicon cannot match that of its mm-Wave or light-wave counterparts. This, combined with the focal-plane array configuration adopted by previous sensors, requires exceedingly large power for the illumination sources. Previous works on silicon have demonstrated 1mW radiation [1,3]; but higher power, as well as energy efficiency, are needed for a practical imaging system. In addition, heterodyne imaging scheme was demonstrated to be very effective in enhancing detection sensitivity [4]. Due to the preservation of phase information, it also enables digital beam forming with a small number of receiver units. This however requires phase locking between the THz source and receiver LO with a small frequency offset (IF<;1GHz). In [5], a 300GHz PLL is reported with probed output. In this paper, a 320GHz transmitter using SiGe HBTs is presented (Fig. 25.5.1). Combining 16 coherent radiators, this work achieves 3.3mW radiated power with 0.54% DC-RF efficiency, which are the highest among state-of-the-art silicon THz radiators shown in the comparison table in Fig. 25.5.6. Meanwhile, the output beam is phase-locked by a fully-integrated PLL, which enables high-performance heterodyne imaging systems.
{"title":"25.5 A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems","authors":"R. Han, Chen Jiang, A. Mostajeran, Mohammad Emadi, Hamidreza Aghasi, H. Sherry, A. Cathelin, E. Afshari","doi":"10.1109/ISSCC.2015.7063118","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063118","url":null,"abstract":"Non-ionizing terahertz imaging using solid-state integrated electronics has been gaining increasing attention over the past few years. However, there are currently several factors that deter the implementations of fully-integrated imaging systems. Due to the lack of low-noise amplification above fmax, the sensitivity of THz pixels on silicon cannot match that of its mm-Wave or light-wave counterparts. This, combined with the focal-plane array configuration adopted by previous sensors, requires exceedingly large power for the illumination sources. Previous works on silicon have demonstrated 1mW radiation [1,3]; but higher power, as well as energy efficiency, are needed for a practical imaging system. In addition, heterodyne imaging scheme was demonstrated to be very effective in enhancing detection sensitivity [4]. Due to the preservation of phase information, it also enables digital beam forming with a small number of receiver units. This however requires phase locking between the THz source and receiver LO with a small frequency offset (IF<;1GHz). In [5], a 300GHz PLL is reported with probed output. In this paper, a 320GHz transmitter using SiGe HBTs is presented (Fig. 25.5.1). Combining 16 coherent radiators, this work achieves 3.3mW radiated power with 0.54% DC-RF efficiency, which are the highest among state-of-the-art silicon THz radiators shown in the comparison table in Fig. 25.5.6. Meanwhile, the output beam is phase-locked by a fully-integrated PLL, which enables high-performance heterodyne imaging systems.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063119
Zhiqiang Huang, H. Luong, B. Chi, Zhihua Wang, Haikun Jia
To support 16-QAM modulation in E-band applications, phase-locked loops (PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed to scale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by the op-amp. Moreover, as the capacitance is reduced, the resistor value has to be increased to maintain the same zero frequency, leading to higher thermal noise and limiting achievable scaling factor. Another method is to integrate digital loop filters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise of digitally-controlled oscillators (DCOs) becomes a bottleneck to achieve good phase noise due to their limited frequency resolution. Furthermore, E-band DCO oscillation frequency is more sensitive to capacitor variation, making it even more difficult to achieve high frequency resolution. To address these issues, this paper proposes a 70.5-to-85.5GHz PLL with an injection-locked frequency tripler (ILFM3) and passive scaling to increase the effective capacitor for the loop filter by 100 times.
{"title":"25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter","authors":"Zhiqiang Huang, H. Luong, B. Chi, Zhihua Wang, Haikun Jia","doi":"10.1109/ISSCC.2015.7063119","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063119","url":null,"abstract":"To support 16-QAM modulation in E-band applications, phase-locked loops (PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed to scale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by the op-amp. Moreover, as the capacitance is reduced, the resistor value has to be increased to maintain the same zero frequency, leading to higher thermal noise and limiting achievable scaling factor. Another method is to integrate digital loop filters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise of digitally-controlled oscillators (DCOs) becomes a bottleneck to achieve good phase noise due to their limited frequency resolution. Furthermore, E-band DCO oscillation frequency is more sensitive to capacitor variation, making it even more difficult to achieve high frequency resolution. To address these issues, this paper proposes a 70.5-to-85.5GHz PLL with an injection-locked frequency tripler (ILFM3) and passive scaling to increase the effective capacitor for the loop filter by 100 times.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123573815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063100
Hao Li, Z. Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, R. Ding, T. B. Jones, Marco Fiorentino, M. Hochberg, S. Palermo, P. Chiang
Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybrid-integrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4Vpp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for optical-dynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.
{"title":"22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS","authors":"Hao Li, Z. Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, R. Ding, T. B. Jones, Marco Fiorentino, M. Hochberg, S. Palermo, P. Chiang","doi":"10.1109/ISSCC.2015.7063100","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063100","url":null,"abstract":"Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybrid-integrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4Vpp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for optical-dynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126611315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063003
S. Kim, R. Nandwana, Q. Khan, R. Pilawa-Podgurski, P. Hanumolu
Multi-phase switching DC-DC converters offer many advantages in terms of high output power, low ripple, fast load transient response, high efficiency across a very wide range of load currents, and alleviated output filter requirements. However, the need for complex controllers that ensure accurate regulation and uniform current sharing between phases along with generation of multiple matched pulse-width modulated (PWM) signals complicate the design of multi-phase converters. Hysteretic control offers the simplest means to implement multi-phase converters and has been widely used in the prior art [1]. However, its nonlinear behavior leads to large output ripple, unpredictable loop dynamics, and wide variation in switching frequency (Fsw), which are undesirable in many noise-sensitive applications. Furthermore, they require current sensors to implement active current sharing, and generation of multiple synchronized PWM signals requires power hungry circuits [1]. A voltage-mode controller using a type-Ill compensator is well-suited for low-noise applications but it requires multiple synchronized and matched ramp generators that also incur large area and power penalty. A digital PWM generator can provide accurately matched multi-phase PWM signals thereby enabling passive current sharing, but digitally controlled buck converters exhibit large ripple due to their limit cycle behavior, have poor transient response, and consume significant quiescent current [2][3]. All these issues become even more challenging to address in high-Fsw converters because of more stringent loop-delay requirements.
{"title":"12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS","authors":"S. Kim, R. Nandwana, Q. Khan, R. Pilawa-Podgurski, P. Hanumolu","doi":"10.1109/ISSCC.2015.7063003","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063003","url":null,"abstract":"Multi-phase switching DC-DC converters offer many advantages in terms of high output power, low ripple, fast load transient response, high efficiency across a very wide range of load currents, and alleviated output filter requirements. However, the need for complex controllers that ensure accurate regulation and uniform current sharing between phases along with generation of multiple matched pulse-width modulated (PWM) signals complicate the design of multi-phase converters. Hysteretic control offers the simplest means to implement multi-phase converters and has been widely used in the prior art [1]. However, its nonlinear behavior leads to large output ripple, unpredictable loop dynamics, and wide variation in switching frequency (Fsw), which are undesirable in many noise-sensitive applications. Furthermore, they require current sensors to implement active current sharing, and generation of multiple synchronized PWM signals requires power hungry circuits [1]. A voltage-mode controller using a type-Ill compensator is well-suited for low-noise applications but it requires multiple synchronized and matched ramp generators that also incur large area and power penalty. A digital PWM generator can provide accurately matched multi-phase PWM signals thereby enabling passive current sharing, but digitally controlled buck converters exhibit large ripple due to their limit cycle behavior, have poor transient response, and consume significant quiescent current [2][3]. All these issues become even more challenging to address in high-Fsw converters because of more stringent loop-delay requirements.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114664964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Depth information has become essential in emerging computer vision applications. Although active sensing methods can provide an accurate indoor depth map, they have limited resolution and consume significant power, such as the 2.1W time-of-flight sensor in [1]. In contrast, depth estimation for stereo RGB images can provide high-resolution depth maps, even in outdoor or low-power scenarios. And, the depth accuracy can be increased by using multi-view light-field images. This paper presents an integrated circuit which estimates full HD (1920×1080) depth maps at 30fps and provides a tradeoff between depth accuracy and power consumption based on two-/three-/five-view stereo images. It addresses design challenges with three primary contributions: 1) a stripe buffering scheme which is designed to reduce the DRAM bandwidth induced by multi-view image access; 2) a four-bank interleaving architecture, which boosts computation performance by parallelizing belief-propagation (BP) operations; and, 3) an adaptive view selection unit, which realizes the accuracy-power tradeoff.
{"title":"23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications","authors":"Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen","doi":"10.1109/ISSCC.2015.7063106","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063106","url":null,"abstract":"Depth information has become essential in emerging computer vision applications. Although active sensing methods can provide an accurate indoor depth map, they have limited resolution and consume significant power, such as the 2.1W time-of-flight sensor in [1]. In contrast, depth estimation for stereo RGB images can provide high-resolution depth maps, even in outdoor or low-power scenarios. And, the depth accuracy can be increased by using multi-view light-field images. This paper presents an integrated circuit which estimates full HD (1920×1080) depth maps at 30fps and provides a tradeoff between depth accuracy and power consumption based on two-/three-/five-view stereo images. It addresses design challenges with three primary contributions: 1) a stripe buffering scheme which is designed to reduce the DRAM bandwidth induced by multi-view image access; 2) a four-bank interleaving architecture, which boosts computation performance by parallelizing belief-propagation (BP) operations; and, 3) an adaptive view selection unit, which realizes the accuracy-power tradeoff.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115019781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063124
Yong Lim, M. Flynn
The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SARADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relaxes the noise requirements of the second stage and enhances the overall ADC speed while maintaining excellent power efficiency [1-4]. However, designs reported in [1,2] rely on power-hungry telescopic amplifiers that also limit the available inter-stage residue gain due to low output swing. A lower-power alternative is a dynamic amplifier, which operates as an open-loop time-domain integrator [3,4]. Although time-domain integration provides the benefit of noise filtering, the calibration required to achieve an accurate residue gain increases design complexity and test cost, and limits robustness. We introduce an uncalibrated fully differential ring-amplifier-based 13b 50MS/s rail-to-rail input swing SAR-assisted pipeline ADC with Waiden and Schreier (SNDR) FoMs of 6.9fJ/conversion-step and 174.9dB, respectively. We also present an improved DAC switching technique that further reduces the first DAC energy consumption and also reduces the DAC errors.
{"title":"26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC","authors":"Yong Lim, M. Flynn","doi":"10.1109/ISSCC.2015.7063124","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063124","url":null,"abstract":"The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SARADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relaxes the noise requirements of the second stage and enhances the overall ADC speed while maintaining excellent power efficiency [1-4]. However, designs reported in [1,2] rely on power-hungry telescopic amplifiers that also limit the available inter-stage residue gain due to low output swing. A lower-power alternative is a dynamic amplifier, which operates as an open-loop time-domain integrator [3,4]. Although time-domain integration provides the benefit of noise filtering, the calibration required to achieve an accurate residue gain increases design complexity and test cost, and limits robustness. We introduce an uncalibrated fully differential ring-amplifier-based 13b 50MS/s rail-to-rail input swing SAR-assisted pipeline ADC with Waiden and Schreier (SNDR) FoMs of 6.9fJ/conversion-step and 174.9dB, respectively. We also present an improved DAC switching technique that further reduces the first DAC energy consumption and also reduces the DAC errors.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115318602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063096
Yanfei Chen, M. Kibune, Asako Toda, A. Hayakawa, T. Akiyama, S. Sekiguchi, H. Ebe, N. Imaizumi, T. Akahoshi, S. Akiyama, Shinsuke Tanaka, T. Simoyama, K. Morito, Takuji Yamamoto, Toshihiko Mori, Y. Koyanagi, H. Tamura
Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of -8.0dBm OMA.
{"title":"22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI","authors":"Yanfei Chen, M. Kibune, Asako Toda, A. Hayakawa, T. Akiyama, S. Sekiguchi, H. Ebe, N. Imaizumi, T. Akahoshi, S. Akiyama, Shinsuke Tanaka, T. Simoyama, K. Morito, Takuji Yamamoto, Toshihiko Mori, Y. Koyanagi, H. Tamura","doi":"10.1109/ISSCC.2015.7063096","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063096","url":null,"abstract":"Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of -8.0dBm OMA.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123544962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063081
S. Stanzione, C. V. Liempd, Misato Nabeto, R. Yazicioglu, C. Hoof
Battery life is a major concern in wireless sensing applications, as it causes a trade-off between system size and power consumption of the electronic circuits connected to it. Even if electronic circuit power consumption is steadily decreasing, the energy density of common energy storage systems is still extremely low in space-constrained applications. In this scenario, energy harvesting is a valuable solution to extend, in theory indefinitely, the autonomy of ubiquitous sensing systems. In particular, vibrational energy harvesters are an excellent solution to power sensors in industrial and automotive applications. This paper presents an electrostatic energy harvester (EEH) interface. Recently, electret-based EEHs have attracted considerable attention because of their capability to generate large powers, even at low accelerations [1]. Unfortunately, these devices are characterized by extremely high internal impedances and their interfacing circuits need to be simultaneously ultra-low-power and capable of working reliably with several tens of Volts applied to the input. To the best of our knowledge, only one solution has been proposed to efficiently interface high-voltage energy harvesters [2]. However, that circuit did not allow fully autonomous battery-less operation and did not work under 25μW available power.
{"title":"20.8 A 500nW batteryless integrated electrostatic energy harvester interface based on a DC-DC converter with 60V maximum input voltage and operating from 1μW available power, including MPPT and cold start","authors":"S. Stanzione, C. V. Liempd, Misato Nabeto, R. Yazicioglu, C. Hoof","doi":"10.1109/ISSCC.2015.7063081","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063081","url":null,"abstract":"Battery life is a major concern in wireless sensing applications, as it causes a trade-off between system size and power consumption of the electronic circuits connected to it. Even if electronic circuit power consumption is steadily decreasing, the energy density of common energy storage systems is still extremely low in space-constrained applications. In this scenario, energy harvesting is a valuable solution to extend, in theory indefinitely, the autonomy of ubiquitous sensing systems. In particular, vibrational energy harvesters are an excellent solution to power sensors in industrial and automotive applications. This paper presents an electrostatic energy harvester (EEH) interface. Recently, electret-based EEHs have attracted considerable attention because of their capability to generate large powers, even at low accelerations [1]. Unfortunately, these devices are characterized by extremely high internal impedances and their interfacing circuits need to be simultaneously ultra-low-power and capable of working reliably with several tens of Volts applied to the input. To the best of our knowledge, only one solution has been proposed to efficiently interface high-voltage energy harvesters [2]. However, that circuit did not allow fully autonomous battery-less operation and did not work under 25μW available power.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122859635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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