Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546461
J. Boucaud, Q. Hivin, C. Durand, F. Gianesello, D. Bucci, J. Robillard, F. Vaurette, J. Broquin, E. Dubois
In this paper, we propose an approach to improve silicon photonics-based optical transceivers packaging capabilities thanks to an optical and electrical interposer. We demonstrate the fabrication of polymer optical waveguides, single mode at telecom wavelengths using photosensitive resists and ultra-violet (UV) laser lithography on a glass substrate. Alongside the waveguides, a total internal reflection (TIR) based mirror is integrated for vertical redirection of the optical signal toward the silicon photonic integrated circuit (PIC). Femtosecond laser ablation is used for the mirror fabrication. Both the waveguides and the mirror have been optically characterized at 1310 nm. Total propagation losses of the waveguides have been measured at 5.5 dB for a 24.7 mm long waveguide. The mirrors present a circular distribution of the EM field.
{"title":"Single Mode Polymer Optical Waveguides and Out-ofplane Coupling Structure on a Glass Substrate","authors":"J. Boucaud, Q. Hivin, C. Durand, F. Gianesello, D. Bucci, J. Robillard, F. Vaurette, J. Broquin, E. Dubois","doi":"10.1109/ESTC.2018.8546461","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546461","url":null,"abstract":"In this paper, we propose an approach to improve silicon photonics-based optical transceivers packaging capabilities thanks to an optical and electrical interposer. We demonstrate the fabrication of polymer optical waveguides, single mode at telecom wavelengths using photosensitive resists and ultra-violet (UV) laser lithography on a glass substrate. Alongside the waveguides, a total internal reflection (TIR) based mirror is integrated for vertical redirection of the optical signal toward the silicon photonic integrated circuit (PIC). Femtosecond laser ablation is used for the mirror fabrication. Both the waveguides and the mirror have been optically characterized at 1310 nm. Total propagation losses of the waveguides have been measured at 5.5 dB for a 24.7 mm long waveguide. The mirrors present a circular distribution of the EM field.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131235730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546405
A. Géczy, I. Bozsóki, B. Illés
Vapour Phase Soldering (VPS) is a condensation based heat-transfer method for reflowing electronic assemblies in electronics manufacturing. VPS is still not widespread in the industry, despite its comeback and clear advantages. This is mainly due to the general use of convection type reflow, the lower throughput of VPS type ovens and the complex process, which is difficult to monitor both by measurement and modelling approaches. Our research focuses on investigating the modeling of the process, to aim for better control and improved soldering quality. The process is sensitive to any perturbing measurements, involving sensors, so carefully validated modelling software may help to understand the details of this reflow method. In order to investigate the process, three different modelling approaches were elaborated with different focuses. The first approach presents an explicit and fast modelling method of the Printed Circuit Board level, involving the abstraction of condensation on horizontal plates and discs. The second approach extends the view by focusing on the component, using heat transfer coefficients extracted from experimental data. The method can reveal specific effects of heat transfer on SMD components with different structures. The third approach involves the volume of the work zone, the vapour blanket inside, the surface and the structure of the assembly. With a multi-physics (heat- and mass transfer) and additional co-simulation approach - based on a custom Finite Difference Method (FDM) solver - the work zone and the board level can be modelled simultaneously. This brings the possibility to monitor the state of the vapour, to investigate the effects of assemblies on the vapour blanket, and the state of the condensate combined, affecting heat transfer on the assembly. The modelling approaches are presented in the paper with a general summary of our recent works, discussion on the validation and the achieved results, highlighting possible rooms for improvement. The findings may also help improving oven design aspects pointing to the requirements of future factories.
{"title":"Modelling approaches of Vapour Phase Reflow Soldering","authors":"A. Géczy, I. Bozsóki, B. Illés","doi":"10.1109/ESTC.2018.8546405","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546405","url":null,"abstract":"Vapour Phase Soldering (VPS) is a condensation based heat-transfer method for reflowing electronic assemblies in electronics manufacturing. VPS is still not widespread in the industry, despite its comeback and clear advantages. This is mainly due to the general use of convection type reflow, the lower throughput of VPS type ovens and the complex process, which is difficult to monitor both by measurement and modelling approaches. Our research focuses on investigating the modeling of the process, to aim for better control and improved soldering quality. The process is sensitive to any perturbing measurements, involving sensors, so carefully validated modelling software may help to understand the details of this reflow method. In order to investigate the process, three different modelling approaches were elaborated with different focuses. The first approach presents an explicit and fast modelling method of the Printed Circuit Board level, involving the abstraction of condensation on horizontal plates and discs. The second approach extends the view by focusing on the component, using heat transfer coefficients extracted from experimental data. The method can reveal specific effects of heat transfer on SMD components with different structures. The third approach involves the volume of the work zone, the vapour blanket inside, the surface and the structure of the assembly. With a multi-physics (heat- and mass transfer) and additional co-simulation approach - based on a custom Finite Difference Method (FDM) solver - the work zone and the board level can be modelled simultaneously. This brings the possibility to monitor the state of the vapour, to investigate the effects of assemblies on the vapour blanket, and the state of the condensate combined, affecting heat transfer on the assembly. The modelling approaches are presented in the paper with a general summary of our recent works, discussion on the validation and the achieved results, highlighting possible rooms for improvement. The findings may also help improving oven design aspects pointing to the requirements of future factories.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546462
G. Alavi, Sefa Özbek, Mahsa Rasteh, M. Grözing, M. Berroth, J. Hesselbarth, Joachim N.Burghartz
a flexible and adaptive energy-efficient high-speed wireless hub is developed as a Hybrid System-in-Foil (HySiF) using CMOS compatible Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 × 1.65 mm2) are thinned down to 45 µm and are embedded face-up inside a two-polymer CFP flexible foil carrier. The active pads of embedded silicon chips inside foil are extended to the surface of the foil and interconnected to the antenna fabricated on the foil using an adaptive layout technique. A thin chip power amplifier (PA) is embedded in flexible polymer foil and is interconnected to the antenna with a signal transmission at 5.5 GHz. The overall thickness of system is below 100 µm and, thus, has bendability down to 4 mm radius of curvature.
{"title":"Embedding and Interconnecting of Ultra-Thin RF Chip in Combination with Flexible Wireless Hub in Polymer Foil","authors":"G. Alavi, Sefa Özbek, Mahsa Rasteh, M. Grözing, M. Berroth, J. Hesselbarth, Joachim N.Burghartz","doi":"10.1109/ESTC.2018.8546462","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546462","url":null,"abstract":"a flexible and adaptive energy-efficient high-speed wireless hub is developed as a Hybrid System-in-Foil (HySiF) using CMOS compatible Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 × 1.65 mm2) are thinned down to 45 µm and are embedded face-up inside a two-polymer CFP flexible foil carrier. The active pads of embedded silicon chips inside foil are extended to the surface of the foil and interconnected to the antenna fabricated on the foil using an adaptive layout technique. A thin chip power amplifier (PA) is embedded in flexible polymer foil and is interconnected to the antenna with a signal transmission at 5.5 GHz. The overall thickness of system is below 100 µm and, thus, has bendability down to 4 mm radius of curvature.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546481
A. Cardoso, S. Martins, A. Gouvêa
Electromigration (EM) is an important phenomenon in microelectronics, widely studied and modeled in chip design in the last decades. More recently, the increase of packaging density pushed EM studies outside of the chip. In Wafer Level Fan-In and Wafer Level Fan-Out designs, EM studies have focused on the package solderjoins, due to the poor robustness of solder alloys to EM. Inside the package, the copper traces in the redistribution layer (RDL) have not been considered critical because the minimum cross-sectional area of RDL technology had non-critical current densities. However, the constant demand for packaging miniaturization is requiring even higher RDL densities, with line/space ($mathrm {L}/mathrm {S})lt 5mu mathrm {m}$ under development for fan-out and $mathrm {L}/mathrm {S}lt 2 mu mathrm {m}$ for fan-in. Due to RDL process limitations, L/S reduction carries a quadratic reduction on the trace's cross-section, which can have a significant impact on EM reliability. Moreover, while IC lines are embedded in a thermally-conductive medium, RDL lines are built on dielectrics with poor heat dissipation and, also critical, fan-out packages have areas/ materials with very different thermal conductivity - silicon (Si), mold compound (MC), which lead to hotter and uneven line temperatures and consequently different EM rates.This paper studies the EM effects in RDL and quantifies its impact on reliability and product life expectancy for Amkor's WLFI/WLFO technologies. The increase of relative resistance, $Delta mathrm {R}/mathrm {R}$, was analyzed on highly stressed RDL Cu traces, built over Si and MC units to test the extreme conditions in fan-out packages. Both continuous and on-off cycled temperature tests were conducted to investigate the thermomechanical stress impact on EM. The results showed very different increase rates of $Delta mathrm {R}/mathrm {R}$ due to the very different thermal dissipation abilities, identifying the need for specific RDL design rules. In the continuous temperature tests, the fairly linear increase of $Delta mathrm {R}/mathrm {R}$ suggested the use of a degradation rate (DR) to characterize the EM effects in a very fast way, instead of determining mean time to failure (MTTF) figures that are time-consuming and depend on arbitrary and heuristic failure criteria (e.g., 20% rise of $Delta mathrm {R}/mathrm {R})$. The linear extrapolation enabled by the DR also allowed the fast build-up of MTTF Weibull plots that would otherwise take several months to complete. A model for the DR, adapted from Black's model, was developed for the statistical estimation of mean DR for a given temperature and current density. In the on-off cycled temperature test, a stepwise behavior of $Delta mathrm {R}/mathrm {R}$ was observed, with general reduction of net MTTF, while DR acceleration was only observed on the MC units, pointing to external thermomechanical-induced effects on the measured $Delta mathrm {R}/mathrm {R}$, which are filtered by
电迁移是微电子学中的一个重要现象，近几十年来在芯片设计中得到了广泛的研究和建模。最近，封装密度的增加推动了芯片之外的EM研究。在晶圆级Fan-In和Wafer - Level Fan-Out设计中，由于焊料合金对EM的鲁棒性较差，EM研究主要集中在封装焊点上。在封装内部，再分布层(RDL)中的铜迹线没有被认为是关键的，因为RDL技术的最小横截面积具有非临界电流密度。然而，对封装小型化的持续需求要求更高的RDL密度，线/空间($mathrm {L}/mathrm {S})lt 5mu mathrm {m}$正在开发用于扇出和$mathrm {L}/mathrm {S}lt 2 mu mathrm {m}$用于扇入)。由于RDL工艺的限制，L/S的减少会对轨迹的横截面产生二次减少，这可能对电磁可靠性产生重大影响。此外，虽然IC线嵌入在导热介质中，但RDL线建立在散热性差的电介质上，同样关键的是，扇出封装的区域/材料具有非常不同的导热性-硅(Si)，模具化合物(MC)，这会导致更热且不均匀的线路温度，从而导致不同的EM率。本文研究了RDL中的EM效应，并量化了其对Amkor的WLFI/WLFO技术的可靠性和产品预期寿命的影响。相对电阻的增加$Delta mathrm {R}/mathrm {R}$在高应力RDL Cu走线上进行了分析，建立在Si和MC单元上，以测试扇形封装中的极端条件。通过连续和开关循环温度测试，研究了热机械应力对EM的影响。结果表明，由于不同的散热能力，$Delta mathrm {R}/mathrm {R}$的增加速率非常不同，因此需要制定特定的RDL设计规则。在连续温度测试中，$Delta mathrm {R}/mathrm {R}$的线性增加表明，使用降解率(DR)以非常快速的方式表征电磁效应，而不是确定耗时且依赖于任意和启发式失效标准(例如，20% rise of $Delta mathrm {R}/mathrm {R})$. The linear extrapolation enabled by the DR also allowed the fast build-up of MTTF Weibull plots that would otherwise take several months to complete. A model for the DR, adapted from Black's model, was developed for the statistical estimation of mean DR for a given temperature and current density. In the on-off cycled temperature test, a stepwise behavior of $Delta mathrm {R}/mathrm {R}$ was observed, with general reduction of net MTTF, while DR acceleration was only observed on the MC units, pointing to external thermomechanical-induced effects on the measured $Delta mathrm {R}/mathrm {R}$, which are filtered by the DR analysis.
{"title":"Characterization of Electromigration Effects in RDL of Wafer Level Fan-In and Fan-Out Packaging Using a Novel Analysis Approach","authors":"A. Cardoso, S. Martins, A. Gouvêa","doi":"10.1109/ESTC.2018.8546481","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546481","url":null,"abstract":"Electromigration (EM) is an important phenomenon in microelectronics, widely studied and modeled in chip design in the last decades. More recently, the increase of packaging density pushed EM studies outside of the chip. In Wafer Level Fan-In and Wafer Level Fan-Out designs, EM studies have focused on the package solderjoins, due to the poor robustness of solder alloys to EM. Inside the package, the copper traces in the redistribution layer (RDL) have not been considered critical because the minimum cross-sectional area of RDL technology had non-critical current densities. However, the constant demand for packaging miniaturization is requiring even higher RDL densities, with line/space ($mathrm {L}/mathrm {S})lt 5mu mathrm {m}$ under development for fan-out and $mathrm {L}/mathrm {S}lt 2 mu mathrm {m}$ for fan-in. Due to RDL process limitations, L/S reduction carries a quadratic reduction on the trace's cross-section, which can have a significant impact on EM reliability. Moreover, while IC lines are embedded in a thermally-conductive medium, RDL lines are built on dielectrics with poor heat dissipation and, also critical, fan-out packages have areas/ materials with very different thermal conductivity - silicon (Si), mold compound (MC), which lead to hotter and uneven line temperatures and consequently different EM rates.This paper studies the EM effects in RDL and quantifies its impact on reliability and product life expectancy for Amkor's WLFI/WLFO technologies. The increase of relative resistance, $Delta mathrm {R}/mathrm {R}$, was analyzed on highly stressed RDL Cu traces, built over Si and MC units to test the extreme conditions in fan-out packages. Both continuous and on-off cycled temperature tests were conducted to investigate the thermomechanical stress impact on EM. The results showed very different increase rates of $Delta mathrm {R}/mathrm {R}$ due to the very different thermal dissipation abilities, identifying the need for specific RDL design rules. In the continuous temperature tests, the fairly linear increase of $Delta mathrm {R}/mathrm {R}$ suggested the use of a degradation rate (DR) to characterize the EM effects in a very fast way, instead of determining mean time to failure (MTTF) figures that are time-consuming and depend on arbitrary and heuristic failure criteria (e.g., 20% rise of $Delta mathrm {R}/mathrm {R})$. The linear extrapolation enabled by the DR also allowed the fast build-up of MTTF Weibull plots that would otherwise take several months to complete. A model for the DR, adapted from Black's model, was developed for the statistical estimation of mean DR for a given temperature and current density. In the on-off cycled temperature test, a stepwise behavior of $Delta mathrm {R}/mathrm {R}$ was observed, with general reduction of net MTTF, while DR acceleration was only observed on the MC units, pointing to external thermomechanical-induced effects on the measured $Delta mathrm {R}/mathrm {R}$, which are filtered by","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120810750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546376
W. David, B. Philipp, B. Sven, Petrova Hanna, F. Sebastian, Schumann Ulrich, Schmidt Bertram, Detert Markus
One trend in medical technology is the continuous miniaturization of components, assemblies and complete systems. Such complete systems are functionalized catheters with different sensor and actuator components [1–8]. If even the smallest bottlenecks, for example in blood vessels, are to be reached in the human body, the catheter diameter must be further reduced with the same functionalization. A new approach is chosen, which does not apply the supply and signal lines to the catheter surface or insert them into the existing lumen, but becomes a direct and inseparable part of the catheter. Contacting these conducting tracks with the electronic components is one of the key processes in the manufacture of this type of catheter. A final demonstrator is used for functional testing.
{"title":"Bus-based, miniaturized multi-sensory catheter system","authors":"W. David, B. Philipp, B. Sven, Petrova Hanna, F. Sebastian, Schumann Ulrich, Schmidt Bertram, Detert Markus","doi":"10.1109/ESTC.2018.8546376","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546376","url":null,"abstract":"One trend in medical technology is the continuous miniaturization of components, assemblies and complete systems. Such complete systems are functionalized catheters with different sensor and actuator components [1–8]. If even the smallest bottlenecks, for example in blood vessels, are to be reached in the human body, the catheter diameter must be further reduced with the same functionalization. A new approach is chosen, which does not apply the supply and signal lines to the catheter surface or insert them into the existing lumen, but becomes a direct and inseparable part of the catheter. Contacting these conducting tracks with the electronic components is one of the key processes in the manufacture of this type of catheter. A final demonstrator is used for functional testing.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116087021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546474
Yu-Ching Hsu, G. Zeng, J. Xian, S. Belyakov, C. Gourlay
The orientation of Cu6Sn5 in the reaction layer can influence the electrical conductivity and mechanical properties of solder joints. This paper explores the role of Ni on the growth orientation of the Cu6Sn5 layer on Cu and Ni substrates. The crystallographic texture of the Cu6Sn5 layer is measured by electron backscatter diffraction analysis (EBSD). It is shown that the Cu6Sn5 layer grows with a strong {0001} fibre texture when Sn-3.0Ag-0.5Cu-xNi (wt.%) alloys are soldered to Cu substrates, and that the Cu6Sn5 growth texture changes to a {1010} fibre texture when Sn-3Ag-0.5Cu-xNi (wt.%) is soldered to Ni. The Cu6Sn5 composition and nickel distribution are examined and the thickness, grain size and the growth facets of Cu6Sn5 crystals in the layer are investigated to understand the effects of nickel content on the Cu6Sn5 layer morphology and texture. The results are used to discuss the potential of using Ni as a means to control the texture of the intermetallic layer.
{"title":"Tailoring the Cu6Sn5 layer texture with Ni additions in Sn-Ag-Cu based solder joints","authors":"Yu-Ching Hsu, G. Zeng, J. Xian, S. Belyakov, C. Gourlay","doi":"10.1109/ESTC.2018.8546474","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546474","url":null,"abstract":"The orientation of Cu6Sn5 in the reaction layer can influence the electrical conductivity and mechanical properties of solder joints. This paper explores the role of Ni on the growth orientation of the Cu<inf>6</inf>Sn<inf>5</inf> layer on Cu and Ni substrates. The crystallographic texture of the Cu6Sn5 layer is measured by electron backscatter diffraction analysis (EBSD). It is shown that the Cu<inf>6</inf>Sn<inf>5</inf> layer grows with a strong {0001} fibre texture when Sn-3.0Ag-0.5Cu-xNi (wt.%) alloys are soldered to Cu substrates, and that the Cu6Sn5 growth texture changes to a {1010} fibre texture when Sn-3Ag-0.5Cu-xNi (wt.%) is soldered to Ni. The Cu<inf>6</inf>Sn<inf>5</inf> composition and nickel distribution are examined and the thickness, grain size and the growth facets of Cu<inf>6</inf>Sn<inf>5</inf> crystals in the layer are investigated to understand the effects of nickel content on the Cu<inf>6</inf>Sn<inf>5</inf> layer morphology and texture. The results are used to discuss the potential of using Ni as a means to control the texture of the intermetallic layer.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116134392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546432
I. Ndip, K. Becker, F. Brandenburger, T. H. Le, M. Huhn, J. Bauer, M. Koch, M. Hempel, M. Schneider-Ramelow, K. Lang
We model, design, fabricate and measure bond wire antennas (BWAs) at mmWave frequencies, considering the impact of encapsulation and process variations which occur during fabrication. Our results reveal that BWAs can withstand the fabrication process, and retain their impedance and radiation characteristics, if properly designed. Therefore, we believe that bond wires can be used as antennas for the development of real-world wireless systems.
{"title":"Can Bond Wires really be used as Antennas?","authors":"I. Ndip, K. Becker, F. Brandenburger, T. H. Le, M. Huhn, J. Bauer, M. Koch, M. Hempel, M. Schneider-Ramelow, K. Lang","doi":"10.1109/ESTC.2018.8546432","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546432","url":null,"abstract":"We model, design, fabricate and measure bond wire antennas (BWAs) at mmWave frequencies, considering the impact of encapsulation and process variations which occur during fabrication. Our results reveal that BWAs can withstand the fabrication process, and retain their impedance and radiation characteristics, if properly designed. Therefore, we believe that bond wires can be used as antennas for the development of real-world wireless systems.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116451806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546457
M. Inac, M. Wietstruck, A. Göritz, B. Çetindoğan, C. Baristiran-Kaynak, M. Lisker, A. Krüger, U. Saarow, P. Heinrich, T. Voß, Kasim Altin, M. Kaynak
In this paper, a yield increase on post-grinding of 200 mm wafer level packaging applications is presented. 200 mm wafer level plasma enhanced oxide-oxide direct bonding and wafer grinding are used in the packaging of the wafers. Since the surface conditions of the wafers that are used in the packaging is the most critical point of the wafer bonding and grinding processes, it is focussed to optimizing wafer surfaces to increase the yield. After the optimizations on the surface conditions of the BiCMOS wafer used in the packaging, the 200 mm plasma enhanced wafer to wafer direct bonding yield increases from 0% to 99% and at the same time the post-grinding yield of these wafers increases from 0% to over 90%.
{"title":"The Effect of Surface Optimization on Post-grinding Yield of 200 mm Wafer Level Packaging Applications","authors":"M. Inac, M. Wietstruck, A. Göritz, B. Çetindoğan, C. Baristiran-Kaynak, M. Lisker, A. Krüger, U. Saarow, P. Heinrich, T. Voß, Kasim Altin, M. Kaynak","doi":"10.1109/ESTC.2018.8546457","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546457","url":null,"abstract":"In this paper, a yield increase on post-grinding of 200 mm wafer level packaging applications is presented. 200 mm wafer level plasma enhanced oxide-oxide direct bonding and wafer grinding are used in the packaging of the wafers. Since the surface conditions of the wafers that are used in the packaging is the most critical point of the wafer bonding and grinding processes, it is focussed to optimizing wafer surfaces to increase the yield. After the optimizations on the surface conditions of the BiCMOS wafer used in the packaging, the 200 mm plasma enhanced wafer to wafer direct bonding yield increases from 0% to 99% and at the same time the post-grinding yield of these wafers increases from 0% to over 90%.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122342915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546445
A. Korotkov, V. Loboda, S. Dzyubanenko, E. Bakulin
The article deals with thermoelectric generators (TEG) to be designed for low-power applications, e.g. high temperature object monitoring systems. TEG operating principle is based on the Seebeck effect. The proposed technological process of TEG fabrication and testing results with the output specific power of 0.3–6.2 μW/sq.mm at the temperature range of 25–100 K are described.
{"title":"Fabrication and Testing of MEMS Technology Based Thermoelectric Generator","authors":"A. Korotkov, V. Loboda, S. Dzyubanenko, E. Bakulin","doi":"10.1109/ESTC.2018.8546445","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546445","url":null,"abstract":"The article deals with thermoelectric generators (TEG) to be designed for low-power applications, e.g. high temperature object monitoring systems. TEG operating principle is based on the Seebeck effect. The proposed technological process of TEG fabrication and testing results with the output specific power of 0.3–6.2 μW/sq.mm at the temperature range of 25–100 K are described.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546502
A. Zehri, L. Ye, Johan Liu
Copper is generally considered as an electronic packaging material due to its good electrical, thermal properties and relatively low cost. However, copper needs high processing temperature, which negatively affects the electronics reliability. In this paper, silver nanoparticles sintering is evaluated for the propose to decrease the processing temperature of copper. Different fractions of silver nanoparticles were mixed with 10 ×m Cu powder and sintered at temperatures of 250°C, 300°C, 400°C and 500°C, under low pressures 4MPa and 8MPa, and a high pressure of 100MPa for comparison. Densities from 45% to 94% of the density of bulk Cu have been achieved while the thermal and electrical conductivities have been evaluated and reached a value of around 270W/m.K and 1.41×106 S/m.
{"title":"Low-Temperature Sintering Bimodal Micro Copper- Nano Silver For Electrical Power Devices","authors":"A. Zehri, L. Ye, Johan Liu","doi":"10.1109/ESTC.2018.8546502","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546502","url":null,"abstract":"Copper is generally considered as an electronic packaging material due to its good electrical, thermal properties and relatively low cost. However, copper needs high processing temperature, which negatively affects the electronics reliability. In this paper, silver nanoparticles sintering is evaluated for the propose to decrease the processing temperature of copper. Different fractions of silver nanoparticles were mixed with 10 ×m Cu powder and sintered at temperatures of 250°C, 300°C, 400°C and 500°C, under low pressures 4MPa and 8MPa, and a high pressure of 100MPa for comparison. Densities from 45% to 94% of the density of bulk Cu have been achieved while the thermal and electrical conductivities have been evaluated and reached a value of around 270W/m.K and 1.41×106 S/m.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128832563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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