Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546463
D. Ernst, M. Wild, T. Zerna
Ultrathin sensors are used in a wide range of applications. In the current work an ultrathin sensor for Active Magnetic Bearings (AMB) has to be realized. Previous studies show very good results by the use of thin silicon interposer with a thickness of $50 mu mathrm{m}[1][4]$. With this technology sensor packages thinner than $150 mu mathrm{m}$ have been already realized. First results with thin polyimide interposer are shown in [3]. With this approach the thickness can be reduced down to less than $100 mu mathrm{m}$ in total.With a focus on improving the long-term reliability the process was optimized within the present work. Therefore the metallization of the sensor and the substrate were investigated. On sensor side the chosen material for interconnecting is gold with different thicknesses of 100 nm and 200 nm. On substrate side bare copper is compared with deposited NiAu on that copper. To evaluate the reliability of the sensor packages several test specimen were manufactured. These test specimen were aged afterwards in a temperature shock test (-20 °C, +85 °C; 15 minutes dwell time). As expected, the test specimen with an additional NiAu layer show lower failure rate after aging until 3400 cycles compared to the bare copper. But, there are still early failures before 100 cycles for any substrate-sensor-combination of some 5 %.As an alternative interconnecting technology soldering with SnAgBi solder paste was investigated as well. Therefore sensor dies with a bismuth layer were prepared and soldered onto test specimen. First results promise that this technology is able to be a proper alternative to Flip Chip interconnecting.
超薄传感器有着广泛的应用。在目前的工作中，必须实现用于主动磁轴承(AMB)的超薄传感器。以往的研究表明，使用厚度为$50 mu mathm {m}[1][4]$的薄硅中间体，效果非常好。利用这项技术，已经实现了厚度小于$150 mu math {m}$的传感器封装。薄聚酰亚胺中间体的第一个结果显示在[3]中。通过这种方法，厚度可以减少到小于$100 mu mathm {m}$。在目前的工作中，以提高长期可靠性为重点，对工艺进行了优化。因此，对传感器和衬底的金属化进行了研究。在传感器侧，选择的互连材料是100 nm和200 nm不同厚度的金。在衬底侧，将裸铜与沉积在铜上的NiAu进行了比较。为了评估传感器封装的可靠性，制作了几个试样。这些试样随后在温度冲击试验中老化(-20℃，+85℃;停留时间15分钟)。正如预期的那样，与裸铜相比，添加NiAu层的试样在老化至3400次循环后的故障率较低。但是，对于任何衬底-传感器组合，在100次循环之前仍有大约5%的早期故障。作为一种替代的互连技术，用SnAgBi锡膏进行了焊接研究。因此，制备了带铋层的传感器模具并将其焊接到试样上。初步结果表明，这项技术能够成为倒装芯片互连的合适替代方案。
{"title":"Packaging of Ultrathin Flexible Magnetic Field Sensors with thin Silicon and Polyimide Interposer","authors":"D. Ernst, M. Wild, T. Zerna","doi":"10.1109/ESTC.2018.8546463","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546463","url":null,"abstract":"Ultrathin sensors are used in a wide range of applications. In the current work an ultrathin sensor for Active Magnetic Bearings (AMB) has to be realized. Previous studies show very good results by the use of thin silicon interposer with a thickness of $50 mu mathrm{m}[1][4]$. With this technology sensor packages thinner than $150 mu mathrm{m}$ have been already realized. First results with thin polyimide interposer are shown in [3]. With this approach the thickness can be reduced down to less than $100 mu mathrm{m}$ in total.With a focus on improving the long-term reliability the process was optimized within the present work. Therefore the metallization of the sensor and the substrate were investigated. On sensor side the chosen material for interconnecting is gold with different thicknesses of 100 nm and 200 nm. On substrate side bare copper is compared with deposited NiAu on that copper. To evaluate the reliability of the sensor packages several test specimen were manufactured. These test specimen were aged afterwards in a temperature shock test (-20 °C, +85 °C; 15 minutes dwell time). As expected, the test specimen with an additional NiAu layer show lower failure rate after aging until 3400 cycles compared to the bare copper. But, there are still early failures before 100 cycles for any substrate-sensor-combination of some 5 %.As an alternative interconnecting technology soldering with SnAgBi solder paste was investigated as well. Therefore sensor dies with a bismuth layer were prepared and soldered onto test specimen. First results promise that this technology is able to be a proper alternative to Flip Chip interconnecting.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132934143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546465
K. Keränen, P. Korhonen, T. Happonen, Mikko Paakkolanvaara, Jouni Kangas, K. Rönkä
This paper introduces high throughput processing of hybrid flexible RGB LED displays. Processing consists of conductive tracks printing on PET substrate, verification of printed substrate quality by specific characterization equipment and assembly of individually addressable RGB LEDs on substrate using adhesive bonding process. High throughput in manufacturing of flexible displays is achieved utilizing roll-to-roll processes in all steps of the manufacturing process. Utilization of seamless printing tool doubled printing process throughput compared to traditional printing process requiring two printing tools and steps. Implemented roll-to-roll automated electrical test equipment enabled high throughput testing and verification of printed substrate web functionality. Testing was a very important step to verify that printed wiring on the web fulfilled quality requirements for the assembly process. Required SMD components electrically bonded on substrate with R2R assembly machine by utilizing Isotropic Conductive Adhesive (ICA). In addition, Non-Conductive Adhesive (NCA) utilized to provide mechanical support of component, when flexible system bended to smaller than 20 mm radius. Dispensing process noticed to be the most time consuming process in flexible LED display manufacturing, when numerous adhesive dots applied on the substrate. In order to increase throughput in manufacturing, decrease of time used in dispensing process needed. Throughput increase by a factor of ten was possible to achieve by utilizing high speed dispensing process. Increase of more dispenser units in the dispensing process furthermore increase achievable throughput in the manufacturing process. Two meter long flexible display system demonstrator was designed, manufactured and tested based on processed flexible display element.
{"title":"High throughput R2R printing, testing and assembly processing of flexible RGB LED displays","authors":"K. Keränen, P. Korhonen, T. Happonen, Mikko Paakkolanvaara, Jouni Kangas, K. Rönkä","doi":"10.1109/ESTC.2018.8546465","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546465","url":null,"abstract":"This paper introduces high throughput processing of hybrid flexible RGB LED displays. Processing consists of conductive tracks printing on PET substrate, verification of printed substrate quality by specific characterization equipment and assembly of individually addressable RGB LEDs on substrate using adhesive bonding process. High throughput in manufacturing of flexible displays is achieved utilizing roll-to-roll processes in all steps of the manufacturing process. Utilization of seamless printing tool doubled printing process throughput compared to traditional printing process requiring two printing tools and steps. Implemented roll-to-roll automated electrical test equipment enabled high throughput testing and verification of printed substrate web functionality. Testing was a very important step to verify that printed wiring on the web fulfilled quality requirements for the assembly process. Required SMD components electrically bonded on substrate with R2R assembly machine by utilizing Isotropic Conductive Adhesive (ICA). In addition, Non-Conductive Adhesive (NCA) utilized to provide mechanical support of component, when flexible system bended to smaller than 20 mm radius. Dispensing process noticed to be the most time consuming process in flexible LED display manufacturing, when numerous adhesive dots applied on the substrate. In order to increase throughput in manufacturing, decrease of time used in dispensing process needed. Throughput increase by a factor of ten was possible to achieve by utilizing high speed dispensing process. Increase of more dispenser units in the dispensing process furthermore increase achievable throughput in the manufacturing process. Two meter long flexible display system demonstrator was designed, manufactured and tested based on processed flexible display element.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133273679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546416
F. Windrich, M. Malanin, E. Bittrich, A. Schwarz, K. Eichhorn, B. Voit
Different in-situ methods were utilized to study thin film polyimide layers in the context of low-temperature cure processes <230°. In-situ Fourier Transform Infrared Spectroscopy, temperature dependent Spectroscopic Ellipsometry and Thermal Analytical Methods were used to characterize the degree of imidization, glass transition temperature and thermal stability respectively. The final degree of imidization in the low-temperature cure region depends strongly on the UV induced network formation during the upstream Iithographic process. A higher crosslinking density reduces the degree of imidization from 97.5% for an unexposed layer to 73.2% for higher crosslinked film. Glass transition temperature and thermal stability are significantly reduced in the case of curing temperatures below 230°C. The glass transition temperature is decreased from 240°C to 218°C for cure temperatures of 350°C and 230°C respectively. The yielded film stress is reduced in parallel, which was proved by determination of wafer warpage and bow.
{"title":"In-situ characterization of thin polyimide films used for microelectronic packaging","authors":"F. Windrich, M. Malanin, E. Bittrich, A. Schwarz, K. Eichhorn, B. Voit","doi":"10.1109/ESTC.2018.8546416","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546416","url":null,"abstract":"Different in-situ methods were utilized to study thin film polyimide layers in the context of low-temperature cure processes <230°. In-situ Fourier Transform Infrared Spectroscopy, temperature dependent Spectroscopic Ellipsometry and Thermal Analytical Methods were used to characterize the degree of imidization, glass transition temperature and thermal stability respectively. The final degree of imidization in the low-temperature cure region depends strongly on the UV induced network formation during the upstream Iithographic process. A higher crosslinking density reduces the degree of imidization from 97.5% for an unexposed layer to 73.2% for higher crosslinked film. Glass transition temperature and thermal stability are significantly reduced in the case of curing temperatures below 230°C. The glass transition temperature is decreased from 240°C to 218°C for cure temperatures of 350°C and 230°C respectively. The yielded film stress is reduced in parallel, which was proved by determination of wafer warpage and bow.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123972215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8547202
R. Roucou, R. Rongen, J.J. M Zaal, P. van der Wel
This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.
{"title":"Effect of PCB stack-up on Temperature Cycling Reliability of WLCSP","authors":"R. Roucou, R. Rongen, J.J. M Zaal, P. van der Wel","doi":"10.1109/ESTC.2018.8547202","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8547202","url":null,"abstract":"This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123996862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546446
Oliver Albrecht, H. Wohlrabe, K. Meier, M. Oppermann, T. Zerna
All integrated circuit (IC) packages types designed and buildup using different materials with at least little but partly very different thermal expansion coefficients. Under thermal loading, e.g. board assembly or field conditions, a deformation and shape change from the initial state often occur as warpage. During the board assembly, this warpage can cause failures such as open solder joints and/or shorts of solder joints. This warpage can be measured and quantified as co-planarity. Shadow moiré technique is an accepted and standardized measurement technique to do so. Beside the advantages of this measurement technique, there are also some disadvantages. A special preparation of the test objects is necessary - one has to flatten and to whiten the surface - and the maximum heating gradient is about 0.25 K/s in common equipment for a convection simulation. In this paper we will present a new approach to measure the warpage of IC packages using the in-situ X-ray inspection. Certain package types, such as ball grid arrays (BGA’s), are known to be more susceptible to component warpage. Hence, BGAs will be investigated for demonstration of the capability and limitations of this new in-situ measurement technique.
{"title":"In-situ X-ray Characterization of IC Package Warpage at Elevated Temperatures","authors":"Oliver Albrecht, H. Wohlrabe, K. Meier, M. Oppermann, T. Zerna","doi":"10.1109/ESTC.2018.8546446","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546446","url":null,"abstract":"All integrated circuit (IC) packages types designed and buildup using different materials with at least little but partly very different thermal expansion coefficients. Under thermal loading, e.g. board assembly or field conditions, a deformation and shape change from the initial state often occur as warpage. During the board assembly, this warpage can cause failures such as open solder joints and/or shorts of solder joints. This warpage can be measured and quantified as co-planarity. Shadow moiré technique is an accepted and standardized measurement technique to do so. Beside the advantages of this measurement technique, there are also some disadvantages. A special preparation of the test objects is necessary - one has to flatten and to whiten the surface - and the maximum heating gradient is about 0.25 K/s in common equipment for a convection simulation. In this paper we will present a new approach to measure the warpage of IC packages using the in-situ X-ray inspection. Certain package types, such as ball grid arrays (BGA’s), are known to be more susceptible to component warpage. Hence, BGAs will be investigated for demonstration of the capability and limitations of this new in-situ measurement technique.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124084397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546476
Adeniyi A. Olumide, K. Baishya, Guangming Zhang, D. Braden, D. Harvey
Determining the lifetime of solder joints on area array packaging through non-destructive evaluation subjected to thermomechanical loads is crucial for reliability testing of electronic devices. Circuit board assemblies (CBA) are expose to cyclic changes in temperature. The rate of change, exposure time and thermal excursion limits are dependent upon product application and usage known as ’Mission Life’. The purpose of this study is to evaluate the application of an acoustic micro-imaging (AMI) inspection technique, in monitoring solder joints through lifetime performance. Test boards with various area array packages, different surface finish configurations and substrate thickness were subjected to an accelerated thermal cycling test (ATC). The test profile used was - 40°C to + 85°C with 30 minutes dwell. AMI scanning was performed every 4cycles over a total period of 220cycles, in order to obtain enough adequate failure data at high stress to accurately project (extrapolate) what the cumulative distribution function (CDF) at use will be. The cracks on the solder joints was determined by using statistical analysis to observe the behavior of the joints at the region of interest (ROI) with increase in thermal cycling. The differences in the plot patterns also confirms the variations of frequency intensity levels for different thermal cycles.
{"title":"Non-destructive Evaluation and Life Monitoring of Solder Joints in Area Array Packaging","authors":"Adeniyi A. Olumide, K. Baishya, Guangming Zhang, D. Braden, D. Harvey","doi":"10.1109/ESTC.2018.8546476","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546476","url":null,"abstract":"Determining the lifetime of solder joints on area array packaging through non-destructive evaluation subjected to thermomechanical loads is crucial for reliability testing of electronic devices. Circuit board assemblies (CBA) are expose to cyclic changes in temperature. The rate of change, exposure time and thermal excursion limits are dependent upon product application and usage known as ’Mission Life’. The purpose of this study is to evaluate the application of an acoustic micro-imaging (AMI) inspection technique, in monitoring solder joints through lifetime performance. Test boards with various area array packages, different surface finish configurations and substrate thickness were subjected to an accelerated thermal cycling test (ATC). The test profile used was - 40°C to + 85°C with 30 minutes dwell. AMI scanning was performed every 4cycles over a total period of 220cycles, in order to obtain enough adequate failure data at high stress to accurately project (extrapolate) what the cumulative distribution function (CDF) at use will be. The cracks on the solder joints was determined by using statistical analysis to observe the behavior of the joints at the region of interest (ROI) with increase in thermal cycling. The differences in the plot patterns also confirms the variations of frequency intensity levels for different thermal cycles.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129125404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546353
P. Apte, T. Salmon, Richard Rice, M. Gerber, R. Beica, Jeff Calvert, D. Hemker, Y. Dordi, M. Ranjan, S. Ramalingam, Jaspreet Gandhi, A. Kaviani, S. Mitra, P. Wong, Vincent Lee Stanford, M.R. El-Sabry
The microelectronics industry today faces multiple inflections: increasing technology complexity, emerging dataintensive market drivers like the Internet of Things (IoT) and Artificial Intelligence (AI), and an increasing focus on systemlevel integration & optimization. These inflections challenge the industry to build innovative collaboration models that cut across traditional silos. SEMI has built a collaborative platform specifically to address this challenge by providing early and comprehensive assessment of future technologies (5-8 years out). The first project focused on interconnect materials and integration strategies, which are critical to most computing systems. Specific elements studied here include the increase in resistivity with narrowing wire-widths, supply-chain issues with proposed solutions, and the impact on latency for simple circuit systems. In addition, we also compared a two-dimensional (2D) system with an interposer-based system (2.5D) to quantify the impact of the latter on the energy-delay product for various applications.
{"title":"Future Interconnect Materials and System Integration Strategies for Data-Intensive Applications","authors":"P. Apte, T. Salmon, Richard Rice, M. Gerber, R. Beica, Jeff Calvert, D. Hemker, Y. Dordi, M. Ranjan, S. Ramalingam, Jaspreet Gandhi, A. Kaviani, S. Mitra, P. Wong, Vincent Lee Stanford, M.R. El-Sabry","doi":"10.1109/ESTC.2018.8546353","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546353","url":null,"abstract":"The microelectronics industry today faces multiple inflections: increasing technology complexity, emerging dataintensive market drivers like the Internet of Things (IoT) and Artificial Intelligence (AI), and an increasing focus on systemlevel integration & optimization. These inflections challenge the industry to build innovative collaboration models that cut across traditional silos. SEMI has built a collaborative platform specifically to address this challenge by providing early and comprehensive assessment of future technologies (5-8 years out). The first project focused on interconnect materials and integration strategies, which are critical to most computing systems. Specific elements studied here include the increase in resistivity with narrowing wire-widths, supply-chain issues with proposed solutions, and the impact on latency for simple circuit systems. In addition, we also compared a two-dimensional (2D) system with an interposer-based system (2.5D) to quantify the impact of the latter on the energy-delay product for various applications.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115876035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546415
Wenhao Li, T. Christiansen, B. Iversen, J. Watkins
The realization of autonomous IOT sensors and devices will require the development of high performance microbatteries. Though numerous microfabrication methods lead to successful creation of sub-millimeter scale electrodes, practical approaches that provide cost-effective nanoscale resolution for energy storage devices remain elusive. We have developed an approach for the direct imprint patterning of crystalline metal oxides using a soft polymer master and inks containing high concentrations of crystalline nanoparticles dispersed in solvent and/or in sol-gel precursors to a desired inorganic phase wherein high aspect ratio nanostructures and sub-100 nm features are easily realized. The technique is further extended to stack the nanostructures by deploying a layer-by-layer imprint strategy. Here we illustrate the utility of this direct patterning technique by the fabrication of high-performance TiO2 nanoelectrode logpile arrays for lithium-ion microbattery anodes and by the fabrication of a fully integrated lithium-ion microbattery made from LiMn2O4Li4Ti5O12 nanoparticles and gel polymer electrolyte. For the TiO2 anode structures, the critical electrode dimension is below 200 nm, which enables the structure to possess favorable rate capability even under discharging current density as high as 5000 mAg-1. By sequential imprinting, electrodes with three-dimensional (3D) woodpile architecture were readily fabricated. The height of architecture can be easily controlled by the number of stacked layers while a constant surface-to-volume ratio is maintained resulting in a proportional increase of areal capacity with the number of stacked layers. The combination leads to efficient use of the material and the resultant specific capacity (250.9 mAhg-1) is amongst the highest reported. The fully integrated 3D microbattery is fabricated by first imprinting a LiMn2O4 cathode grid array followed by coating the grid array with a polymer separator and then backfilling the structure with a Li4Ti5O12 nanoparticles to form the anode. The full cell battery is shown to exhibit an attractive combination of high energy density, superior capacity retention (40% at 300 C) and high-power density (855.5 μWcm-2μm-1), comparable to some of the best microsupercapacitors. The fabrication strategy proposed here can also be applied to other electroactive materials for use in energy storage systems.
{"title":"High Performance Microbatteries for Integrated Power via Nanoimprinting of 3-D Electrodes","authors":"Wenhao Li, T. Christiansen, B. Iversen, J. Watkins","doi":"10.1109/ESTC.2018.8546415","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546415","url":null,"abstract":"The realization of autonomous IOT sensors and devices will require the development of high performance microbatteries. Though numerous microfabrication methods lead to successful creation of sub-millimeter scale electrodes, practical approaches that provide cost-effective nanoscale resolution for energy storage devices remain elusive. We have developed an approach for the direct imprint patterning of crystalline metal oxides using a soft polymer master and inks containing high concentrations of crystalline nanoparticles dispersed in solvent and/or in sol-gel precursors to a desired inorganic phase wherein high aspect ratio nanostructures and sub-100 nm features are easily realized. The technique is further extended to stack the nanostructures by deploying a layer-by-layer imprint strategy. Here we illustrate the utility of this direct patterning technique by the fabrication of high-performance TiO2 nanoelectrode logpile arrays for lithium-ion microbattery anodes and by the fabrication of a fully integrated lithium-ion microbattery made from LiMn2O4Li4Ti5O12 nanoparticles and gel polymer electrolyte. For the TiO2 anode structures, the critical electrode dimension is below 200 nm, which enables the structure to possess favorable rate capability even under discharging current density as high as 5000 mAg-1. By sequential imprinting, electrodes with three-dimensional (3D) woodpile architecture were readily fabricated. The height of architecture can be easily controlled by the number of stacked layers while a constant surface-to-volume ratio is maintained resulting in a proportional increase of areal capacity with the number of stacked layers. The combination leads to efficient use of the material and the resultant specific capacity (250.9 mAhg-1) is amongst the highest reported. The fully integrated 3D microbattery is fabricated by first imprinting a LiMn2O4 cathode grid array followed by coating the grid array with a polymer separator and then backfilling the structure with a Li4Ti5O12 nanoparticles to form the anode. The full cell battery is shown to exhibit an attractive combination of high energy density, superior capacity retention (40% at 300 C) and high-power density (855.5 μWcm-2μm-1), comparable to some of the best microsupercapacitors. The fabrication strategy proposed here can also be applied to other electroactive materials for use in energy storage systems.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115964501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546385
P. Choudhury, S. Telu, Anilesh Kumar, M. Ribas, S. Sarkar
Increased complexity of interconnection metallurgies, and additional demand for higher functionality and performance have been driving novel designs and electronics miniaturization. Consequently, higher I/O’s density, finer pitches and smaller package sizes are also changing the requirements of Pb-free solder alloys. Hence, there is a need for solder alloys with thermal and mechanical reliability better than SAC305, but with lower, similar or higher melting temperatures, depending on the application. In this paper, we characterize various high reliability solder alloys using uniaxial tensile tests (at different temperatures and strain rates) and creep tests. Alloying additions are used for controlling the growth of intermetallic compounds and microstructure strengthening. Major additions impact the melting behavior and the bulk mechanical properties, whereas minor alloying additions influence the diffusion kinetics and have significant impact on their thermal reliability. The uniform distribution of intermetallics minimizes dislocation motion and deformation, resulting in alloy strengthening.Compared to SAC305, the high and ultra-high reliability alloys presented here show superior mechanical properties. The effect of temperature and strain rate on the mechanical behavior of these alloys are investigated by uniaxial tensile tests at room temperature and 150°C, and strain rates from 10^-4 to 5/s. Deformation during thermal cycling up to 150°C is expected to be controlled by creep, due to the high homologous temperature. Thus, high temperature creep test is used for estimating thermomechanical properties and longer reliability of these alloys in actual usage. As the melting behavior of these alloys cover a wide range of melting temperatures, they can be used in various applications, such as assembly of heat sensitive packages, automotive under-the-hood, semiconductors, LEDs and power electronics.
{"title":"High Reliability Lead-free Alloys for Performance-Critical Applications","authors":"P. Choudhury, S. Telu, Anilesh Kumar, M. Ribas, S. Sarkar","doi":"10.1109/ESTC.2018.8546385","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546385","url":null,"abstract":"Increased complexity of interconnection metallurgies, and additional demand for higher functionality and performance have been driving novel designs and electronics miniaturization. Consequently, higher I/O’s density, finer pitches and smaller package sizes are also changing the requirements of Pb-free solder alloys. Hence, there is a need for solder alloys with thermal and mechanical reliability better than SAC305, but with lower, similar or higher melting temperatures, depending on the application. In this paper, we characterize various high reliability solder alloys using uniaxial tensile tests (at different temperatures and strain rates) and creep tests. Alloying additions are used for controlling the growth of intermetallic compounds and microstructure strengthening. Major additions impact the melting behavior and the bulk mechanical properties, whereas minor alloying additions influence the diffusion kinetics and have significant impact on their thermal reliability. The uniform distribution of intermetallics minimizes dislocation motion and deformation, resulting in alloy strengthening.Compared to SAC305, the high and ultra-high reliability alloys presented here show superior mechanical properties. The effect of temperature and strain rate on the mechanical behavior of these alloys are investigated by uniaxial tensile tests at room temperature and 150°C, and strain rates from 10^-4 to 5/s. Deformation during thermal cycling up to 150°C is expected to be controlled by creep, due to the high homologous temperature. Thus, high temperature creep test is used for estimating thermomechanical properties and longer reliability of these alloys in actual usage. As the melting behavior of these alloys cover a wide range of melting temperatures, they can be used in various applications, such as assembly of heat sensitive packages, automotive under-the-hood, semiconductors, LEDs and power electronics.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117283371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546449
Dr. Etienne Hirt, Klaus Ruzicka
Space applications demand highly reliable and low weight systems. Three-dimensional moulded interconnect device (3D-MID) processes have the potential to fulfil the requirements by combining the (electronic) packaging with routing and mechanical structure. In this paper 3D-MID technology is reviewed, most promising techniques identified and test vehicles are investigated with the focus on space usage within the ESA Artes 5.1 program.
空间应用需要高可靠性和低重量的系统。三维模压互连器件(3D-MID)工艺通过将(电子)封装与布线和机械结构相结合，具有满足要求的潜力。本文回顾了3D-MID技术，确定了最有前途的技术，并对测试车辆进行了调查，重点是ESA Artes 5.1计划中的空间使用情况。
{"title":"3D-MID for Space","authors":"Dr. Etienne Hirt, Klaus Ruzicka","doi":"10.1109/ESTC.2018.8546449","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546449","url":null,"abstract":"Space applications demand highly reliable and low weight systems. Three-dimensional moulded interconnect device (3D-MID) processes have the potential to fulfil the requirements by combining the (electronic) packaging with routing and mechanical structure. In this paper 3D-MID technology is reviewed, most promising techniques identified and test vehicles are investigated with the focus on space usage within the ESA Artes 5.1 program.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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