Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546344
W. Steller, F. Windrich, D. Bremner, S. Robertson, R. Mrossko, J. Keller, T. Brunschwiler, G. Schlottig, H. Oppermann, M. Wolf, K. Lang
High operation temperatures are a main impact factor for long-term reliability. An efficient cooling approach is crucial especially for high performance computing processors (HPC). As reference, the “International Technology Roadmap for Semiconductors” (ITRS) predicted a power consumption of about 700W for data center server processors [1]. Different cooling approaches were investigated already [2]. Unfortunately, current solutions are not sufficient to fulfill high thermal HPC specifications. On one hand, the insufficient cooling performance is raising the chip junction temperature over the critical point. On other hand, the high performance requirements (e.g. low latency time, higher bandwidth) force to use 3D-Integration of components, which is additional raising the heat build-up [3, 4, 5]. Therefore, only the direct integration of a cooling approach within the 3D-stack can eliminate the overheating bottleneck at all. The fluidic cooling approach has a high potential to fulfill the requirements for this direct fluidic integration approach [6]. This work shows the integration and realization of microfluidic features (microfluidic channels and fluidic inlets/outlets) into an interposer. Furthermore we present the integration of this fluidic interposer into a System in Package (SiP) in order to realize a dual side chip cooling for a heat dissipation of 672W (168W/cm-2 which correlates with predicted power consumption of data center server processor according ITRS-Roadmap [1].
{"title":"Microfluidic Interposer for High Performance Fluidic Chip Cooling","authors":"W. Steller, F. Windrich, D. Bremner, S. Robertson, R. Mrossko, J. Keller, T. Brunschwiler, G. Schlottig, H. Oppermann, M. Wolf, K. Lang","doi":"10.1109/ESTC.2018.8546344","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546344","url":null,"abstract":"High operation temperatures are a main impact factor for long-term reliability. An efficient cooling approach is crucial especially for high performance computing processors (HPC). As reference, the “International Technology Roadmap for Semiconductors” (ITRS) predicted a power consumption of about 700W for data center server processors [1]. Different cooling approaches were investigated already [2]. Unfortunately, current solutions are not sufficient to fulfill high thermal HPC specifications. On one hand, the insufficient cooling performance is raising the chip junction temperature over the critical point. On other hand, the high performance requirements (e.g. low latency time, higher bandwidth) force to use 3D-Integration of components, which is additional raising the heat build-up [3, 4, 5]. Therefore, only the direct integration of a cooling approach within the 3D-stack can eliminate the overheating bottleneck at all. The fluidic cooling approach has a high potential to fulfill the requirements for this direct fluidic integration approach [6]. This work shows the integration and realization of microfluidic features (microfluidic channels and fluidic inlets/outlets) into an interposer. Furthermore we present the integration of this fluidic interposer into a System in Package (SiP) in order to realize a dual side chip cooling for a heat dissipation of 672W (168W/cm-2 which correlates with predicted power consumption of data center server processor according ITRS-Roadmap [1].","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546402
Malika Tlili, Maina Sinou, Camilla Kärnfelt, D. Bourreau, A. Péden
This paper presents work on micro heat pipe (MHP) fabrication in Low Temperature Cofired Ceramics (LTCC) modules for cooling purpose. The MHPs are fabricated in a 10 layer structure using ESL41020 tape. Different fabrication settings have been tested to minimize swelling and groove deformation. The best result is obtained by using fugitive tape, extended firing profile, and hot lamination at 50°C for 5 minutes with 70 bar pressure.
{"title":"Micro Heat Pipe Design and Fabrication on LTCC","authors":"Malika Tlili, Maina Sinou, Camilla Kärnfelt, D. Bourreau, A. Péden","doi":"10.1109/ESTC.2018.8546402","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546402","url":null,"abstract":"This paper presents work on micro heat pipe (MHP) fabrication in Low Temperature Cofired Ceramics (LTCC) modules for cooling purpose. The MHPs are fabricated in a 10 layer structure using ESL41020 tape. Different fabrication settings have been tested to minimize swelling and groove deformation. The best result is obtained by using fugitive tape, extended firing profile, and hot lamination at 50°C for 5 minutes with 70 bar pressure.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125413653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546492
Rongfeng Luo, Y. Chai, Shengli Ma, Xiaoyuzhang, Feng Ji, Qi Zhong
In this paper, a TSV interposer base SIP for RF applications is proposed. It’s composed of two separate TSV interposers based on high resistivity Si substrate, which is utilized as the substrate and Cap for RF SIP package. Choice of high resistivity Si substrate is intended to relieve RF loss. The one used for SIP package substrate is consisted of Cu TSVs, RF transmission lines and cavities, the cavity is coated with Copper layer inside, populated with electrical grounding Cu TSVs at the bottom surface, surrounded by lines of TSVs, and it’s utilized to accommodate RF microelectronic chips. The other one used for capping is similar to the bottom TSV interposer in structure. The two TSV interposers will be aligned in the final step with the cavities being sealed to form a close room for the inside RF device for improving the property in electromagnetic compatibility. To demonstrate TSV interposer based RF SIP, Process is developed for the TSV interposer. To testify theprocess, a test vehicle is designed and TSV interposer is fabricated, assembled and characterized.
{"title":"A novel TSV interposer based System-in-Package for RF applications","authors":"Rongfeng Luo, Y. Chai, Shengli Ma, Xiaoyuzhang, Feng Ji, Qi Zhong","doi":"10.1109/ESTC.2018.8546492","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546492","url":null,"abstract":"In this paper, a TSV interposer base SIP for RF applications is proposed. It’s composed of two separate TSV interposers based on high resistivity Si substrate, which is utilized as the substrate and Cap for RF SIP package. Choice of high resistivity Si substrate is intended to relieve RF loss. The one used for SIP package substrate is consisted of Cu TSVs, RF transmission lines and cavities, the cavity is coated with Copper layer inside, populated with electrical grounding Cu TSVs at the bottom surface, surrounded by lines of TSVs, and it’s utilized to accommodate RF microelectronic chips. The other one used for capping is similar to the bottom TSV interposer in structure. The two TSV interposers will be aligned in the final step with the cavities being sealed to form a close room for the inside RF device for improving the property in electromagnetic compatibility. To demonstrate TSV interposer based RF SIP, Process is developed for the TSV interposer. To testify theprocess, a test vehicle is designed and TSV interposer is fabricated, assembled and characterized.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122722854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546358
Xiaochen Chen, Han He, L. Ukkonen, J. Virkki
We present passive UHF RFID platforms composed of 3D-printed biodegradable plastic structures and conductive thread. Due to its flexibility, this extremely cost-effective and environmentally friendly wireless platform can be easily embedded into versatile structures. We evaluated the wireless performance of the tag fabricated from conductive thread both on a 3D-printed substrate as well as inside two 3D-printed layers. The read range of the tag on a 3D-printed substrate was around 6 meters between 860-960 MHz. Then, another layer was applied on top of the tag. Thus, the tag was left inside a 3D-printed platform, where it as protected from environmental stresses, such as moisture. The read range of this structure was still 6 meters throughout the global UHF RFID frequency band. Based on these initial results, these platforms show potential for unobtrusive identification and sensing solutions.
{"title":"3D-Printed Eco-Friendly and Cost-Effective Wireless Platforms","authors":"Xiaochen Chen, Han He, L. Ukkonen, J. Virkki","doi":"10.1109/ESTC.2018.8546358","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546358","url":null,"abstract":"We present passive UHF RFID platforms composed of 3D-printed biodegradable plastic structures and conductive thread. Due to its flexibility, this extremely cost-effective and environmentally friendly wireless platform can be easily embedded into versatile structures. We evaluated the wireless performance of the tag fabricated from conductive thread both on a 3D-printed substrate as well as inside two 3D-printed layers. The read range of the tag on a 3D-printed substrate was around 6 meters between 860-960 MHz. Then, another layer was applied on top of the tag. Thus, the tag was left inside a 3D-printed platform, where it as protected from environmental stresses, such as moisture. The read range of this structure was still 6 meters throughout the global UHF RFID frequency band. Based on these initial results, these platforms show potential for unobtrusive identification and sensing solutions.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546500
L. Hou, J. Derakhshandeh, A. Radisic, M. Honore, J. de Coster, V. Cherman, P. Bex, K. Rebibis, G. Beyer, E. Beyne, I. De Wolf
In this work, an in-situ resistance measurement method is proposed to investigate the interfacial solid state reaction of alternative metallurgies, such as Ni and Cu/Ni as UBM materials, with Sn solders. The electrical properties of formed IMC phases for different metallurgies systems are extracted and discussed. Kinetic parameters, such as activation energy and power factor, of Ni/Sn and Cu/Ni/Sn solid-state reaction are extracted from in-situ resistance measurement. Power factor of Ni/Sn and Cu/Ni/Sn kinetic reaction indicate that the IMC evolution behaviors involve bulk diffusion-controlled (the time exponent n = 0.5) for Ni/Sn, while the growth evolution of (Cu,Ni)6Sn5 in Cu/Ni/Sn solid state reaction involves grain-boundary diffusion controlled (the time exponent n = 0.33) from in-situ resistance measurement. This proposed in-situ measurement methodology has the advantages of being quick and accurate to understand and characterize the reaction and phase formation between UBM and solder materials for 3D applications.
{"title":"An in-situ resistance measurement to extract IMC resistivity and kinetic parameter of alternative metallurgies for 3D stacking","authors":"L. Hou, J. Derakhshandeh, A. Radisic, M. Honore, J. de Coster, V. Cherman, P. Bex, K. Rebibis, G. Beyer, E. Beyne, I. De Wolf","doi":"10.1109/ESTC.2018.8546500","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546500","url":null,"abstract":"In this work, an in-situ resistance measurement method is proposed to investigate the interfacial solid state reaction of alternative metallurgies, such as Ni and Cu/Ni as UBM materials, with Sn solders. The electrical properties of formed IMC phases for different metallurgies systems are extracted and discussed. Kinetic parameters, such as activation energy and power factor, of Ni/Sn and Cu/Ni/Sn solid-state reaction are extracted from in-situ resistance measurement. Power factor of Ni/Sn and Cu/Ni/Sn kinetic reaction indicate that the IMC evolution behaviors involve bulk diffusion-controlled (the time exponent n = 0.5) for Ni/Sn, while the growth evolution of (Cu,Ni)6Sn5 in Cu/Ni/Sn solid state reaction involves grain-boundary diffusion controlled (the time exponent n = 0.33) from in-situ resistance measurement. This proposed in-situ measurement methodology has the advantages of being quick and accurate to understand and characterize the reaction and phase formation between UBM and solder materials for 3D applications.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546356
J. Ahmar, E. Wiss, S. Wiese
Cracking of the brittle X7R BaTiO3 ceramic dielectric material is a severe problem in areas where large sized multilayer ceramic capacitors (MLCC) are needed to provide larger capacities or higher dielectric strength for high voltage applications. Therefore the understanding of the crack formation within multilayer ceramic capacitors (MLCC) is an important issue. The paper will describe four-point-bending experiment on MLCCs, which were soldered on a pcb. The experimental design considered existing tests for the qualification of MLCC components. Basing on these considerations a specimen was designed that is able to detect the crack event via an in situ capacitance measurement. For the fabrication of the specimens two types of capacitors were chosen: MLCC 1206 and MLCC 1812. Both were made from an X7R BaTiO3 ceramic dielectric material. The substrate consisted on a 1.6 mm thick FR 4 pcb stripe having the same width as the capacitors. The capacitors were soldered using SnPbAg2, SnAg0.3Cu0.7 and SnAg3.8Cu0.7 solder alloys. After testing all samples were metallographically prepared, to analyze the cracks within the ceramic body of the capacitor by light microscopy. The paper will present the results of these microscopic studies, with regard to the crack shape that was found in the microsections of the tested specimens. The dependence of crack shape on the employed capacitor geometry and on the used solder alloy will be discussed.
{"title":"Flex Cracking of Multilayer Ceramic Capacitors: Experiments on Fracture Propagation","authors":"J. Ahmar, E. Wiss, S. Wiese","doi":"10.1109/ESTC.2018.8546356","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546356","url":null,"abstract":"Cracking of the brittle X7R BaTiO3 ceramic dielectric material is a severe problem in areas where large sized multilayer ceramic capacitors (MLCC) are needed to provide larger capacities or higher dielectric strength for high voltage applications. Therefore the understanding of the crack formation within multilayer ceramic capacitors (MLCC) is an important issue. The paper will describe four-point-bending experiment on MLCCs, which were soldered on a pcb. The experimental design considered existing tests for the qualification of MLCC components. Basing on these considerations a specimen was designed that is able to detect the crack event via an in situ capacitance measurement. For the fabrication of the specimens two types of capacitors were chosen: MLCC 1206 and MLCC 1812. Both were made from an X7R BaTiO3 ceramic dielectric material. The substrate consisted on a 1.6 mm thick FR 4 pcb stripe having the same width as the capacitors. The capacitors were soldered using SnPbAg2, SnAg0.3Cu0.7 and SnAg3.8Cu0.7 solder alloys. After testing all samples were metallographically prepared, to analyze the cracks within the ceramic body of the capacitor by light microscopy. The paper will present the results of these microscopic studies, with regard to the crack shape that was found in the microsections of the tested specimens. The dependence of crack shape on the employed capacitor geometry and on the used solder alloy will be discussed.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546372
K. Honda, Y. Koseki, T. Ogawa, T. Nonaka
The performance of the newly developed film to level the applied pressure among dies in the process of multi dies simultaneous bonding was evaluated. Sintering Ag paste was used as pre-applied connection material. The leveling performance was evaluated by nine dies simultaneous bonding. The height of the dies was intentionally differed one another, which was controlled by a SUS tape insertion between the bonding tool and the dies. The film compensated the height difference of up to 50 $mu$m in the bonding process. The results of the cross sectional observation after the bonding showed that the dense sintered Ag layer was formed uniformly in all dies in spite of with and without the SUS tape insertion on the backsides of the dies.
{"title":"Multi dies simultaneous bonding for power device with the newly developed pressure leveling film","authors":"K. Honda, Y. Koseki, T. Ogawa, T. Nonaka","doi":"10.1109/ESTC.2018.8546372","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546372","url":null,"abstract":"The performance of the newly developed film to level the applied pressure among dies in the process of multi dies simultaneous bonding was evaluated. Sintering Ag paste was used as pre-applied connection material. The leveling performance was evaluated by nine dies simultaneous bonding. The height of the dies was intentionally differed one another, which was controlled by a SUS tape insertion between the bonding tool and the dies. The film compensated the height difference of up to 50 $mu$m in the bonding process. The results of the cross sectional observation after the bonding showed that the dense sintered Ag layer was formed uniformly in all dies in spite of with and without the SUS tape insertion on the backsides of the dies.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/estc.2018.8546332
T. Gottwald, C. Roessle
Hybrid and electrical Drive is bringing momentum to the development of new solutions for high power drives, DC/DC and AC/DC converters. High power means increased challenges for high current and for thermal management of dissipated power as well. The p2 Pack Technology is a real alternative to conventional systems to further improve reliability, power dissipation at lower system complexity and lower cost. It also meets the challenge of minimized installation space due to its low volume. It could be shown that inductances of the switching cells can be less than 1nH. Therefore all application with the need for fast switching, especially wideband gap semiconductors like GaN and SiC can profit from this embedding architecture. With the new p2 Pack Technology a new architecture was developed, which is helpful for very robust, cost efficient and miniaturized high power Inverter configurations.
{"title":"Minimizing Form Factor and Parasitic Inductances of Power Electronic Modules: The p2 Pack Technology","authors":"T. Gottwald, C. Roessle","doi":"10.1109/estc.2018.8546332","DOIUrl":"https://doi.org/10.1109/estc.2018.8546332","url":null,"abstract":"Hybrid and electrical Drive is bringing momentum to the development of new solutions for high power drives, DC/DC and AC/DC converters. High power means increased challenges for high current and for thermal management of dissipated power as well. The p2 Pack Technology is a real alternative to conventional systems to further improve reliability, power dissipation at lower system complexity and lower cost. It also meets the challenge of minimized installation space due to its low volume. It could be shown that inductances of the switching cells can be less than 1nH. Therefore all application with the need for fast switching, especially wideband gap semiconductors like GaN and SiC can profit from this embedding architecture. With the new p2 Pack Technology a new architecture was developed, which is helpful for very robust, cost efficient and miniaturized high power Inverter configurations.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128364905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546493
Jing Wang, Zhaoxia Zhou, Wen-Feng Lin, Changqing Liu, B. Ahmadi, L. Empringham
The present investigation demonstrates a singlestep electrodeposition route for the fabrication of compact copper-based graphene nanoplatelets (GnPs) nanocomposite coatings, with dispersed GnP co-deposition. The effect of cathodic current density on the surface morphology of the deposits was examined. With increasing deposition current densities from 10 to 40 mA/cm2, there seemed to be a gradual increase in the lateral size of co-deposited GnPs and a decrease in their distribution density, along with a progressive decrease in the deposit surface feature. The chemical state of GnP from the sub-surface region of composite coatings was assessed using XPS in conjunction with Ar ion sputtering and found comparable to that of pristine GnPs. The Cu-GnP composite coatings exhibited slightly higher electrical sheet resistance, compared to that of the untreated Cu and pure Cu deposited counterparts.
{"title":"Copper-based Graphene Nanoplatelet Composites as Interconnect for Power Electronics Pacakging","authors":"Jing Wang, Zhaoxia Zhou, Wen-Feng Lin, Changqing Liu, B. Ahmadi, L. Empringham","doi":"10.1109/ESTC.2018.8546493","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546493","url":null,"abstract":"The present investigation demonstrates a singlestep electrodeposition route for the fabrication of compact copper-based graphene nanoplatelets (GnPs) nanocomposite coatings, with dispersed GnP co-deposition. The effect of cathodic current density on the surface morphology of the deposits was examined. With increasing deposition current densities from 10 to 40 mA/cm2, there seemed to be a gradual increase in the lateral size of co-deposited GnPs and a decrease in their distribution density, along with a progressive decrease in the deposit surface feature. The chemical state of GnP from the sub-surface region of composite coatings was assessed using XPS in conjunction with Ar ion sputtering and found comparable to that of pristine GnPs. The Cu-GnP composite coatings exhibited slightly higher electrical sheet resistance, compared to that of the untreated Cu and pure Cu deposited counterparts.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116521381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546389
Akhil Kumar, M. Schulz, S. Sheva, J. Keller, V. Bader, M. Wöhrmann, J. Bauer, D. May, B. Wunderle
We have made advancement towards developing our novel and non-destructive system for in-situ condition monitoring and detection of delamination of interfaces within electronic packages. A matrix of $5 times 5$ solder based Thixels has been designed within each of the 4 Quadrants of a flip chip with a $10 times 10$mm2 Silicon die. Hardware layout based on a FCOB approach was designed. Before the production and assembly of the FCOB along with the testing system, a finite element study was performed to make a feasibility check by using a UBM of SiO2 on the Silicon side. Afterwards, two batches of FCOB assemblies were produced. One set with underfill and the other without. These were then tested upon a multiplexer based self-built measurement system with a software based lock-in algorithm to receive 3 omega output signals. The change in the 3 omega voltage was successfully measured in the Thixel and the results depict a good SNR at the frequency of optimum sensitivity of 500 Hz. However, we are currently able to measure one quadrant at a time and in future have the possibility to extend this to at least two, if not more. Also, with the good SNR value that has been achieved, we can further decrease the measurement time per sensor to less than 1.25 s by varying sampling parameters.
{"title":"Delamination Detection in an Electronic Package by Means of a Newly Developed Delamination Chip Based on Thermal Pixel (Thixel) Array","authors":"Akhil Kumar, M. Schulz, S. Sheva, J. Keller, V. Bader, M. Wöhrmann, J. Bauer, D. May, B. Wunderle","doi":"10.1109/ESTC.2018.8546389","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546389","url":null,"abstract":"We have made advancement towards developing our novel and non-destructive system for in-situ condition monitoring and detection of delamination of interfaces within electronic packages. A matrix of $5 times 5$ solder based Thixels has been designed within each of the 4 Quadrants of a flip chip with a $10 times 10$mm2 Silicon die. Hardware layout based on a FCOB approach was designed. Before the production and assembly of the FCOB along with the testing system, a finite element study was performed to make a feasibility check by using a UBM of SiO2 on the Silicon side. Afterwards, two batches of FCOB assemblies were produced. One set with underfill and the other without. These were then tested upon a multiplexer based self-built measurement system with a software based lock-in algorithm to receive 3 omega output signals. The change in the 3 omega voltage was successfully measured in the Thixel and the results depict a good SNR at the frequency of optimum sensitivity of 500 Hz. However, we are currently able to measure one quadrant at a time and in future have the possibility to extend this to at least two, if not more. Also, with the good SNR value that has been achieved, we can further decrease the measurement time per sensor to less than 1.25 s by varying sampling parameters.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130645121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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