Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences最新文献

With the ongoing digitization, digital circuits have become increasingly present in everyday life. However, as circuits can be faulty, their verification poses a challenging but essential challenge. In contrast to formal verification techniques, simulation techniques fail to fully guarantee the correctness of a circuit. However, due to the exponential complexity of the verification problem, formal verification can fail due to time or space constraints. To overcome this challenge, recently Polynomial Formal Verification (PFV) has been introduced. Here, it has been shown that several circuits and circuit classes can be formally verified in polynomial time and space. In general, these proofs have to be conducted manually, requiring a lot of time. However, in recent research, a method for automated PFV has been proposed, where a proof engine automatically generates human-readable proofs that show the polynomial size of a Binary Decision Diagram (BDD) for a given function. The engine analyses the BDD and finds a pattern, which is then proven by induction. In this article, we formalize the previously presented BDD patterns and propose algorithms for the pattern detection, establishing new possibilities for the automated proof generation for more complex functions. Furthermore, we show an exemplary proof that can be generated using the presented methods.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

The thirst for more efficient computational paradigms has reignited interest in computation in memory (CIM), a burgeoning topic that pivots on the strengths of more versatile logic systems. Surging ahead in this innovative milieu, multi-valued logic systems have been identified as possessing the potential to amplify storage density and computation efficacy. Notably, ternary logic has attracted widespread research owing to its relatively lower computational and storage complexity, offering a promising alternative to the traditional binary logic computation. This study provides insight into the feasibility of ternary logic in the CIM domain using resistive random-access memory (ReRAM) devices. Its multi-level programming capability making it an ideal conduit for the integration of ternary logic. We focus on ternary Łukasiewicz logic because its computational characteristics are highly suitable for mapping logic values with input and output signals. This approach is characterized by voltage-reading-based output for ease of subsequent utilization and computation and validated in 1T1R crossbar arrays in an integrated ReRAM chip (Memory Advanced Demonstrator 200 mm). In addition, the effect of variability of memristive devices on logical computation and the potential for parallel operation are also investigated.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

Sensors for the perception of multimodal stimuli-ranging from the five senses humans possess and beyond-have reached an unprecedented level of sophistication and miniaturization, raising the prospect of making man-made large-scale complex systems that can rival nature a reality. Artificial intelligence (AI) at the edge aims to integrate such sensors with real-time cognitive abilities enabled by recent advances in AI. Such AI progress has only been achieved by using massive computing power which, however, would not be available in most distributed systems of interest. Nature has solved this problem by integrating computing, memory and sensing functionalities in the same hardware so that each part can learn its environment in real time and take local actions that lead to stable global functionalities. While this is a challenging task by itself, it would raise a new set of security challenges when implemented. As in nature, malicious agents can attack and commandeer the system to perform their own tasks. This article aims to define the types of systemic attacks that would emerge, and introduces a multiscale framework for combatting them. A primary thesis is that edge AI systems have to deal with unknown attack strategies that can only be countered in real time using low-touch adaptive learning systems.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

The MiG-V was designed for high-security applications and is the first commercially available logic-locked RISC-V processor on the market. In this context, logic locking was used to protect the RISC-V processor design during the untrusted manufacturing process by using key-driven logic gates to obfuscate the original design. Although this method defends against malicious modifications, such as hardware Trojans, logic locking's impact on the RISC-V processor's data confidentiality during runtime has not been thoroughly examined. In this study, we evaluate the impact of logic locking on data confidentiality. By altering the logic locking key of the MiG-V while running SSL cryptographic algorithms, we identify data leakages resulting from the exploitation of the logic-locking hardware. We show that changing a single bit of the logic locking key can expose 100% of the cryptographic encryption key. This research reveals a critical security flaw in logic locking, highlighting the need for comprehensive security assessments beyond logic-locking key-recovery attacks.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

The advent of in-memory computing has introduced a new paradigm of computation, which offers significant improvements in terms of latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect of the hardware variations and non-idealities of the emerging memory technologies may significantly compromise the accuracy of inferred neural networks and result in malfunctions in safety-critical applications. This article addresses the issue from three different perspectives. First, we describe the technology-related sources of these variations. Then, we propose an architectural-level mitigation strategy that involves the coordinated action of two checksum codes designed to detect and correct errors at runtime. Finally, we optimize the area and latency overhead of the proposed solution by using two accuracy-aware hardware-software co-design techniques. The results demonstrate higher efficiency in mitigating the accuracy degradation of multiple AI algorithms in the context of different technologies compared with state-of-the-art solutions and traditional techniques such as triple modular redundancy. Several configurations of our implementation recover more than 95% of the original accuracy with less than 40% of the area and less than 30% of latency overhead.This article is part of the themed issue 'Emerging technologies for future secure computing platforms'.

Memristive technology mitigates the memory wall issue in von Neumann architectures by enabling in-memory data processing. Unlike traditional complementary metal-oxide semiconductor (CMOS) technology, memristors provide a new paradigm for implementing cryptographic functions and security considerations. While prior research explores memristors for cryptographic functions and side-channel attack vulnerabilities, our study uniquely addresses memristor-oriented countermeasures. We review different memristive crossbar configurations, implement a four-bit S-box cryptographic function, and analyse memristor-oriented hiding and masking techniques using a self-rectifying passive crossbar. Our findings confirm the efficacy of memristor-oriented hiding techniques but highlight limitations in memristor-oriented masked dual-rail pre-charge logic (MDPL) masking methods. Effective MDPL masking depends on specific power consumption conditions, i.e. the power profile of input data '01' and '10' are not clearly distinguishable from '00' and '11', which, however, are not satisfied across various memristive logic families. Despite passing t-tests, xor4Sbox with CRS-based MDPL masking failed stochastic approaches owing to power consumption differences. Our study prioritizes memristor-oriented countermeasures, advancing the understanding of challenges and opportunities in memristive technology for cryptographic functions.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

Resistive random access memory (ReRAM) holds promise for building computing-in-memory (CIM) architectures to execute machine learning (ML) applications. However, existing ReRAM technology faces challenges such as cell and cycle variability, read-disturb and limited endurance, necessitating improvements in devices, algorithms and applications. Understanding the behaviour of ReRAM technologies is crucial for advancement. Existing platforms can either only characterize single cells and do not support CIM operations, or lack a comprehensive software stack for simple system integration. This article introduces NeuroBreakoutBoard (NBB), a versatile, integrable and portable instrumentation platform for ReRAM crossbars. The platform features a software stack enabling experiments via Python from a host PC. In a case study, we demonstrate the capabilities of NBB by conducting diverse experiments on TiN/Ti/HfO₂/TiN cells. Our results show that NBB can characterize individual cells and perform CIM operations with a relative measurement error below 2%.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

Encryption and decryption of data with very low latency and high energy efficiency is desirable in almost every application that deals with sensitive data. The advanced encryption standard (AES) is a widely adopted algorithm in symmetric key cryptography with numerous efficient implementations. Nonetheless, in scenarios involving extensive data processing, the primary limitations on performance and efficiency arise from data movement between memory and the processor, rather than data processing itself. In this article, we present a novel in-memory computing (IMC) approach for AES encryption and key-expansion, and experimentally validate it on an IMC prototype chip based on phase-change memory (PCM) technology. We leverage operators stored in PCM crossbar arrays to achieve the flexibility to tune performance at runtime based on the amount of free storage available in the memory system. In addition, we introduce a method for parallel in-memory polynomial modular multiplication and evaluate the potential of intrinsic stochastic properties of PCM devices for random key generation. We show how to further improve efficiency with minimal additional auxiliary circuitry. To evaluate the performance within a custom-built large-scale in-memory AES system, we design and implement a cycle-accurate simulator that integrates parameters from Spice simulations for detailed latency and energy consumption analysis of the AES algorithm. Our evaluations indicate that our IMC-based AES approach outperforms state-of-the-art methods, achieving speed factor improvements of up to 19.7 at equivalent energy efficiency.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

The increasing demand for processing large volumes of data for machine learning (ML) models has pushed data bandwidth requirements beyond the capability of traditional von Neumann architecture. In-memory computing (IMC) has recently emerged as a promising solution to address this gap by enabling distributed data storage and processing at the micro-architectural level, significantly reducing both latency and energy. In this article, we present In-Memory comPuting architecture based on Y-FlAsh technology for Coalesced Tsetlin machine inference (IMPACT), underpinned on a cutting-edge memory device, Y-Flash, fabricated on a 180 nm complementary metal oxide semiconductor (CMOS) process. Y-Flash devices have recently been demonstrated for digital and analogue memory applications; they offer high yield, non-volatility and low power consumption. IMPACT leverages the Y-Flash array to implement the inference of a novel ML algorithm: coalesced Tsetlin machine (CoTM) based on propositional logic. CoTM utilizes Tsetlin automata (TA) to create Boolean feature selections stochastically across parallel clauses. IMPACT is organized into two computational crossbars for storing the TA and weights. Through validation on the MNIST dataset, IMPACT achieved [Formula: see text] accuracy. IMPACT demonstrated improvements in energy efficiency, e.g. factors of 2.23 over CNN-based ReRAM, 2.46 over neuromorphic using NOR-Flash and 2.06 over DNN-based phase-change memory (PCM), suited for modern ML inference applications.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.