Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305233
M. Thomason, C. Billman, B. Greenwood, B. Williams, C. Belisle, F. Bauwens
Developing reliable high voltage transistors requires consistent manufacturing of critical architectural parameters within the device over time and with various design configurations. Structural parameters that directly affect reliability are especially crucial to delivering robust parts to the market place. In this paper it is shown that the nwell and pwell photo critical dimension (CD)'s for a 25 V lateral field n-type transistor (LFNDMOS), are significant control parameters for minimizing hot-carrier degradation and thus, improving the reliability. Variations in manufacturing photo CD's, such as, the edge proximity of the nwell (used as the extended drain) and the pwell (used as the body) to the bird's beak (BB) was found to directly effect interface trap formation and hot-carrier degradation. By understanding these critical structural parameters a more reliable manufacturing process can be developed
{"title":"Lithography CD Variation effects on LFNDMOS Transistor Hot-Carrier Degradation","authors":"M. Thomason, C. Billman, B. Greenwood, B. Williams, C. Belisle, F. Bauwens","doi":"10.1109/IRWS.2006.305233","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305233","url":null,"abstract":"Developing reliable high voltage transistors requires consistent manufacturing of critical architectural parameters within the device over time and with various design configurations. Structural parameters that directly affect reliability are especially crucial to delivering robust parts to the market place. In this paper it is shown that the nwell and pwell photo critical dimension (CD)'s for a 25 V lateral field n-type transistor (LFNDMOS), are significant control parameters for minimizing hot-carrier degradation and thus, improving the reliability. Variations in manufacturing photo CD's, such as, the edge proximity of the nwell (used as the extended drain) and the pwell (used as the body) to the bird's beak (BB) was found to directly effect interface trap formation and hot-carrier degradation. By understanding these critical structural parameters a more reliable manufacturing process can be developed","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"45 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113974049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305202
Jih-San Li, Main-gwo Chen, P. Juan, K. Su
In this study, the delay-dependent negative bias temperature instability (NBTI) was performed and a power law relationship between the lifetime and the delay time was found. The AC lifetimes under dynamic stress as a function of duty cycle and frequency were also investigated. It was observed that the time-to-failure (TTF) has an exponential dependence on duty ratio and a power law dependency on frequency. An accurate AC model incorporated with duty ratio and frequency is proposed. The mechanisms due to the effect of recovery are discussed
{"title":"Effects of Delay Time and AC Factors on Negative Bias Temperature Instability of PMOSFETs","authors":"Jih-San Li, Main-gwo Chen, P. Juan, K. Su","doi":"10.1109/IRWS.2006.305202","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305202","url":null,"abstract":"In this study, the delay-dependent negative bias temperature instability (NBTI) was performed and a power law relationship between the lifetime and the delay time was found. The AC lifetimes under dynamic stress as a function of duty cycle and frequency were also investigated. It was observed that the time-to-failure (TTF) has an exponential dependence on duty ratio and a power law dependency on frequency. An accurate AC model incorporated with duty ratio and frequency is proposed. The mechanisms due to the effect of recovery are discussed","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122628861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305236
Shuang-Yuan Chen, C. Tu, Jung-Chun Lin, Po-Wei Kao, Wen-Cheng Lin, Z. Jhou, S. Chou, J. Ko, H. Haung
Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures
{"title":"Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs","authors":"Shuang-Yuan Chen, C. Tu, Jung-Chun Lin, Po-Wei Kao, Wen-Cheng Lin, Z. Jhou, S. Chou, J. Ko, H. Haung","doi":"10.1109/IRWS.2006.305236","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305236","url":null,"abstract":"Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305220
A. Martin, C. Sior, C. Schlunder
The main goal of this work is to present a sensitive method for the testing of PID which is applicable to all oxide thicknesses and types of MOS transistors
本工作的主要目标是提出一种适用于所有氧化物厚度和类型的MOS晶体管的PID灵敏测试方法
{"title":"Fast productive WLR characterisation methods of plasma induced damage of thin and thick MOS gate oxides","authors":"A. Martin, C. Sior, C. Schlunder","doi":"10.1109/IRWS.2006.305220","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305220","url":null,"abstract":"The main goal of this work is to present a sensitive method for the testing of PID which is applicable to all oxide thicknesses and types of MOS transistors","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134184052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305240
J.Y.C. Yang, Cheng-li Lin, C. Hu, Ju-ping Chen, C. Kao, K. Su
Interface defect density on 90 nm PFET ultra-thin gate dielectric is checked by using a near flat band SILC in this work. Although power-law model has been successfully adopted to explain the gate oxide breakdown phenomenon below 2.0nm in industry field (Wu et al., 2000), (Ohgata et al., 2005), (Naoyoshi et al., 2003) and (Mariko et al., 2001), a correlation between power-law model with interface defect density has been made first time in this investigation. Critical defect density (NBD) shows strong correlation with power-law exponent factor due to SILC leakage increasing ratio (dJ/J0) dominate dielectric breakdown on our decouple plasma nitridation (DPN) power splits. A preliminary model is proposed to explain the nitridation-induced oxide reliability degradation mechanism. Since larger concentration of Nitrogen incorporation will cause excess interface states, those energy levels may reduce proton tunneling barrier in anode hydrogen release (AHR) behavior, thus further enhance AHR effect to degrade oxide breakdown strength
本文采用近平带硅原子阱检测了90 nm pet超薄栅极介质上的界面缺陷密度。虽然幂律模型已经在工业领域成功地解释了2.0nm以下栅极氧化物击穿现象(Wu et al.， 2000)、(Ohgata et al.， 2005)、(Naoyoshi et al.， 2003)和(Mariko et al.， 2001)，但本研究首次将幂律模型与界面缺陷密度联系起来。临界缺陷密度(NBD)与幂律指数因子有很强的相关性，因为硅烷泄漏增加比(dJ/J0)在去耦等离子体氮化(DPN)功率分裂中占主导地位。提出了一个初步的模型来解释氮化引起的氧化物可靠性退化机制。较大的氮掺入浓度会产生过量的界面态，这些能级可能会降低阳极氢释放(AHR)行为中的质子隧穿势垒，从而进一步增强AHR效应，降低氧化物击穿强度
{"title":"The Correlation of Interface Defect Density and Power-Law Exponent Factor on Ultra-thin Gate Dielectric Reliability","authors":"J.Y.C. Yang, Cheng-li Lin, C. Hu, Ju-ping Chen, C. Kao, K. Su","doi":"10.1109/IRWS.2006.305240","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305240","url":null,"abstract":"Interface defect density on 90 nm PFET ultra-thin gate dielectric is checked by using a near flat band SILC in this work. Although power-law model has been successfully adopted to explain the gate oxide breakdown phenomenon below 2.0nm in industry field (Wu et al., 2000), (Ohgata et al., 2005), (Naoyoshi et al., 2003) and (Mariko et al., 2001), a correlation between power-law model with interface defect density has been made first time in this investigation. Critical defect density (NBD) shows strong correlation with power-law exponent factor due to SILC leakage increasing ratio (dJ/J0) dominate dielectric breakdown on our decouple plasma nitridation (DPN) power splits. A preliminary model is proposed to explain the nitridation-induced oxide reliability degradation mechanism. Since larger concentration of Nitrogen incorporation will cause excess interface states, those energy levels may reduce proton tunneling barrier in anode hydrogen release (AHR) behavior, thus further enhance AHR effect to degrade oxide breakdown strength","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128020299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305199
C. Schlunder, W. Heinrigs, W. Gustin, H. Reisinger
The NBTI recovery phenomenon leads to a fast reduction of the stress induced electrical device parameter degradation after end of stress. Delay times between device-stress and -characterization within NBTI-experiments affect the measurement values of degradation. This work discusses the impact of these delays on lifetime prediction for technology qualifications. For this reason we investigate delay times from 1mus up to 60s and stress times from 100ms up to 250000s. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations
{"title":"On the impact of the NBTI recovery phenomenon on lifetime prediction of modern p-MOSFETs","authors":"C. Schlunder, W. Heinrigs, W. Gustin, H. Reisinger","doi":"10.1109/IRWS.2006.305199","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305199","url":null,"abstract":"The NBTI recovery phenomenon leads to a fast reduction of the stress induced electrical device parameter degradation after end of stress. Delay times between device-stress and -characterization within NBTI-experiments affect the measurement values of degradation. This work discusses the impact of these delays on lifetime prediction for technology qualifications. For this reason we investigate delay times from 1mus up to 60s and stress times from 100ms up to 250000s. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115950728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305237
W. Chang, M. Ker, T. Lai, Tien-Hao Tang, K. Su
The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased
在硅片上研究了40 v CMOS工艺中器件结构和布局参数对ESD稳健性的影响。从实验结果来看，漏极区没有漂移植入的高压mosfet比漏极区有漂移植入的高压mosfet具有更好的tlp测量It2和ESD鲁棒性。此外，HV mosfet的It2和ESD水平可以随着漏极扩散到多栅极的布局间距的增加而增加
{"title":"ESD Robustness of 40-V CMOS Devices With/Without Drift Implant","authors":"W. Chang, M. Ker, T. Lai, Tien-Hao Tang, K. Su","doi":"10.1109/IRWS.2006.305237","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305237","url":null,"abstract":"The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116221154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305214
A. Haggag, P. Kuhn, P. Ingersoll, Chi-Nan Li, T. Harp, A. Hoefler, D. Burnett, K. Baker, Ko-Min Chang
We discuss flash oxide scalability model of various program/erase methods within the constraint of high performance (fast program/erase times) and high reliability (data retention). We show that HCI programming with FN channel erase (HCI/CE) offers the best scalable solution compared to other common methods, HCI programming with FN edge erase (HCI/EE) and uniform channel FN program erase (UCPE)
{"title":"Flash Oxide Scalability Model and Impact of Program/Erase Method","authors":"A. Haggag, P. Kuhn, P. Ingersoll, Chi-Nan Li, T. Harp, A. Hoefler, D. Burnett, K. Baker, Ko-Min Chang","doi":"10.1109/IRWS.2006.305214","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305214","url":null,"abstract":"We discuss flash oxide scalability model of various program/erase methods within the constraint of high performance (fast program/erase times) and high reliability (data retention). We show that HCI programming with FN channel erase (HCI/CE) offers the best scalable solution compared to other common methods, HCI programming with FN edge erase (HCI/EE) and uniform channel FN program erase (UCPE)","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125926642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305221
O. Aubel, T. Sullivan, D. Massey, T. Lee, T. Merrill, S. Polchlopek, A. Strong
Reliability monitoring is an important part of process control in high volume production. For the back end of line (BEOL), a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation (Schuster, 2001). In this work we present practical normalization procedures to ensure an appropriate wafer to wafer comparison which is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements have been performed on a commercially available 300mm multi-side probe station, using custom-made software to implement the current ramp and resistance measurement. The test conditions were achieved through Joule heating; the test structures used were 800mum long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14mum to 10mum. After several normalization steps described in this paper we found a strong activation energy dependence on line width. This dependence was linked to issues in temperature investigation using a constant TCR value. Additionally we found a simple way to estimate the current density exponent by optimizing the Arrhenius relation. Overall a comprehensive guideline for constant current WL-EM is presented
{"title":"Practical considerations for Wafer-Level Electromigration Monitoring in high volume production","authors":"O. Aubel, T. Sullivan, D. Massey, T. Lee, T. Merrill, S. Polchlopek, A. Strong","doi":"10.1109/IRWS.2006.305221","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305221","url":null,"abstract":"Reliability monitoring is an important part of process control in high volume production. For the back end of line (BEOL), a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation (Schuster, 2001). In this work we present practical normalization procedures to ensure an appropriate wafer to wafer comparison which is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements have been performed on a commercially available 300mm multi-side probe station, using custom-made software to implement the current ramp and resistance measurement. The test conditions were achieved through Joule heating; the test structures used were 800mum long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14mum to 10mum. After several normalization steps described in this paper we found a strong activation energy dependence on line width. This dependence was linked to issues in temperature investigation using a constant TCR value. Additionally we found a simple way to estimate the current density exponent by optimizing the Arrhenius relation. Overall a comprehensive guideline for constant current WL-EM is presented","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126291359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305248
Jia-Lin Wu, C. Kao, Hua-Ching Chien, Tzung-Kuen Tsai, Chih-Yuan Lee, Chien-Wei Liao, Chung-Yu Chou, M. Yang
The reliability characteristics of polysilicon-oxide-nitride-oxide -silicon (SONOS) devices with different thin tunnel oxides are studied. The tunnel oxynitride growth in a pure N2O ambient with high temperature has better performance than in a dry oxidation with N2 annealing treatment including leakage current, programming speed, read disturb and retention. Besides, the surface roughness and interface states between tunnel oxide and Si substrate are also observed by atomic force microscope (AFM) technique and charge-pumping method to evaluate interfacial nitrogen incorporation. The results show that the reliability of data retention obtained a significant improvement while maintaining good programming/erase performance and can provide a straightforward way of reliability improvement for future flash memory application
{"title":"Retention Reliability Improvement of SONOS Non-volatile Memory with N2O Oxidation Tunnel Oxide","authors":"Jia-Lin Wu, C. Kao, Hua-Ching Chien, Tzung-Kuen Tsai, Chih-Yuan Lee, Chien-Wei Liao, Chung-Yu Chou, M. Yang","doi":"10.1109/IRWS.2006.305248","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305248","url":null,"abstract":"The reliability characteristics of polysilicon-oxide-nitride-oxide -silicon (SONOS) devices with different thin tunnel oxides are studied. The tunnel oxynitride growth in a pure N2O ambient with high temperature has better performance than in a dry oxidation with N2 annealing treatment including leakage current, programming speed, read disturb and retention. Besides, the surface roughness and interface states between tunnel oxide and Si substrate are also observed by atomic force microscope (AFM) technique and charge-pumping method to evaluate interfacial nitrogen incorporation. The results show that the reliability of data retention obtained a significant improvement while maintaining good programming/erase performance and can provide a straightforward way of reliability improvement for future flash memory application","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"513 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131704515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：