Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305212
C. Guérin, V. Huard, A. Bravaix, M. Denais
This work shows that channel hot carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (Vg). At low Vg, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high Vg, the second degradation mode becomes worse depending on Vd. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of charge pumping (CP) and direct current current voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation
{"title":"Impact of Hot Carrier Degradation Modes on I/O nMOSFETS Aging Prediction","authors":"C. Guérin, V. Huard, A. Bravaix, M. Denais","doi":"10.1109/IRWS.2006.305212","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305212","url":null,"abstract":"This work shows that channel hot carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (Vg). At low Vg, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high Vg, the second degradation mode becomes worse depending on Vd. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of charge pumping (CP) and direct current current voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115670181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305243
Charles Slayman, Manny Ma, Scott Lindley
History has shown that DRAM technology shrinks as the server memory density grows and, at the same time, user expectation of system uptime increases. Given this, new mitigation techniques are required to reduce the impact of DRAM faults on server reliability, availability, and serviceability (RAS). This study shows the trade-offs in the effectiveness of two commonly used error correction codes (ECC) and two dynamic memory reconfiguration (DMR) schemes with various types of anticipated memory failures. This study proposes a "RAS intelligent" way to look at device reliability as DRAM technology scales below 100nm
{"title":"Impact of Error Correction Code and Dynamic Memory Reconfiguration on High-Reliability/Low-Cost Server Memory","authors":"Charles Slayman, Manny Ma, Scott Lindley","doi":"10.1109/IRWS.2006.305243","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305243","url":null,"abstract":"History has shown that DRAM technology shrinks as the server memory density grows and, at the same time, user expectation of system uptime increases. Given this, new mitigation techniques are required to reduce the impact of DRAM faults on server reliability, availability, and serviceability (RAS). This study shows the trade-offs in the effectiveness of two commonly used error correction codes (ECC) and two dynamic memory reconfiguration (DMR) schemes with various types of anticipated memory failures. This study proposes a \"RAS intelligent\" way to look at device reliability as DRAM technology scales below 100nm","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116051219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305239
Yuhao Luo, D. Nayak, J. Lee, D. Gitlin, C. T. Tsai
Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and both pass product specs. Wafer level device reliability was also studied for NBTI, HCI and oxide TDDB. Wafer level NBTI is well correlated with product level HTOL degradation. It is confirmed that USP technology improves product performance significantly, and the product reliability is comparable to that of baseline technology
{"title":"Reliability of Strain-Si FPGA Product Fabricated by Novel Ultimate Spacer Process","authors":"Yuhao Luo, D. Nayak, J. Lee, D. Gitlin, C. T. Tsai","doi":"10.1109/IRWS.2006.305239","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305239","url":null,"abstract":"Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and both pass product specs. Wafer level device reliability was also studied for NBTI, HCI and oxide TDDB. Wafer level NBTI is well correlated with product level HTOL degradation. It is confirmed that USP technology improves product performance significantly, and the product reliability is comparable to that of baseline technology","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132273645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305238
N. Wakai, Y. Kobira, T. Oishi, S. Yamasaki, H. Egawa
An effective procedure to determine the burn-in acceleration factors for 90 nm system LSI are discussed in this paper. The relationship among yield, defect density, and reliability, is well known and well documented for defect mechanisms. In particular, it is important to determine the suitable acceleration factors for temperature and voltage to estimate the exact burn-in conditions needed to screen these defects. The approach in this paper is found to be useful for recent Cu-processes which are difficult to control from a defectivity standpoint. Performing an evaluation with test vehicles of 90nm and 130nm technology, the following acceleration factors were obtained, Ea ges 0.9eV and gamma (Gamma) ges - 5.85. In addition, it was determined that a lower defect density gave a lower Weibull shape parameter. As a result of failure analysis, it is found that the main failures in these technologies were caused by particles, and their Weibull shape parameter "m" was changed depending of the related defect density. These factors can be applied for an immature time period where the process and products have failure mechanisms dominated by defects. Thus, an effective burn-in is possible with classification from the standpoint of defect density, even from a period of technology immaturity
{"title":"Burn-In Acceleration Considerations in 90nm System LSI","authors":"N. Wakai, Y. Kobira, T. Oishi, S. Yamasaki, H. Egawa","doi":"10.1109/IRWS.2006.305238","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305238","url":null,"abstract":"An effective procedure to determine the burn-in acceleration factors for 90 nm system LSI are discussed in this paper. The relationship among yield, defect density, and reliability, is well known and well documented for defect mechanisms. In particular, it is important to determine the suitable acceleration factors for temperature and voltage to estimate the exact burn-in conditions needed to screen these defects. The approach in this paper is found to be useful for recent Cu-processes which are difficult to control from a defectivity standpoint. Performing an evaluation with test vehicles of 90nm and 130nm technology, the following acceleration factors were obtained, Ea ges 0.9eV and gamma (Gamma) ges - 5.85. In addition, it was determined that a lower defect density gave a lower Weibull shape parameter. As a result of failure analysis, it is found that the main failures in these technologies were caused by particles, and their Weibull shape parameter \"m\" was changed depending of the related defect density. These factors can be applied for an immature time period where the process and products have failure mechanisms dominated by defects. Thus, an effective burn-in is possible with classification from the standpoint of defect density, even from a period of technology immaturity","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126198894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305215
G. Tao, H. Chauveau, S. Nath
Most of the flash endurance results reported so far are typically in a temperature range of -40degC to +85degC, while devices in automotive "under the hood" applications can experience up to 150degC. This paper reports the temperature dependence of FN/FN based flash memories. Experiments have been carried out on 2.7Mb test memory arrays with temperatures up to 150degC. An empirical model has been developed to describe the temperature dependent degradation of the Vt window. This model fits the experimental data over the whole temperature range, and the endurance performance with single shot P/E cycles exceeds 1 million cycles
{"title":"Experimental Study of Temperature Dependence of Program/Erase Endurance of Embedded Flash Memories with 2T-FNFN Device Architecture","authors":"G. Tao, H. Chauveau, S. Nath","doi":"10.1109/IRWS.2006.305215","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305215","url":null,"abstract":"Most of the flash endurance results reported so far are typically in a temperature range of -40degC to +85degC, while devices in automotive \"under the hood\" applications can experience up to 150degC. This paper reports the temperature dependence of FN/FN based flash memories. Experiments have been carried out on 2.7Mb test memory arrays with temperatures up to 150degC. An empirical model has been developed to describe the temperature dependent degradation of the Vt window. This model fits the experimental data over the whole temperature range, and the endurance performance with single shot P/E cycles exceeds 1 million cycles","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126279632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305228
Chi-Shiun Wang, Wen-Chun Chang, W. Ke, K. Su
In this paper, we propose a comprehensive solution for in-line NBTI monitor, including test structure, bias condition determination, reliability specification calculation, and lifetime projection. A smart self-heating pMOSFET has been successfully realized in 90nm standard CMOS technology. For the first time, we use channel resistance to carefully calibrate device junction temperature. Charge separation technique can precisely define NBTI cold holes regimes. No interruption adopts during our NBTI monitor stress duration, which can avoid recovery effect. Finally, the end-of-life (EoL) projection of each device, which is consistent with time-consuming package result, can be achieved by applying acceleration models. The whole monitor process of each sample can be finished within 2 minutes. This novel monitor can provide an early alert of process control diagnosis
{"title":"Ultra-Fast Negative Bias Temperature Instability Monitoring and End-of-Life Projection","authors":"Chi-Shiun Wang, Wen-Chun Chang, W. Ke, K. Su","doi":"10.1109/IRWS.2006.305228","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305228","url":null,"abstract":"In this paper, we propose a comprehensive solution for in-line NBTI monitor, including test structure, bias condition determination, reliability specification calculation, and lifetime projection. A smart self-heating pMOSFET has been successfully realized in 90nm standard CMOS technology. For the first time, we use channel resistance to carefully calibrate device junction temperature. Charge separation technique can precisely define NBTI cold holes regimes. No interruption adopts during our NBTI monitor stress duration, which can avoid recovery effect. Finally, the end-of-life (EoL) projection of each device, which is consistent with time-consuming package result, can be achieved by applying acceleration models. The whole monitor process of each sample can be finished within 2 minutes. This novel monitor can provide an early alert of process control diagnosis","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305208
D. Brisbin, P. Lindorfer, P. Chaparala
Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices
{"title":"Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability","authors":"D. Brisbin, P. Lindorfer, P. Chaparala","doi":"10.1109/IRWS.2006.305208","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305208","url":null,"abstract":"Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127780822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305244
Yuanjing Li, A. Tang
A study has been conducted to understand polysilicon fuse blow mechanisms and determine optimized blow conditions. The correlation of optical microscope images, cross section SEM (scanning electron microscope) images, and electrical waveforms of fuses blown at different voltages revealed two different blow mechanisms. Furthermore, SEM images of fuses blown using different pulse widths showed the physical changes of fuses during the fuse blow process
{"title":"Blowing Polysilicon Fuses: What Conditions are Best?","authors":"Yuanjing Li, A. Tang","doi":"10.1109/IRWS.2006.305244","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305244","url":null,"abstract":"A study has been conducted to understand polysilicon fuse blow mechanisms and determine optimized blow conditions. The correlation of optical microscope images, cross section SEM (scanning electron microscope) images, and electrical waveforms of fuses blown at different voltages revealed two different blow mechanisms. Furthermore, SEM images of fuses blown using different pulse widths showed the physical changes of fuses during the fuse blow process","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IRWS.2006.305203
Yunlong Li, G. Groeseneken, K. Maex, Z. Tokei
The real-time conduction mechanism evolution during bias stress of three silica based inter-metal dielectrics in Cu damascene structures was investigated. Capacitance measurements at 1 MHz and I-V measurements were intermittently inserted into the process of bias stress to monitor the conduction mechanism evolution with time. All experiments show that the capacitance is constant and the I-V curve slope decreases with bias stress and converges to the half of the initial value. Based on these findings, we conclude that the conduction mechanism changes from a normal Frenkel-Poole emission to an "abnormal" Frenkel-Poole emission with bias stress
{"title":"Bias Stress Induced Conduction Mechanism Evolution in Silica Based Inter-Metal Dielectrics","authors":"Yunlong Li, G. Groeseneken, K. Maex, Z. Tokei","doi":"10.1109/IRWS.2006.305203","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305203","url":null,"abstract":"The real-time conduction mechanism evolution during bias stress of three silica based inter-metal dielectrics in Cu damascene structures was investigated. Capacitance measurements at 1 MHz and I-V measurements were intermittently inserted into the process of bias stress to monitor the conduction mechanism evolution with time. All experiments show that the capacitance is constant and the I-V curve slope decreases with bias stress and converges to the half of the initial value. Based on these findings, we conclude that the conduction mechanism changes from a normal Frenkel-Poole emission to an \"abnormal\" Frenkel-Poole emission with bias stress","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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