Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305232
R. Leon, Y. Chen
GaAs CHFETs (complementary heterostructure field effect transistors) were characterized before and after stress testing at both room temperature and in cryogenic conditions. Various values of drain and gate voltages were used for stress conditions, and the effects of temperature on both performance and reliability were examined. A decrease in drain saturation current is observed below 150 K as well as an exponential decrease of gate leakage with decreasing temperature. Parametric degradation that follows a log-log relationship was observed under all stress conditions. For high electrical stress, the degradation was found to be worse at cryogenic temperatures
{"title":"Cryogenic Performance and Reliability of GaAs CHFETs","authors":"R. Leon, Y. Chen","doi":"10.1109/IRWS.2006.305232","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305232","url":null,"abstract":"GaAs CHFETs (complementary heterostructure field effect transistors) were characterized before and after stress testing at both room temperature and in cryogenic conditions. Various values of drain and gate voltages were used for stress conditions, and the effects of temperature on both performance and reliability were examined. A decrease in drain saturation current is observed below 150 K as well as an exponential decrease of gate leakage with decreasing temperature. Parametric degradation that follows a log-log relationship was observed under all stress conditions. For high electrical stress, the degradation was found to be worse at cryogenic temperatures","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122302918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305224
D. Heh, R. Choi, C. Young, G. Bersuker
A single pulse technique with a wide range of pulse times has been applied to study trap charging and discharging mechanisms in nMOSFET high-k devices. It is shown that both charging and discharging are controlled by two distinctive processes with different characteristic times. A proposed characterization methodology, which separates the relaxation effects associated with the fast transient charging/discharging processes, allows extracting the intrinsic dependence of threshold voltage on stress time
{"title":"Fast and slow charge trapping/detrapping processes in high-k nMOSFETs","authors":"D. Heh, R. Choi, C. Young, G. Bersuker","doi":"10.1109/IRWS.2006.305224","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305224","url":null,"abstract":"A single pulse technique with a wide range of pulse times has been applied to study trap charging and discharging mechanisms in nMOSFET high-k devices. It is shown that both charging and discharging are controlled by two distinctive processes with different characteristic times. A proposed characterization methodology, which separates the relaxation effects associated with the fast transient charging/discharging processes, allows extracting the intrinsic dependence of threshold voltage on stress time","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116716646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305222
H. Xiong, J. Suehle
Low frequency (LF) noise is studied in n-type metal-oxide-semiconductor field-effect-transistors (nMOSFETs) with various HfO2 or interfacial layer (IL) thicknesses and is found to be dominated by 1/f noise in the frequency range 1 Hz lesfles 1.6 kHz. LF noise magnitude increases with HfO2 thickness and decreases with IL SiO2 thickness. Traps at the channel and dielectric interface do not contribute to the 1/f noise or cannot be resolved from thermal noise. The LF noise correlates well with the hysteresis or Vth instability observed during DC measurements. The volume trap density calculated from 1/f noise analysis is more than one order of magnitude higher in 7 nm HfO2 than in 3 nm HfO2 devices. Qualitative trap spatial profiles can be obtained from the LF spectra, and the stress induced redistribution of trap distribution is discussed
{"title":"Spatial Probing of Traps in nMOSFET with ALD HfO2/SiO2 Stacks Using Low Frequency Noise Characteristics","authors":"H. Xiong, J. Suehle","doi":"10.1109/IRWS.2006.305222","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305222","url":null,"abstract":"Low frequency (LF) noise is studied in n-type metal-oxide-semiconductor field-effect-transistors (nMOSFETs) with various HfO2 or interfacial layer (IL) thicknesses and is found to be dominated by 1/f noise in the frequency range 1 Hz lesfles 1.6 kHz. LF noise magnitude increases with HfO2 thickness and decreases with IL SiO2 thickness. Traps at the channel and dielectric interface do not contribute to the 1/f noise or cannot be resolved from thermal noise. The LF noise correlates well with the hysteresis or Vth instability observed during DC measurements. The volume trap density calculated from 1/f noise analysis is more than one order of magnitude higher in 7 nm HfO2 than in 3 nm HfO2 devices. Qualitative trap spatial profiles can be obtained from the LF spectra, and the stress induced redistribution of trap distribution is discussed","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134454731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305210
J. Roux, X. Federspiel, D. Roy
In this work we have characterized the self-heating in NMOS transistors using gate resistance methodology. The resulting self-heating model was used to estimate the channel temperature during DC HCI stress. Furthermore, the same model (Arrhenius) was used to extrapolate HCI lifetime corresponding to analog and digital applications. And this is demonstrated for NMOS transistor and for PMOS transistor. This is the first investigation of SH impact on HCI DC degradation for both analog and digital applications and the first proposed methodology to correct HCI DC dataset from SH contribution
{"title":"Effect of Self-Heating on HCI Lifetime Prediction in SOI Technologies","authors":"J. Roux, X. Federspiel, D. Roy","doi":"10.1109/IRWS.2006.305210","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305210","url":null,"abstract":"In this work we have characterized the self-heating in NMOS transistors using gate resistance methodology. The resulting self-heating model was used to estimate the channel temperature during DC HCI stress. Furthermore, the same model (Arrhenius) was used to extrapolate HCI lifetime corresponding to analog and digital applications. And this is demonstrated for NMOS transistor and for PMOS transistor. This is the first investigation of SH impact on HCI DC degradation for both analog and digital applications and the first proposed methodology to correct HCI DC dataset from SH contribution","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133123787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305216
J. Han, B. Lee, J. Han, W. Kwon, C. Chang, S. Sim, Chan-Kwang Park, Kinam Kim
Sporadic drain disturb problem in multi-level cell (MLC) NOR flash memory devices incorporating cobalt salicidation processes becomes a new critical failure mode. The provoked disturb is shown to be caused by erratic lateral encroachment of cobalt salicidation on the drain region of the flash cell. This failure becomes increasingly significant as the device cell size is scaled down. In this work, we report our study on the new failure mechanism and suggest our engineered device fabrication method to alleviate the cobalt encroachment
{"title":"A Critical Failure Source in 65nm-MLC NOR Flash Memory Incorporating Co-Salicidation Process","authors":"J. Han, B. Lee, J. Han, W. Kwon, C. Chang, S. Sim, Chan-Kwang Park, Kinam Kim","doi":"10.1109/IRWS.2006.305216","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305216","url":null,"abstract":"Sporadic drain disturb problem in multi-level cell (MLC) NOR flash memory devices incorporating cobalt salicidation processes becomes a new critical failure mode. The provoked disturb is shown to be caused by erratic lateral encroachment of cobalt salicidation on the drain region of the flash cell. This failure becomes increasingly significant as the device cell size is scaled down. In this work, we report our study on the new failure mechanism and suggest our engineered device fabrication method to alleviate the cobalt encroachment","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114737755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305229
F. Duan, S. Cooper, A. Marathe, J. Zhang, S. Jayanarayanan
During the accelerated stressing test, not only the stress voltage affects the lifetime extrapolation but also the monitoring voltage plays a considerable role. We have conducted a series of tests in various stress and monitoring voltages to quantify this impact. We have seen ~20 times difference on lifetime at monitoring voltages of 1.0V and 1.5V under a same stressed voltage. This difference should be taken into account to accurately predict the lifetime at normal use conditions from the data obtained in accelerated life test
{"title":"Impact of Monitoring Voltage on the Lifetime Extrapolation During the Accelerated Degradation Tests","authors":"F. Duan, S. Cooper, A. Marathe, J. Zhang, S. Jayanarayanan","doi":"10.1109/IRWS.2006.305229","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305229","url":null,"abstract":"During the accelerated stressing test, not only the stress voltage affects the lifetime extrapolation but also the monitoring voltage plays a considerable role. We have conducted a series of tests in various stress and monitoring voltages to quantify this impact. We have seen ~20 times difference on lifetime at monitoring voltages of 1.0V and 1.5V under a same stressed voltage. This difference should be taken into account to accurately predict the lifetime at normal use conditions from the data obtained in accelerated life test","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129479323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305230
R. Bottini, A. Sebastiani, N. Galbiati, C. Scozzari, G. Ghidini
Aim of this work is to propose a new fast methodology to be applied to thick gate and tunnel oxides in Flash and embedded Flash processes. Starting from the reliability characterization of the dielectric it is possible to define a very short stress (lower than 1-2sec) which correlates with standard long reliability testing procedures (constant voltage stress, CVS, or constant current stress, CCS). For thick dielectrics, whose significant charge trapping affects the lifetime, the definition of a short stress condition is critical, but it is shown that a short CCS test can overcome this problem. This short test can be introduced at parametric testing in order to screen defective oxides following a criteria directly correlated with device requirements
{"title":"Oxide Reliability: a new Methodology for Reliability Evaluation at Parametric Testing","authors":"R. Bottini, A. Sebastiani, N. Galbiati, C. Scozzari, G. Ghidini","doi":"10.1109/IRWS.2006.305230","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305230","url":null,"abstract":"Aim of this work is to propose a new fast methodology to be applied to thick gate and tunnel oxides in Flash and embedded Flash processes. Starting from the reliability characterization of the dielectric it is possible to define a very short stress (lower than 1-2sec) which correlates with standard long reliability testing procedures (constant voltage stress, CVS, or constant current stress, CCS). For thick dielectrics, whose significant charge trapping affects the lifetime, the definition of a short stress condition is critical, but it is shown that a short CCS test can overcome this problem. This short test can be introduced at parametric testing in order to screen defective oxides following a criteria directly correlated with device requirements","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305246
D. Verbitsky
A simple procedure, evaluating wafer reliability by HALT before full regular processing, is justified and optimized. This procedure is aimed at early failure rate assessment, reliability adjustment, and yield enhancement per customer needs. A test plan concept, detailed design and realization are suggested. Test optimization with respect to customer requirements, field failures, and manufacturing losses are presented. Some regular flaws and recommendations are proposed. The procedure allows significant manufacturing and field savings along with increasing customer satisfaction. The procedure can be extended to manufacturing operation optimization and applied to related GaAs and Si based innovative technologies
{"title":"Wafer Reliability Evaluation and Monitoring for InGaAsP Devices","authors":"D. Verbitsky","doi":"10.1109/IRWS.2006.305246","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305246","url":null,"abstract":"A simple procedure, evaluating wafer reliability by HALT before full regular processing, is justified and optimized. This procedure is aimed at early failure rate assessment, reliability adjustment, and yield enhancement per customer needs. A test plan concept, detailed design and realization are suggested. Test optimization with respect to customer requirements, field failures, and manufacturing losses are presented. Some regular flaws and recommendations are proposed. The procedure allows significant manufacturing and field savings along with increasing customer satisfaction. The procedure can be extended to manufacturing operation optimization and applied to related GaAs and Si based innovative technologies","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131317965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305245
L.J. Duan, H. H. Au, M. Kuan, P. Quek, K. Pey
Poly-silicon crater defect generated in large plate of n+ poly-silicon on p-type substrate that resulted in gate oxide integrity (GOI) failure in 0.15mum silicon process is investigated. Al tiny particle accidentally introduced from PECVD resistance protection oxide (RPO) deposition is found to be able to translate into such poly-silicon crater defect in the test structure during subsequent oxide photo-resist patterning and oxide wet etching. The defect size can correlate to DI water rinse time of photo-resist developing in RPO oxide patterning. The longer time of water rinse, the larger size of the craters. This paper describes observation of n+ poly-silicon crater formation. A new mechanism of Al tiny particle induced n+ poly-silicon charging effect during high speed spinning water rinse in oxide patterning process is proposed. After water rinse completion in the process, the charges stored in poly-silicon are unable to be discharged immediately due to enough large capacitance of gate oxide in discharging path of the test structure. Charged poly-silicon is then quickly attacked in diluted 0.5w%HF immersion of RPO oxide wet etching by galvanic corrosion to form a crater. To eliminate poly-silicon crater formation, efforts could be put into eliminating the presence of aluminum particles in oxide deposition or optimization of water rinse condition. Oxide dry etching is also one of possible improvements can be evaluated
{"title":"A New Mechanism of Poly-silicon Crater Defect Induced from Al Tiny Particle Charging Effect during Water Rinse in Oxide Patterning Process","authors":"L.J. Duan, H. H. Au, M. Kuan, P. Quek, K. Pey","doi":"10.1109/IRWS.2006.305245","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305245","url":null,"abstract":"Poly-silicon crater defect generated in large plate of n+ poly-silicon on p-type substrate that resulted in gate oxide integrity (GOI) failure in 0.15mum silicon process is investigated. Al tiny particle accidentally introduced from PECVD resistance protection oxide (RPO) deposition is found to be able to translate into such poly-silicon crater defect in the test structure during subsequent oxide photo-resist patterning and oxide wet etching. The defect size can correlate to DI water rinse time of photo-resist developing in RPO oxide patterning. The longer time of water rinse, the larger size of the craters. This paper describes observation of n+ poly-silicon crater formation. A new mechanism of Al tiny particle induced n+ poly-silicon charging effect during high speed spinning water rinse in oxide patterning process is proposed. After water rinse completion in the process, the charges stored in poly-silicon are unable to be discharged immediately due to enough large capacitance of gate oxide in discharging path of the test structure. Charged poly-silicon is then quickly attacked in diluted 0.5w%HF immersion of RPO oxide wet etching by galvanic corrosion to form a crater. To eliminate poly-silicon crater formation, efforts could be put into eliminating the presence of aluminum particles in oxide deposition or optimization of water rinse condition. Oxide dry etching is also one of possible improvements can be evaluated","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305247
L. Sheng, E. De Backer, D. Wojciechowski, J. De Greve, K. Dhondt, S. Boonen, D. Malschaert, E. Snyder
Surface roughness enhanced current stressing is shown to enhance the dielectric breakdown in poly-oxide-poly capacitors. Moreover, it is demonstrated for the first time that the changes of sophisticated polysilicon surface features as depicted by AFM-PSD (power spectral density) synthesis can globally become the dominant "defects" in deteriorating the dielectric reliability under a high electric field
{"title":"Surface Roughness Enhanced Current in Defectively Stressing Poly-Oxide-Poly Capacitors","authors":"L. Sheng, E. De Backer, D. Wojciechowski, J. De Greve, K. Dhondt, S. Boonen, D. Malschaert, E. Snyder","doi":"10.1109/IRWS.2006.305247","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305247","url":null,"abstract":"Surface roughness enhanced current stressing is shown to enhance the dielectric breakdown in poly-oxide-poly capacitors. Moreover, it is demonstrated for the first time that the changes of sophisticated polysilicon surface features as depicted by AFM-PSD (power spectral density) synthesis can globally become the dominant \"defects\" in deteriorating the dielectric reliability under a high electric field","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121092375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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