Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305223
M. Rafik, G. Ribes, D. Roy, S. Kalpat, G. Ghibaudo
In this paper, stress induced leakage current under positive gate voltage is investigated. It turns out that it is caused by bulk defects that are also responsible for breakdown. Moreover, it appears that depending on the gate voltage, erroneous estimation could be made and could affect the conclusions on the reliability
{"title":"New Insight on the Origin of Stress Induced Leakage Current for SIO2/HFO2 Dielectric Stacks","authors":"M. Rafik, G. Ribes, D. Roy, S. Kalpat, G. Ghibaudo","doi":"10.1109/IRWS.2006.305223","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305223","url":null,"abstract":"In this paper, stress induced leakage current under positive gate voltage is investigated. It turns out that it is caused by bulk defects that are also responsible for breakdown. Moreover, it appears that depending on the gate voltage, erroneous estimation could be made and could affect the conclusions on the reliability","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128349869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305241
A. Aal
In this paper a new technique for predicting gate oxide reliability with high confidence from easily accessible ramped voltage stress data is proposed. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions
{"title":"Fast Prediction Of Gate Oxide Reliability - Application Of The Cumulative Damage Principle For Transforming V-Ramp Breakdown Distributions Into TDDB Failure Distributions","authors":"A. Aal","doi":"10.1109/IRWS.2006.305241","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305241","url":null,"abstract":"In this paper a new technique for predicting gate oxide reliability with high confidence from easily accessible ramped voltage stress data is proposed. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128828694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305231
R. Southwick, M. Elgin, G. Bersuker, R. Choi, W. B. Knowlton
Hafnium oxide integrity is investigated. Time-zero dielectric breakdown tests to determine breakdown strength is performed for electron gate injection over a variety of HfO2 thicknesses. Results indicate the breakdown strength is not purely related to the electric field or voltage drop across the high-k but suggests a combination of both. Reliability of the gate stack seems to improve as the HfO2 layer thickness decreases
{"title":"Preliminary Study of the Breakdown Strength of TiN/HfO2/SiO2/Si MOS Gate Stacks","authors":"R. Southwick, M. Elgin, G. Bersuker, R. Choi, W. B. Knowlton","doi":"10.1109/IRWS.2006.305231","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305231","url":null,"abstract":"Hafnium oxide integrity is investigated. Time-zero dielectric breakdown tests to determine breakdown strength is performed for electron gate injection over a variety of HfO2 thicknesses. Results indicate the breakdown strength is not purely related to the electric field or voltage drop across the high-k but suggests a combination of both. Reliability of the gate stack seems to improve as the HfO2 layer thickness decreases","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128830448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305217
H. Suto, S. Mori, M. Kanno, N. Nagashima
Electrically programmable fuses (e-fuse) (Alavi, 1997) with Ni-silicided poly-Si filament fabricated on four dopant conditions were studied through two successive I-V measurements. The initial I-V sweeps can change e-fuses into targeted programmed states and display the whole programming processes where the currents change in many orders of magnitude. The second I-V curves can show the stabilities and conductions in the programmed states on both bias polarities. The programming processes in quasi-programmed states before properly programming were found to be strongly dependent on the dopant conditions. And at least two or three properly programmed states were identified among properly programmed states in terms of the characteristic spreads of the final resistance and the conduction behaviors. The most distinctive currents after properly programming are similar to those in varistors. The stability in every programmed state turned out to be dependent strongly on the dopant conditions
{"title":"Study of Electrically Programmable Fuses through Series of I-V Measurements","authors":"H. Suto, S. Mori, M. Kanno, N. Nagashima","doi":"10.1109/IRWS.2006.305217","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305217","url":null,"abstract":"Electrically programmable fuses (e-fuse) (Alavi, 1997) with Ni-silicided poly-Si filament fabricated on four dopant conditions were studied through two successive I-V measurements. The initial I-V sweeps can change e-fuses into targeted programmed states and display the whole programming processes where the currents change in many orders of magnitude. The second I-V curves can show the stabilities and conductions in the programmed states on both bias polarities. The programming processes in quasi-programmed states before properly programming were found to be strongly dependent on the dopant conditions. And at least two or three properly programmed states were identified among properly programmed states in terms of the characteristic spreads of the final resistance and the conduction behaviors. The most distinctive currents after properly programming are similar to those in varistors. The stability in every programmed state turned out to be dependent strongly on the dopant conditions","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114293403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305204
X. Federspiel, D. Ney, L. Doyen, V. Girault
The careful analysis of resistance evolution with time during electromigration tests provided valuable information about damascene architecture and intrinsic electromigration behaviour. We found first, that resistance evolution includes an abrupt event, the amplitude of which is usually corresponding to the failure criteria and second, that the height of this step (and sample resistance) is correlated with time to fail. We showed that the evolution of time to step was more likely to be due to the vertical growth of a void which length is making resistance step amplitude varying from sample to sample. Second we found a correlation between sample initial resistance and time to failure that is believed to be due to trench depth. However this effect is widely spread and correlation coefficient is as low as 0.3. These 2 phenomena combined together, increase the standard deviation affecting lifetime. As a matter of fact, resistance increase rate is expected to be directly proportional to void growth rate and copper diffusion coefficient whereas step height is function of the void shape and barrier thickness
{"title":"Dynamics of Resistance Evolution During Electromigration","authors":"X. Federspiel, D. Ney, L. Doyen, V. Girault","doi":"10.1109/IRWS.2006.305204","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305204","url":null,"abstract":"The careful analysis of resistance evolution with time during electromigration tests provided valuable information about damascene architecture and intrinsic electromigration behaviour. We found first, that resistance evolution includes an abrupt event, the amplitude of which is usually corresponding to the failure criteria and second, that the height of this step (and sample resistance) is correlated with time to fail. We showed that the evolution of time to step was more likely to be due to the vertical growth of a void which length is making resistance step amplitude varying from sample to sample. Second we found a correlation between sample initial resistance and time to failure that is believed to be due to trench depth. However this effect is widely spread and correlation coefficient is as low as 0.3. These 2 phenomena combined together, increase the standard deviation affecting lifetime. As a matter of fact, resistance increase rate is expected to be directly proportional to void growth rate and copper diffusion coefficient whereas step height is function of the void shape and barrier thickness","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305200
T. Grasser, W. Gos, B. Kaczer
Negative bias temperature instability (NBTI) is one of the most serious reliability concerns for highly scaled pMOSFETs. It is most commonly interpreted by some form of reaction-diffusion (RD) model, which assumes that some hydrogen species is released from previously passivated interface defects, which then diffuses into the oxide. It has been argued, however, that hydrogen motion in the oxide is trap-controlled, resulting in dispersive transport behavior. This defect-controlled transport modifies the characteristic exponent in the power-law that describes the threshold-voltage shift. However, previously published models are contradictory and both an increase and a decrease in the power-law exponent have been reported. We clarify this discrepancy by identifying the boundary condition which couples the transport equations to the electro-chemical reaction at the interface as the crucial component of the physically-based description
{"title":"Modeling of Dispersive Transport in the Context of Negative Bias Temperature Instability","authors":"T. Grasser, W. Gos, B. Kaczer","doi":"10.1109/IRWS.2006.305200","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305200","url":null,"abstract":"Negative bias temperature instability (NBTI) is one of the most serious reliability concerns for highly scaled pMOSFETs. It is most commonly interpreted by some form of reaction-diffusion (RD) model, which assumes that some hydrogen species is released from previously passivated interface defects, which then diffuses into the oxide. It has been argued, however, that hydrogen motion in the oxide is trap-controlled, resulting in dispersive transport behavior. This defect-controlled transport modifies the characteristic exponent in the power-law that describes the threshold-voltage shift. However, previously published models are contradictory and both an increase and a decrease in the power-law exponent have been reported. We clarify this discrepancy by identifying the boundary condition which couples the transport equations to the electro-chemical reaction at the interface as the crucial component of the physically-based description","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115068809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305209
M. Gurfinkel, J. Suehle, J. Bernstein, Y. Shapira, A. Lelis, D. Habersat, N. Goldsman
One of the most important issues that limits the performance and reliability of SiC power MOSFETs is the threshold voltage instability under normal operation conditions. This phenomenon has been recently studied using dc sweep measurements. In this work, we studied the threshold voltage instability using fast I-V measurements. The results show that under positive bias, VTH shifts to more positive values, while it shifts to more negative values under negative bias. Fast I-V measurements reveal the full extent of the VTH instability, underestimated by the dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. A physical model involving fast transient charge trapping and de-trapping at and near the SiC/SiO2 interface is proposed
{"title":"Ultra-Fast Measurements of VTH Instability in SiC MOSFETs due to Positive and Negative Constant Bias Stress","authors":"M. Gurfinkel, J. Suehle, J. Bernstein, Y. Shapira, A. Lelis, D. Habersat, N. Goldsman","doi":"10.1109/IRWS.2006.305209","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305209","url":null,"abstract":"One of the most important issues that limits the performance and reliability of SiC power MOSFETs is the threshold voltage instability under normal operation conditions. This phenomenon has been recently studied using dc sweep measurements. In this work, we studied the threshold voltage instability using fast I-V measurements. The results show that under positive bias, VTH shifts to more positive values, while it shifts to more negative values under negative bias. Fast I-V measurements reveal the full extent of the VTH instability, underestimated by the dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. A physical model involving fast transient charge trapping and de-trapping at and near the SiC/SiO2 interface is proposed","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"231 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305218
Boon Ang, S. Tumakha, J. Im, S. Paak
The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65nm logic CMOS technology were studied. Under optimal programming conditions, high post-program resistance can be achieved. These well programmed fuses showed good data retention, capable of meeting the operating lifetime requirement of most applications
{"title":"NiSi Polysilicon Fuse Reliability in 65nm Logic CMOS Technology","authors":"Boon Ang, S. Tumakha, J. Im, S. Paak","doi":"10.1109/IRWS.2006.305218","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305218","url":null,"abstract":"The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65nm logic CMOS technology were studied. Under optimal programming conditions, high post-program resistance can be achieved. These well programmed fuses showed good data retention, capable of meeting the operating lifetime requirement of most applications","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132860258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305225
S. Jakschik, T. Kauerauf, R. Degreave, Y. Hwang, R. Duschl, M. Kerber, A. Avellan, S. Kudelka
Looking to reliability of high-k dielectrics, their behavior under electrical stress is very often determined by traps and charges. During the past years a strong focus of the reliability investigation was given to HfO2. However, especially LSTP as well as memory industry is going to use a silicon doped hafnium oxide (HfSiOx). Three different cases of current vs. time dependence are observed with constant voltage stress for HfSiOx. Often the current decreases for short stress times because of charging. This period can be followed by either barrier lowering due to electron detrapping or stress induced leakage current (SILC) (Duschl, 2006). Both mechanisms raise the current level at constant voltage. In the SILC case the increase of leakage can go step wise, whereas for barrier lowering the leakage increases gradually even on small areas. However, although barrier lowering and charging are considered to be reversible by alternating voltage polarity SILC is often not reversible because it introduces damage and high resistance break down spots in the dielectric. During measurement SILC can even remain undetected if barrier lowering and/or charging are dominant. Recently, it was shown that barrier lowering for these HfSiOx is the major contribution to leakage increase over stress time (Duschl, 2006). In the following paper the authors focus on the question if a small SILC contribution behind the dominant measured barrier lowering can become a reliability concern. In a first part major effects of SILC in HfSiOx with EOT>1.5nm and TiN gate are discussed. In a second part we analyze whether SILC damage can be hidden by barrier lowering or not. Finally we are coming to the conclusion, that a sample with leakage increase due to barrier lowering does not exhibit severe SILC in parallel
{"title":"Influence of Stress-Induced-Leakage-Current on Reliability of HfSiOx with EOT>1.5nm and TiN Gate","authors":"S. Jakschik, T. Kauerauf, R. Degreave, Y. Hwang, R. Duschl, M. Kerber, A. Avellan, S. Kudelka","doi":"10.1109/IRWS.2006.305225","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305225","url":null,"abstract":"Looking to reliability of high-k dielectrics, their behavior under electrical stress is very often determined by traps and charges. During the past years a strong focus of the reliability investigation was given to HfO2. However, especially LSTP as well as memory industry is going to use a silicon doped hafnium oxide (HfSiOx). Three different cases of current vs. time dependence are observed with constant voltage stress for HfSiOx. Often the current decreases for short stress times because of charging. This period can be followed by either barrier lowering due to electron detrapping or stress induced leakage current (SILC) (Duschl, 2006). Both mechanisms raise the current level at constant voltage. In the SILC case the increase of leakage can go step wise, whereas for barrier lowering the leakage increases gradually even on small areas. However, although barrier lowering and charging are considered to be reversible by alternating voltage polarity SILC is often not reversible because it introduces damage and high resistance break down spots in the dielectric. During measurement SILC can even remain undetected if barrier lowering and/or charging are dominant. Recently, it was shown that barrier lowering for these HfSiOx is the major contribution to leakage increase over stress time (Duschl, 2006). In the following paper the authors focus on the question if a small SILC contribution behind the dominant measured barrier lowering can become a reliability concern. In a first part major effects of SILC in HfSiOx with EOT>1.5nm and TiN gate are discussed. In a second part we analyze whether SILC damage can be hidden by barrier lowering or not. Finally we are coming to the conclusion, that a sample with leakage increase due to barrier lowering does not exhibit severe SILC in parallel","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121749399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-01DOI: 10.1109/IRWS.2006.305219
J. Qin, J. Bernstein
In this paper, we study temperature and voltage acceleration of semiconductor device with multiple intrinsic failure mechanisms involved: hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). Simulation shows that system activation energy and voltage acceleration parameter depend on stress temperature and voltage. A modified Arrhenius relationship is proposed to model the temperature dependence of device lifetime at given voltage. A modified exponential model is also proposed to model the voltage dependence of device lifetime at given temperature
{"title":"Non-Arrhenius Temperature Acceleration and Stress-Dependent Voltage Acceleration for Semiconductor Device Involving Multiple Failure Mechanisms","authors":"J. Qin, J. Bernstein","doi":"10.1109/IRWS.2006.305219","DOIUrl":"https://doi.org/10.1109/IRWS.2006.305219","url":null,"abstract":"In this paper, we study temperature and voltage acceleration of semiconductor device with multiple intrinsic failure mechanisms involved: hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). Simulation shows that system activation energy and voltage acceleration parameter depend on stress temperature and voltage. A modified Arrhenius relationship is proposed to model the temperature dependence of device lifetime at given voltage. A modified exponential model is also proposed to model the voltage dependence of device lifetime at given temperature","PeriodicalId":199223,"journal":{"name":"2006 IEEE International Integrated Reliability Workshop Final Report","volume":"22 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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