Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996789
Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, T. Hsieh
In this paper we present an approach to minimize power consumption in the logic synthesis stage by using the gate decomposition technique. Since the power consumption of ICs is not only decided by the switching activity of each gate but also depends on the gate types in the target library, the major difference between our algorithm and the traditional methods is that we consider the power consumption of different types of gate. In addition, by the usage of inverter relocation based on Demorgan's law, we can further reduce the IC's total power consumption. Under the cases of different of input signal probabilities, switching rates are applied, and experimental results show that our approach can further reduce average power consumption by up to 12.7% as compared to the case of the applied ExDecomp/HeuDecomp algorithm (Twari et al, Proc. 30th Design Automation Conf., pp.74-79, 1993).
在本文中，我们提出了一种利用门分解技术来最小化逻辑合成阶段功耗的方法。由于ic的功耗不仅取决于每个门的开关活动，还取决于目标库中的门类型，因此我们的算法与传统方法的主要区别在于我们考虑了不同类型门的功耗。此外，利用基于Demorgan定律的逆变器重新定位，可以进一步降低集成电路的总功耗。在不同输入信号概率的情况下，应用开关率，实验结果表明，与应用ExDecomp/HeuDecomp算法相比，我们的方法可以进一步降低平均功耗高达12.7% (Twari et al . Proc. 30 Design Automation Conf.， pp.74-79, 1993)。
{"title":"Structural decomposition with functional considerations for low power","authors":"Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, T. Hsieh","doi":"10.1109/ISQED.2002.996789","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996789","url":null,"abstract":"In this paper we present an approach to minimize power consumption in the logic synthesis stage by using the gate decomposition technique. Since the power consumption of ICs is not only decided by the switching activity of each gate but also depends on the gate types in the target library, the major difference between our algorithm and the traditional methods is that we consider the power consumption of different types of gate. In addition, by the usage of inverter relocation based on Demorgan's law, we can further reduce the IC's total power consumption. Under the cases of different of input signal probabilities, switching rates are applied, and experimental results show that our approach can further reduce average power consumption by up to 12.7% as compared to the case of the applied ExDecomp/HeuDecomp algorithm (Twari et al, Proc. 30th Design Automation Conf., pp.74-79, 1993).","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77665664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996791
D. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee, Brian A. Clebowicz, IV RichardW.Hollis, L. Wissel, Tad Wilder
Boeing Satellite Systems and IBM have designed and fabricated a, set of ASIC chip types to perform computation-intensive digital signal processing (DSP) functions on board geosynchronous satellites of the Thuraya mobile communications system. Preparation for this application required comprehensive review of the reliability and space-worthiness of the underlying process and packaging technology. First-pass success on all nine million-plus-gate ASIC designs required extensive model-based simulation and verification. These technologies allowed a four-fold increase in the computational power of the DSP unit over previous systems based on radiation-hardened ASICs, while simultaneously decreasing the number of ASICs required by another factor of five. The first Thuraya satellite is on-orhit, and the whole communications system is performing flawlessly.
{"title":"Megagate ASICs for the Thuraya satellite digital signal processor","authors":"D. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee, Brian A. Clebowicz, IV RichardW.Hollis, L. Wissel, Tad Wilder","doi":"10.1109/ISQED.2002.996791","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996791","url":null,"abstract":"Boeing Satellite Systems and IBM have designed and fabricated a, set of ASIC chip types to perform computation-intensive digital signal processing (DSP) functions on board geosynchronous satellites of the Thuraya mobile communications system. Preparation for this application required comprehensive review of the reliability and space-worthiness of the underlying process and packaging technology. First-pass success on all nine million-plus-gate ASIC designs required extensive model-based simulation and verification. These technologies allowed a four-fold increase in the computational power of the DSP unit over previous systems based on radiation-hardened ASICs, while simultaneously decreasing the number of ASICs required by another factor of five. The first Thuraya satellite is on-orhit, and the whole communications system is performing flawlessly.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83501023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996744
Zhuo Gao, Ji Luo, Hu Huang, Wei Zhang, J. Bernstein
Field-programmable gate arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower non-recurring engineering (NRE) cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, laser-induced MakeLink/spl trade/ technology is proposed as a programmable switch element. The electrical resistance is as low as 0.8 /spl Omega/ to 11 /spl Omega/, depending on the size of the link, which is 2-3 orders smaller than that of NMOS transistor in a SRAM based FPGA. Thus the speed improvement for laser field-programmable gate array (LFPGA) is significant. Other features of laser-induced vertical links technology, such as small size and radiation hardness, can also greatly improve the FPGA performance. The cluster-based LFPGA with 128 by 64 basic logic elements (BLE) is laid out under a 0.5 /spl mu/m commercialized technology. The chip size is about 138 mm/sup 2/.
{"title":"Reliable laser programmable gate array technology","authors":"Zhuo Gao, Ji Luo, Hu Huang, Wei Zhang, J. Bernstein","doi":"10.1109/ISQED.2002.996744","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996744","url":null,"abstract":"Field-programmable gate arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower non-recurring engineering (NRE) cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, laser-induced MakeLink/spl trade/ technology is proposed as a programmable switch element. The electrical resistance is as low as 0.8 /spl Omega/ to 11 /spl Omega/, depending on the size of the link, which is 2-3 orders smaller than that of NMOS transistor in a SRAM based FPGA. Thus the speed improvement for laser field-programmable gate array (LFPGA) is significant. Other features of laser-induced vertical links technology, such as small size and radiation hardness, can also greatly improve the FPGA performance. The cluster-based LFPGA with 128 by 64 basic logic elements (BLE) is laid out under a 0.5 /spl mu/m commercialized technology. The chip size is about 138 mm/sup 2/.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78717334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996769
N. Shigyo, H. Kawashima, S. Yasuda
This paper describes an ESD protection device design to minimize its area A/sub p/ while maintaining the breakdown voltage V/sub ESD/. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate V/sub ESD/. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.
{"title":"Design of ESD protection device using statistical methods","authors":"N. Shigyo, H. Kawashima, S. Yasuda","doi":"10.1109/ISQED.2002.996769","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996769","url":null,"abstract":"This paper describes an ESD protection device design to minimize its area A/sub p/ while maintaining the breakdown voltage V/sub ESD/. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate V/sub ESD/. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81116211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996733
B. Brodersen
Summary form only given. There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links are also rapidly evolving. The multiple inter-related technologies required for implementation of such wireless systems requires a co-design strategy in communication algorithms, digital architectures and the analog and digital circuits required for their implementation. Critical to good design of these chips is the definition of energy and area performance metrics that can facilitate the tradeoff of issues such as the cost of providing flexibility or the amount of parallelism to exploit. These design decisions can result in differences of orders of magnitude in the metrics between what is possible in the technology and what is often achieved if the costs are not fully understood. A design infrastructure which supports architectures and which optimizes the metrics is described for wireless systems, providing a fully automated chip design flow from a high level system specification.
{"title":"Wireless systems-on-a-chip design","authors":"B. Brodersen","doi":"10.1109/ISQED.2002.996733","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996733","url":null,"abstract":"Summary form only given. There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links are also rapidly evolving. The multiple inter-related technologies required for implementation of such wireless systems requires a co-design strategy in communication algorithms, digital architectures and the analog and digital circuits required for their implementation. Critical to good design of these chips is the definition of energy and area performance metrics that can facilitate the tradeoff of issues such as the cost of providing flexibility or the amount of parallelism to exploit. These design decisions can result in differences of orders of magnitude in the metrics between what is possible in the technology and what is often achieved if the costs are not fully understood. A design infrastructure which supports architectures and which optimizes the metrics is described for wireless systems, providing a fully automated chip design flow from a high level system specification.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83684369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996732
A. Raza
Human beings being social have had a need to communicate. The modern chapter in enabling large scale communication has been aided by intelligence in the transport, distribution, protection, traffic management, decoding, analyzing and displaying of communication content. The intelligence has been embedded in an explosive confluence of software, systems and integrated circuits. This has resulted in the most amazing transformation of the way we live our lives, work, and engage in all other necessary and capricious activity. It has also created a huge economic footprint on the Gross Domestic Product of the United States of America. With a massive transformation that has occurred in such a short time, this throbbing network across the planet has to operate reliably because of the precious payload it carries.
{"title":"The role of ICs in the creation of a connected world and the importance of product quality","authors":"A. Raza","doi":"10.1109/ISQED.2002.996732","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996732","url":null,"abstract":"Human beings being social have had a need to communicate. The modern chapter in enabling large scale communication has been aided by intelligence in the transport, distribution, protection, traffic management, decoding, analyzing and displaying of communication content. The intelligence has been embedded in an explosive confluence of software, systems and integrated circuits. This has resulted in the most amazing transformation of the way we live our lives, work, and engage in all other necessary and capricious activity. It has also created a huge economic footprint on the Gross Domestic Product of the United States of America. With a massive transformation that has occurred in such a short time, this throbbing network across the planet has to operate reliably because of the precious payload it carries.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88543991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996694
Gaofeng Wang, X. Qi, Zhiping Yu, R. Dutton
An accurate nonlinear circuit model for metal-insulator-semiconductor (MIS) interconnects is presented based on a device level simulation. The device level simulation gives detailed information regarding field-carrier interactions, semiconductor substrate loss and nonlinearity, as well as slow-wave effect, external bias effect and screening effect of the charged carriers. This model consists of an equivalent transmission line that mimics the energy transport characteristics of the actual MIS interconnect, and provides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analyses.
{"title":"Accurate model of metal-insulator-semiconductor interconnects","authors":"Gaofeng Wang, X. Qi, Zhiping Yu, R. Dutton","doi":"10.1109/ISQED.2002.996694","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996694","url":null,"abstract":"An accurate nonlinear circuit model for metal-insulator-semiconductor (MIS) interconnects is presented based on a device level simulation. The device level simulation gives detailed information regarding field-carrier interactions, semiconductor substrate loss and nonlinearity, as well as slow-wave effect, external bias effect and screening effect of the charged carriers. This model consists of an equivalent transmission line that mimics the energy transport characteristics of the actual MIS interconnect, and provides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analyses.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76705139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996706
Y. Tsiatouhas, T. Haniotakis, D. Nikolos, A. Arapoyanni
I/sub DDQ/ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new I/sub DDQ/ testing scheme is proposed. This scheme is based on the elimination, during I/sub DDQ/ testing, of the normal leakage current from the sensing node of the circuit under test so that already known in the open literature I/sub DDQ/ sensing techniques can be applied in deep submicron.
{"title":"Extending the viability of I/sub DDQ/ testing in the deep submicron era","authors":"Y. Tsiatouhas, T. Haniotakis, D. Nikolos, A. Arapoyanni","doi":"10.1109/ISQED.2002.996706","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996706","url":null,"abstract":"I/sub DDQ/ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new I/sub DDQ/ testing scheme is proposed. This scheme is based on the elimination, during I/sub DDQ/ testing, of the normal leakage current from the sensing node of the circuit under test so that already known in the open literature I/sub DDQ/ sensing techniques can be applied in deep submicron.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76822262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996765
Jin-Kyu Park, Keun-Ho Lee, C. Lee, Gi-Young Yang, Young-Kwan Park, J. Kong
An efficient modeling methodology for abnormally structured MOS transistors is presented. Contrary to the previous method utilizing a 3D device simulator, only the 3D Poisson solver is used to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. For the frequent modifications of the layout design, the easiness of the proposed method guarantees the efficient reflection of the current degradation effect in circuit simulation. This method is applied to 0.17 /spl mu/m DRAM process and the good agreements with the measured data are examined.
{"title":"Characterizing the current degradation of abnormally structured MOS transistors using a 3D Poisson solver","authors":"Jin-Kyu Park, Keun-Ho Lee, C. Lee, Gi-Young Yang, Young-Kwan Park, J. Kong","doi":"10.1109/ISQED.2002.996765","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996765","url":null,"abstract":"An efficient modeling methodology for abnormally structured MOS transistors is presented. Contrary to the previous method utilizing a 3D device simulator, only the 3D Poisson solver is used to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. For the frequent modifications of the layout design, the easiness of the proposed method guarantees the efficient reflection of the current degradation effect in circuit simulation. This method is applied to 0.17 /spl mu/m DRAM process and the good agreements with the measured data are examined.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91541241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996772
Wai-Ching Douglas Lam, Cheng-Kok Koh, C. Tsao
Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose an algorithm that performs clock skew scheduling to minimize the number of simultaneous switching events such that the power supply noise is suppressed. Our approach establishes a direct relationship between current (drawn by a circuit element, sequential or combinational) and skew by the concept of envelope waveforms, using a graphical representation. We provide a graph-based scheduling approach to reduce the peak current and to minimize the difference between the current peaks and valleys such that the current profile of the entire circuit is smoothened. Our approach also guarantees that the resulting clock schedule does not violate setup and hold time constraints. Experimental results on benchmark circuits show an average reduction of 19.6% in the peak current, an average reduction of 38.7% in the current swing, and an average reduction of 47.4% in voltage variations in the power lines.
{"title":"Power supply noise suppression via clock skew scheduling","authors":"Wai-Ching Douglas Lam, Cheng-Kok Koh, C. Tsao","doi":"10.1109/ISQED.2002.996772","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996772","url":null,"abstract":"Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose an algorithm that performs clock skew scheduling to minimize the number of simultaneous switching events such that the power supply noise is suppressed. Our approach establishes a direct relationship between current (drawn by a circuit element, sequential or combinational) and skew by the concept of envelope waveforms, using a graphical representation. We provide a graph-based scheduling approach to reduce the peak current and to minimize the difference between the current peaks and valleys such that the current profile of the entire circuit is smoothened. Our approach also guarantees that the resulting clock schedule does not violate setup and hold time constraints. Experimental results on benchmark circuits show an average reduction of 19.6% in the peak current, an average reduction of 38.7% in the current swing, and an average reduction of 47.4% in voltage variations in the power lines.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81665930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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