Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241684
S. Martinie, O. Rozeau, T. Poiroux, P. Scheer, Salim El Ghouli, Mihyun Kang, A. Juge, Harrison Lee
With the maturity of CMOS technologies and their use for low power various analog and digital applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Indeed, with the decrease of supply voltages/currents and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI) technologies, the devices operate close to the weak-moderate inversion, where gm/Id Figure is impacted by effects like the depletion of source/drain electrodes and the parasitic currents such as Impact ionization current in moderate inver-sion and Gate Leakage current in weak inversion, can have a significant impact on the model accuracy. This paper describes the latest significant improvements of L-UTSOI model (formerly Leti-UTSOI) related to version 102.4. These model extensions are validated against Silicon experimental data.
{"title":"L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology","authors":"S. Martinie, O. Rozeau, T. Poiroux, P. Scheer, Salim El Ghouli, Mihyun Kang, A. Juge, Harrison Lee","doi":"10.23919/SISPAD49475.2020.9241684","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241684","url":null,"abstract":"With the maturity of CMOS technologies and their use for low power various analog and digital applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Indeed, with the decrease of supply voltages/currents and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI) technologies, the devices operate close to the weak-moderate inversion, where gm/Id Figure is impacted by effects like the depletion of source/drain electrodes and the parasitic currents such as Impact ionization current in moderate inver-sion and Gate Leakage current in weak inversion, can have a significant impact on the model accuracy. This paper describes the latest significant improvements of L-UTSOI model (formerly Leti-UTSOI) related to version 102.4. These model extensions are validated against Silicon experimental data.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128377134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241622
Sanghoon Myung, Jinwoo Kim, Yongwoo Jeon, Wonik Jang, I. Huh, Jaemin Kim, Songyi Han, K. Baek, Jisu Ryu, Yoon-suk Kim, Jiseong Doh, Jae-ho Kim, C. Jeong, Daesin Kim
This paper presents a novel approach to enable real-time device simulation and optimization. State-of-the-art algorithms which can describe semiconductor domain are adopted to train deep learning models whose input and output are process condition and doping profile / electrical characteristic, respectively. Our framework enables to update automatically deep learning models by estimating the uncertainty of the model prediction. Our Real-Time TCAD framework is validated on 130nm processes for display driver integration circuit (DDI), and 1) prediction time was 530,000 times faster than conventional TCAD, and time spent for process optimization was reduced by 300,000 times compared to human expert, 2) the model achieved average accuracy of 99% compared to TCAD simulation results, and thus, 3) process development time for DDI was reduced by 8 weeks.
{"title":"Real-Time TCAD: a new paradigm for TCAD in the artificial intelligence era","authors":"Sanghoon Myung, Jinwoo Kim, Yongwoo Jeon, Wonik Jang, I. Huh, Jaemin Kim, Songyi Han, K. Baek, Jisu Ryu, Yoon-suk Kim, Jiseong Doh, Jae-ho Kim, C. Jeong, Daesin Kim","doi":"10.23919/SISPAD49475.2020.9241622","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241622","url":null,"abstract":"This paper presents a novel approach to enable real-time device simulation and optimization. State-of-the-art algorithms which can describe semiconductor domain are adopted to train deep learning models whose input and output are process condition and doping profile / electrical characteristic, respectively. Our framework enables to update automatically deep learning models by estimating the uncertainty of the model prediction. Our Real-Time TCAD framework is validated on 130nm processes for display driver integration circuit (DDI), and 1) prediction time was 530,000 times faster than conventional TCAD, and time spent for process optimization was reduced by 300,000 times compared to human expert, 2) the model achieved average accuracy of 99% compared to TCAD simulation results, and thus, 3) process development time for DDI was reduced by 8 weeks.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124438945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/sispad49475.2020.9241617
{"title":"SISPAD 2020 Commentary","authors":"","doi":"10.23919/sispad49475.2020.9241617","DOIUrl":"https://doi.org/10.23919/sispad49475.2020.9241617","url":null,"abstract":"","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241676
M. L. Van de Put, G. Gaddemane, Sanjay Gopalan, M. Fischetti
We investigate theoretically the impact of the dielectric environment on electronic transport in monolayer MoS2. In particular, we extend our first-principles Monte Carlo method to account for the screening of the electron-phonon interaction by the free carriers in the layer and the dielectric environment. In addition, we include the effect of remote-phonon scattering induced by the surrounding dielectrics. For monolayer MoS2 on various dielectric substrates, we find that screening could improve the mobility significantly, but the inclusion of remote-phonon scattering degrades the mobility below its free-standing value. In our model, the introduction of gates in a dual-gate configuration does not appreciably decrease the remote-phonon interaction as it does in inversion layers or thicker films. However, for a double-gate field-effect transistor, we still obtain reasonable transport characteristics.
{"title":"Effects of the Dielectric Environment on Electronic Transport in Monolayer MoS2: Screening and Remote Phonon Scattering","authors":"M. L. Van de Put, G. Gaddemane, Sanjay Gopalan, M. Fischetti","doi":"10.23919/SISPAD49475.2020.9241676","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241676","url":null,"abstract":"We investigate theoretically the impact of the dielectric environment on electronic transport in monolayer MoS2. In particular, we extend our first-principles Monte Carlo method to account for the screening of the electron-phonon interaction by the free carriers in the layer and the dielectric environment. In addition, we include the effect of remote-phonon scattering induced by the surrounding dielectrics. For monolayer MoS2 on various dielectric substrates, we find that screening could improve the mobility significantly, but the inclusion of remote-phonon scattering degrades the mobility below its free-standing value. In our model, the introduction of gates in a dual-gate configuration does not appreciably decrease the remote-phonon interaction as it does in inversion layers or thicker films. However, for a double-gate field-effect transistor, we still obtain reasonable transport characteristics.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128817923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241648
Y. Oussaiti, D. Rideau, J. Manouvrier, V. Quenette, B. Mamdy, C. Buj, J. Grebot, H. Wehbe-Alause, A. Lopez, G. Mugny, M. Agnew, E. Lacombe, M. Pala, P. Dollfus
We present a Verilog-A model accounting for the temporal avalanche buildup and its statistics in Single-Photon Avalanche Diodes (SPADs). This physics-based approach is compared to TCAD mixed-mode analyzing predictions, as well as measurements. The buildup that can be in the order of hundreds picoseconds, affects the statistical pulse width distribution, which is experimentally verified. Furthermore, we address in detail the voltage swing across the device during avalanche and its quenching, studying its impact on power consumption. This model can help a chip designer to optimize circuits for quenching the SPAD photodiode.
{"title":"Verilog-A model for avalanche dynamics and quenching in Single-Photon Avalanche Diodes","authors":"Y. Oussaiti, D. Rideau, J. Manouvrier, V. Quenette, B. Mamdy, C. Buj, J. Grebot, H. Wehbe-Alause, A. Lopez, G. Mugny, M. Agnew, E. Lacombe, M. Pala, P. Dollfus","doi":"10.23919/SISPAD49475.2020.9241648","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241648","url":null,"abstract":"We present a Verilog-A model accounting for the temporal avalanche buildup and its statistics in Single-Photon Avalanche Diodes (SPADs). This physics-based approach is compared to TCAD mixed-mode analyzing predictions, as well as measurements. The buildup that can be in the order of hundreds picoseconds, affects the statistical pulse width distribution, which is experimentally verified. Furthermore, we address in detail the voltage swing across the device during avalanche and its quenching, studying its impact on power consumption. This model can help a chip designer to optimize circuits for quenching the SPAD photodiode.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121106506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241614
Z. Stanojević, G. Strof, Oskar Baumgartner, Gerhard Rzepa, M. Karner
We are the first to present a subband-BTE solver with a fully integrated source/drain-tunneling current calculation based on the WKB-approximation. The method is validated against ballistic NEGF calculations showing good agreement. An investigation of Si and Ge-based NWFETs is performed showing that intra-band source/drain-tunneling is not a concern for Si devices. For Ge-based PMOS devices however, tunneling leakage limits sensible $mathrm{L}_{mathrm{G}}-$scaling to around 20 nm.
{"title":"Performance and Leakage Analysis of Si and Ge NWFETs Using a Combined Subband BTE and WKB Approach","authors":"Z. Stanojević, G. Strof, Oskar Baumgartner, Gerhard Rzepa, M. Karner","doi":"10.23919/SISPAD49475.2020.9241614","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241614","url":null,"abstract":"We are the first to present a subband-BTE solver with a fully integrated source/drain-tunneling current calculation based on the WKB-approximation. The method is validated against ballistic NEGF calculations showing good agreement. An investigation of Si and Ge-based NWFETs is performed showing that intra-band source/drain-tunneling is not a concern for Si devices. For Ge-based PMOS devices however, tunneling leakage limits sensible $mathrm{L}_{mathrm{G}}-$scaling to around 20 nm.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241664
A. Royet, L. Dagault, S. Kerdilès, P. Alba, J. P. Barnes, Filadelfo Cristiano, Karim Huet
Physical parameters calibration (dielectric and alloy properties) of Si$_{1-X}$Gex alloys is presented in order to simulate the Ultra Violet-Nanosecond Laser Annealing (UV-NLA) of this material for Si/ Si$_{1-X}$Gex based MOS devices. Optical and physical parameters are extracted and modeled from experimental characterizations for several Ge concentrations and then fitted to match experimental laser annealing results. A good prediction, in terms of melt depth and melting duration, is achieved for different Ge concentrations between 20 and 40%, usually encountered in Si$_{1-X}$Gex CMOS integration process.
{"title":"Undoped SiGe material calibration for numerical nanosecond laser annealing simulations","authors":"A. Royet, L. Dagault, S. Kerdilès, P. Alba, J. P. Barnes, Filadelfo Cristiano, Karim Huet","doi":"10.23919/SISPAD49475.2020.9241664","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241664","url":null,"abstract":"Physical parameters calibration (dielectric and alloy properties) of Si$_{1-X}$Gex alloys is presented in order to simulate the Ultra Violet-Nanosecond Laser Annealing (UV-NLA) of this material for Si/ Si$_{1-X}$Gex based MOS devices. Optical and physical parameters are extracted and modeled from experimental characterizations for several Ge concentrations and then fitted to match experimental laser annealing results. A good prediction, in terms of melt depth and melting duration, is achieved for different Ge concentrations between 20 and 40%, usually encountered in Si$_{1-X}$Gex CMOS integration process.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241668
Gijae Kang, Joohyun Jeon, Junsoo Kim, H. Ahn, I. Jang, D. Kim
We investigate the dopant trap level and equilibrium concentration of Si(110)/a-SiO2 2 interface with a wide variety of dopants (B, C, N, Br, Cl, F and H). The electronic and atomic properties of intrinsic and extrinsic defects are analyzed using First-principles calculation. It is shown that the average trap levels for hole and electron deepen as the electronegativity of the dopant increases. Also, we applied a simple thermodynamic model to evaluate the equilibrium concentration of active trap as a function of dopant concentration at the interface. From the model it turns out that H and F completely passivate the intrinsic Pb center of Si and reduce the trap concentration, while other elements, especially N, Br and Cl, induces new trap states which amounts to several times more than the pre-existing Pb center.
{"title":"First-principles study of dopant trap level and concentration in Si(110)/a-SiO2 interface","authors":"Gijae Kang, Joohyun Jeon, Junsoo Kim, H. Ahn, I. Jang, D. Kim","doi":"10.23919/SISPAD49475.2020.9241668","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241668","url":null,"abstract":"We investigate the dopant trap level and equilibrium concentration of Si(110)/a-SiO2 2 interface with a wide variety of dopants (B, C, N, Br, Cl, F and H). The electronic and atomic properties of intrinsic and extrinsic defects are analyzed using First-principles calculation. It is shown that the average trap levels for hole and electron deepen as the electronegativity of the dopant increases. Also, we applied a simple thermodynamic model to evaluate the equilibrium concentration of active trap as a function of dopant concentration at the interface. From the model it turns out that H and F completely passivate the intrinsic Pb center of Si and reduce the trap concentration, while other elements, especially N, Br and Cl, induces new trap states which amounts to several times more than the pre-existing Pb center.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134548897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241625
A. Pal, E. Bazizi, Liu Jiang, Mehdi Saremi, B. Alexander, Buvna Ayyagari-Sangamalli
Though single diffusion break (SDB) acts as an efficient area-scaling enabler for current CMOS technology nodes, it degrades devices’ variability performance, which can be mitigated by enabling self-aligned SDB (SA-SDB) technology. Unfortunately, SA-SDB causes PMOS performance degradation due to channel stress relaxation. To solve this issue, we propose material engineering of SA-SDB technology to improve PMOS performance. Using 3D-TCAD simulations, we show that by using stressed oxide for the SA-SDB cavity fill, both PMOS and NMOS device performance can be improved. Furthermore, using ring-oscillator as a representative circuit for CMOS technology evaluation, we showed that the circuit performance can be improved by 13-21% for 2-3 GPa stress in the oxide, thus enabling simultaneous area-scaling and circuit and variability performance improvement with SA-SDB technology for advanced CMOS nodes.
{"title":"Self-Aligned Single Diffusion Break Technology Optimization Through Material Engineering for Advanced CMOS Nodes","authors":"A. Pal, E. Bazizi, Liu Jiang, Mehdi Saremi, B. Alexander, Buvna Ayyagari-Sangamalli","doi":"10.23919/SISPAD49475.2020.9241625","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241625","url":null,"abstract":"Though single diffusion break (SDB) acts as an efficient area-scaling enabler for current CMOS technology nodes, it degrades devices’ variability performance, which can be mitigated by enabling self-aligned SDB (SA-SDB) technology. Unfortunately, SA-SDB causes PMOS performance degradation due to channel stress relaxation. To solve this issue, we propose material engineering of SA-SDB technology to improve PMOS performance. Using 3D-TCAD simulations, we show that by using stressed oxide for the SA-SDB cavity fill, both PMOS and NMOS device performance can be improved. Furthermore, using ring-oscillator as a representative circuit for CMOS technology evaluation, we showed that the circuit performance can be improved by 13-21% for 2-3 GPa stress in the oxide, thus enabling simultaneous area-scaling and circuit and variability performance improvement with SA-SDB technology for advanced CMOS nodes.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131436898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241688
Naoya Uene, T. Mabuchi, M. Zaitsu, Shigeo Yasuhara, T. Tokumasu
In order to form a SiGe thin film by chemical vapor deposition (CVD) with a suitable quality for advanced devices, the relationships between materials/process and structure/composition are needed to be clarified at the atomic level. We simulated SiGe CVD by using reactive force-field (ReaxFF) molecular dynamics simulations, especially on binary systems of SiHx + GeHx, and derived the influence of the substrate temperature and these ratios of gaseous species on the crystallinity and compositions in the thin films. The crystallinity increases as the substrate temperature increases, and the lowest crystallinity is obtained at the ratios of gaseous species 0.5 and 0.7 for the SiH3 and SiH2, respectively. As the substrate temperature increases, the hydrogen content decreases while Si and Ge content tend to increase. These trends can be seen in relevant studies. Through this simulation we successfully observe that the reactivity of gaseous species greatly affects the crystallinity and compositions in the thin films.
{"title":"Reactive Force-Field Molecular Dynamics Study of the Silicon-Germanium Deposition Processes by Plasma Enhanced Chemical Vapor Deposition","authors":"Naoya Uene, T. Mabuchi, M. Zaitsu, Shigeo Yasuhara, T. Tokumasu","doi":"10.23919/SISPAD49475.2020.9241688","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241688","url":null,"abstract":"In order to form a SiGe thin film by chemical vapor deposition (CVD) with a suitable quality for advanced devices, the relationships between materials/process and structure/composition are needed to be clarified at the atomic level. We simulated SiGe CVD by using reactive force-field (ReaxFF) molecular dynamics simulations, especially on binary systems of SiHx + GeHx, and derived the influence of the substrate temperature and these ratios of gaseous species on the crystallinity and compositions in the thin films. The crystallinity increases as the substrate temperature increases, and the lowest crystallinity is obtained at the ratios of gaseous species 0.5 and 0.7 for the SiH3 and SiH2, respectively. As the substrate temperature increases, the hydrogen content decreases while Si and Ge content tend to increase. These trends can be seen in relevant studies. Through this simulation we successfully observe that the reactivity of gaseous species greatly affects the crystallinity and compositions in the thin films.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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