Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241674
F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. Mattausch, H. Takatsuka
Our investigation focuses on accurate circuit aging prediction for bulk MOSFETs. A self-consistent aging modeling is proposed, which considers the trap-density N trap increase as the aging origin. This N trap s considered in the Poisson equation together with other charges induced within MOSFET. It is demonstrated that a universal relationship of the N trap increase as a function of integrated substrate current, caused by device stress, can describe the MOSFET aging in a simple way for any device-operating conditions. An exponential increase with constant and unitary slope of the N trap is found to successfully predict the aging phenomena, reaching a saturation for high stress degradation. The model universality is verified additionally for any device size. Comparison with existing conventional aging modeling for circuit simulation is discussed for demonstrating the simplifications due to the developed modeling approach.
{"title":"Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling","authors":"F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. Mattausch, H. Takatsuka","doi":"10.23919/SISPAD49475.2020.9241674","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241674","url":null,"abstract":"Our investigation focuses on accurate circuit aging prediction for bulk MOSFETs. A self-consistent aging modeling is proposed, which considers the trap-density N trap increase as the aging origin. This N trap s considered in the Poisson equation together with other charges induced within MOSFET. It is demonstrated that a universal relationship of the N trap increase as a function of integrated substrate current, caused by device stress, can describe the MOSFET aging in a simple way for any device-operating conditions. An exponential increase with constant and unitary slope of the N trap is found to successfully predict the aging phenomena, reaching a saturation for high stress degradation. The model universality is verified additionally for any device size. Comparison with existing conventional aging modeling for circuit simulation is discussed for demonstrating the simplifications due to the developed modeling approach.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123659548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241642
Xujiao Gao, L. Tracy, E. Anderson, Deanna Campbell, J. Ivie, T. Lu, D. Mamaluy, S. Schmucker, S. Misra
One big challenge of the emerging atomic precision advanced manufacturing (APAM) technology for microelectronics application is to realize APAM devices that operate at room temperature (RT). We demonstrate that semiclassical technology computer aided design (TCAD) device simulation tool can be employed to understand current leakage and improve APAM device design for RT operation. To establish the applicability of semiclassical simulation, we first show that a semiclassical impurity scattering model with the Fermi-Dirac statistics can explain the very low mobility in APAM devices quite well; we also show semiclassical TCAD reproduces measured sheet resistances when proper mobility values are used. We then apply semiclassical TCAD to simulate current leakage in realistic APAM wires. With insights from modeling, we were able to improve device design, fabricate Hall bars, and demonstrate RT operation for the very first time.
{"title":"Modeling Assisted Room Temperature Operation of Atomic Precision Advanced Manufacturing Devices","authors":"Xujiao Gao, L. Tracy, E. Anderson, Deanna Campbell, J. Ivie, T. Lu, D. Mamaluy, S. Schmucker, S. Misra","doi":"10.23919/SISPAD49475.2020.9241642","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241642","url":null,"abstract":"One big challenge of the emerging atomic precision advanced manufacturing (APAM) technology for microelectronics application is to realize APAM devices that operate at room temperature (RT). We demonstrate that semiclassical technology computer aided design (TCAD) device simulation tool can be employed to understand current leakage and improve APAM device design for RT operation. To establish the applicability of semiclassical simulation, we first show that a semiclassical impurity scattering model with the Fermi-Dirac statistics can explain the very low mobility in APAM devices quite well; we also show semiclassical TCAD reproduces measured sheet resistances when proper mobility values are used. We then apply semiclassical TCAD to simulate current leakage in realistic APAM wires. With insights from modeling, we were able to improve device design, fabricate Hall bars, and demonstrate RT operation for the very first time.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115020605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241653
T. Dutta, F. Adamu-Lema, A. Asenov, Y. Widjaja, Valerii Nebesnyi
For the first time, physical insights into the writing process in the bi-stable 1-transistor SRAM cells are provided using dynamic (time dependent) TCAD simulations. The simulations are based on 28 nm planar CMOS technology, and the setup is carefully calibrated against available experimental data. Based on the simulations, we were able to identify clearly the mechanisms involved in the write ‘1’ operation. The dependence of the writing process on drain and gate bias conditions was also investigated.
{"title":"Dynamic Simulation of Write ‘1’ Operation in the Bi-stable 1-Transistor SRAM Cell","authors":"T. Dutta, F. Adamu-Lema, A. Asenov, Y. Widjaja, Valerii Nebesnyi","doi":"10.23919/SISPAD49475.2020.9241653","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241653","url":null,"abstract":"For the first time, physical insights into the writing process in the bi-stable 1-transistor SRAM cells are provided using dynamic (time dependent) TCAD simulations. The simulations are based on 28 nm planar CMOS technology, and the setup is carefully calibrated against available experimental data. Based on the simulations, we were able to identify clearly the mechanisms involved in the write ‘1’ operation. The dependence of the writing process on drain and gate bias conditions was also investigated.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241654
S. S. Raju, Boyan Wang, Kashyap Mehta, M. Xiao, Yuhao Zhang, H. Wong
In this paper, we propose and study the use of noise to avoid the overfitting issue in Technology Computer-Aided Design-augmented machine learning (TCAD-ML). TCAD-ML uses TCAD to generate sufficient data to train ML models for defect detection and reverse engineering by taking electrical characteristics such as Current-Voltage, IV, and Capacitance-Voltage, CV, curves as inputs. For example, the model can be used to deduce the epitaxial thicknesses of a p-i-n diode or the ambient temperature of a Schottky diode being measured, based on a givenIV curve. The models developed by TCAD-ML usually have overfitting issues when it is applied to experimental IV curves or IV curves generated with different TCAD setup. To avoid this issue, white Gaussian noise is added to the TCAD generated curves before ML. We show that by choosing the noise level properly, overfitting can be avoided. This is demonstrated successfully by using the TCAD-ML model to predict 1) the epitaxial thicknesses of a set of TCAD silicon diode IV’s generated with different settings (extra doping variations) than the settings in the training data and 2) the ambient temperature of experimental IV’s of Ga2O3 Schottky diode. Moreover, domain expertise is not required in the ML process.
{"title":"Application of Noise to Avoid Overfitting in TCAD Augmented Machine Learning","authors":"S. S. Raju, Boyan Wang, Kashyap Mehta, M. Xiao, Yuhao Zhang, H. Wong","doi":"10.23919/SISPAD49475.2020.9241654","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241654","url":null,"abstract":"In this paper, we propose and study the use of noise to avoid the overfitting issue in Technology Computer-Aided Design-augmented machine learning (TCAD-ML). TCAD-ML uses TCAD to generate sufficient data to train ML models for defect detection and reverse engineering by taking electrical characteristics such as Current-Voltage, IV, and Capacitance-Voltage, CV, curves as inputs. For example, the model can be used to deduce the epitaxial thicknesses of a p-i-n diode or the ambient temperature of a Schottky diode being measured, based on a givenIV curve. The models developed by TCAD-ML usually have overfitting issues when it is applied to experimental IV curves or IV curves generated with different TCAD setup. To avoid this issue, white Gaussian noise is added to the TCAD generated curves before ML. We show that by choosing the noise level properly, overfitting can be avoided. This is demonstrated successfully by using the TCAD-ML model to predict 1) the epitaxial thicknesses of a set of TCAD silicon diode IV’s generated with different settings (extra doping variations) than the settings in the training data and 2) the ambient temperature of experimental IV’s of Ga2O3 Schottky diode. Moreover, domain expertise is not required in the ML process.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132743380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241638
Yohan Kim, Sanghoon Myung, Jisu Ryu, C. Jeong, Daesin Kim
This paper proposes a novel compact modeling framework based on artificial neural networks and physics informed machine learning techniques. This physics- augmented neural compact model shows highly accurate fitting abilities and physically consistent inferences even at the unseen data. It is also scalable and technology independent, and consequently, is suitable for electrical modeling of new emerging devices. In addition, this neural compact model is able to cover both digital and analog circuit analysis due to the weight decay regularization as well as high order derivative losses. Finally, it is applied to promising DRAM and Logic technologies to be evaluated in terms of its scalability and fitting accuracy. The CMC’s (Compact Model Coalition) standard model API (Application Programming Interface) supports the custom model implementation for SPICE. Therefore, this framework enables the circuit simulators to assess technology-independent PPA (Power, Performance, Area) and early-stage DTCO (Design Technology Cooptimization) for new emerging devices.
本文提出了一种基于人工神经网络和物理信息机器学习技术的新型紧凑建模框架。这种物理增强的神经紧凑模型显示出高度精确的拟合能力和物理上一致的推论，即使在看不见的数据。它还具有可扩展性和技术独立性，因此适用于新兴设备的电气建模。此外，由于权重衰减正则化和高阶导数损失，该神经紧凑模型能够覆盖数字和模拟电路分析。最后，将其应用于有前途的DRAM和Logic技术，以评估其可扩展性和拟合精度。CMC (Compact Model Coalition)的标准模型API (Application Programming Interface)支持SPICE的自定义模型实现。因此，该框架使电路模拟器能够评估与技术无关的PPA(功率，性能，面积)和早期DTCO(设计技术协同优化)用于新兴设备。
{"title":"Physics-augmented Neural Compact Model for Emerging Device Technologies","authors":"Yohan Kim, Sanghoon Myung, Jisu Ryu, C. Jeong, Daesin Kim","doi":"10.23919/SISPAD49475.2020.9241638","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241638","url":null,"abstract":"This paper proposes a novel compact modeling framework based on artificial neural networks and physics informed machine learning techniques. This physics- augmented neural compact model shows highly accurate fitting abilities and physically consistent inferences even at the unseen data. It is also scalable and technology independent, and consequently, is suitable for electrical modeling of new emerging devices. In addition, this neural compact model is able to cover both digital and analog circuit analysis due to the weight decay regularization as well as high order derivative losses. Finally, it is applied to promising DRAM and Logic technologies to be evaluated in terms of its scalability and fitting accuracy. The CMC’s (Compact Model Coalition) standard model API (Application Programming Interface) supports the custom model implementation for SPICE. Therefore, this framework enables the circuit simulators to assess technology-independent PPA (Power, Performance, Area) and early-stage DTCO (Design Technology Cooptimization) for new emerging devices.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121868973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241629
N. D. Le, B. Davier, P. Dollfus, M. Pala, A. Bournel, J. Saint-Martin
Our home made Full-Band particle Monte Carlo is used to investigate the thermal interface conductance at Silicon/Germanium heterojunctions.
利用自制的全波段粒子蒙特卡罗方法研究了硅/锗异质结的热界面电导。
{"title":"Full Band Monte Carlo simulation of phonon transfer at interfaces","authors":"N. D. Le, B. Davier, P. Dollfus, M. Pala, A. Bournel, J. Saint-Martin","doi":"10.23919/SISPAD49475.2020.9241629","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241629","url":null,"abstract":"Our home made Full-Band particle Monte Carlo is used to investigate the thermal interface conductance at Silicon/Germanium heterojunctions.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241669
D. Chanemougame, Jeffrey Smith, P. Gutwin, Brandon Byrns, L. Liebmann
New tools and methodologies are fused with conventional elements of the process-design-kit (PDK) and design enablement to introduce a rigorous yet fast and agile technology prototyping platform. This design technology cooptimization (DTCO) solution replaces the rigid, time and resources consuming PDK to enhance the core functions critical to evaluate power, performance area and cost (PPAC). Any technology definition with any device or process integration innovation can be evaluated at the standard cell level first, and then at the block level to explore and understand the requirements of different design applications. The flexibility and fast turn-around make it practical to imagine, test and compare many technology prototypes. From simple evolutions to innovative disruptions, the feasibility and value of the technology choices and hardware tools required can be identified early with great detail, significantly accelerating the development of future process tools. To illustrate the efficiency of the platform, complementary-FET (CFET) [1] technologies are compared to reference finFET technologies. As we approach the fundamental limits of dimensional scaling, with so many choices ahead of us including 3D constructs, we need efficient technology prototyping to navigate and steer in the right direction.
{"title":"Agile Pathfinding Technology Prototyping: the Hunt for Directional Correctness","authors":"D. Chanemougame, Jeffrey Smith, P. Gutwin, Brandon Byrns, L. Liebmann","doi":"10.23919/SISPAD49475.2020.9241669","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241669","url":null,"abstract":"New tools and methodologies are fused with conventional elements of the process-design-kit (PDK) and design enablement to introduce a rigorous yet fast and agile technology prototyping platform. This design technology cooptimization (DTCO) solution replaces the rigid, time and resources consuming PDK to enhance the core functions critical to evaluate power, performance area and cost (PPAC). Any technology definition with any device or process integration innovation can be evaluated at the standard cell level first, and then at the block level to explore and understand the requirements of different design applications. The flexibility and fast turn-around make it practical to imagine, test and compare many technology prototypes. From simple evolutions to innovative disruptions, the feasibility and value of the technology choices and hardware tools required can be identified early with great detail, significantly accelerating the development of future process tools. To illustrate the efficiency of the platform, complementary-FET (CFET) [1] technologies are compared to reference finFET technologies. As we approach the fundamental limits of dimensional scaling, with so many choices ahead of us including 3D constructs, we need efficient technology prototyping to navigate and steer in the right direction.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125150642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241660
Alberto Sciuto, I. Deretzis, G. Fisicaro, S. Lombardo, A. Magna, M. Grimaldi, K. Huet, Bobby Lespinasse, Armand Verstraete, B. Curvers, I. Bejenari, A. Burenkov, P. Pichler
Current semiconductor device manufacturing often needs the integration of annealing process steps with a low thermal budget; and, among them, pulsed laser annealing (LA) is a reliable option. Consequently, the use of LA specialized Technology Computer Aided Design (TCAD) models is emerging as a support for the development of this particular heating methods. Anyway, models already implemented in academic or commercial packages usually consider some approximations which can lead to inaccurate predictions if they are applied in rather common configurations of nano-device: i.e. structures with nm wide elements where amorphous pockets are also present. In particular, in these cases non-diffusive thermal transport and explosive crystallization could take place. Here we present upgrades of the LA TCAD models allowing the simulation of these phenomena. We will demonstrate that these models can be reliably integrated in the current TCAD packages discussing the key features of the numerical solutions features in some particular cases.
{"title":"Advanced simulations on laser annealing: explosive crystallization and phonon transport corrections","authors":"Alberto Sciuto, I. Deretzis, G. Fisicaro, S. Lombardo, A. Magna, M. Grimaldi, K. Huet, Bobby Lespinasse, Armand Verstraete, B. Curvers, I. Bejenari, A. Burenkov, P. Pichler","doi":"10.23919/SISPAD49475.2020.9241660","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241660","url":null,"abstract":"Current semiconductor device manufacturing often needs the integration of annealing process steps with a low thermal budget; and, among them, pulsed laser annealing (LA) is a reliable option. Consequently, the use of LA specialized Technology Computer Aided Design (TCAD) models is emerging as a support for the development of this particular heating methods. Anyway, models already implemented in academic or commercial packages usually consider some approximations which can lead to inaccurate predictions if they are applied in rather common configurations of nano-device: i.e. structures with nm wide elements where amorphous pockets are also present. In particular, in these cases non-diffusive thermal transport and explosive crystallization could take place. Here we present upgrades of the LA TCAD models allowing the simulation of these phenomena. We will demonstrate that these models can be reliably integrated in the current TCAD packages discussing the key features of the numerical solutions features in some particular cases.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129815041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241656
Sung-Min Hong, Phil-Hun Ahn
In this work, an AC nonequilibrium Green function (NEGF) simulation for nanosheet MOSFETs is presented. The AC NEGF equations are discretized using a decoupled mode-space approach for efficient implementation. The Poisson equation is solved self consistently to obtain the electrostatic potential. Our in-house device simulator, G-Device, is used to simulate the AC responses on nanosheet MOSFETs.
{"title":"AC NEGF Simulation of Nanosheet MOSFETs","authors":"Sung-Min Hong, Phil-Hun Ahn","doi":"10.23919/SISPAD49475.2020.9241656","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241656","url":null,"abstract":"In this work, an AC nonequilibrium Green function (NEGF) simulation for nanosheet MOSFETs is presented. The AC NEGF equations are discretized using a decoupled mode-space approach for efficient implementation. The Poisson equation is solved self consistently to obtain the electrostatic potential. Our in-house device simulator, G-Device, is used to simulate the AC responses on nanosheet MOSFETs.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124357808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.23919/SISPAD49475.2020.9241639
Uma Sharma, S. Mahapatra
Sentaurus TCAD is enabled to calculate interface trap generation ($Delta N_{IT}$) during Negative Bias Temperature Instability (NBTI) under drain bias (VD) and self-heating (SH) effects. The setup is calibrated with pure NBTI (VD=0V) experimental data, and is further used to determine the NBTI component during Hot Carrier Degradation (HCD) stress. Such decomposition of NBTI and HCD is demonstrated for multiple fin length (FL) p-FinFETs to model HCD experimental data at different $VG/VD$ stress.
{"title":"A TCAD Framework for Assessing NBTI Impact Under Drain Bias and Self-Heating Effects in Replacement Metal Gate (RMG) p-FinFETs","authors":"Uma Sharma, S. Mahapatra","doi":"10.23919/SISPAD49475.2020.9241639","DOIUrl":"https://doi.org/10.23919/SISPAD49475.2020.9241639","url":null,"abstract":"Sentaurus TCAD is enabled to calculate interface trap generation ($Delta N_{IT}$) during Negative Bias Temperature Instability (NBTI) under drain bias (VD) and self-heating (SH) effects. The setup is calibrated with pure NBTI (VD=0V) experimental data, and is further used to determine the NBTI component during Hot Carrier Degradation (HCD) stress. Such decomposition of NBTI and HCD is demonstrated for multiple fin length (FL) p-FinFETs to model HCD experimental data at different $VG/VD$ stress.","PeriodicalId":206964,"journal":{"name":"2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124105015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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