Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852636
Sammy Cheung, Kar Keng Chua, B. Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, C. Sung, Kim Pin Tan, Yu Fong Tan, C. K. Wong
A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.
讨论了一种用于高性能系统集成的百万门可编程逻辑器件(PLD)。APEX 20K1000E采用0.18 /spl mu/m CMOS工艺制造。该芯片支持多种I/O标准，采用集成的LVDS (low voltage differential signaling)接口时，数据带宽可达622 Mbps。多个片上锁相环(PLL)提高性能并提供时钟频率合成。嵌入式内容可寻址内存(CAM)增强了快速搜索应用程序的性能。
{"title":"A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM","authors":"Sammy Cheung, Kar Keng Chua, B. Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, C. Sung, Kim Pin Tan, Yu Fong Tan, C. K. Wong","doi":"10.1109/CICC.2000.852636","DOIUrl":"https://doi.org/10.1109/CICC.2000.852636","url":null,"abstract":"A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79195344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852664
T. Yamauchi, M. Kinoshita, T. Amano, K. Dosaka, K. Arimoto, H. Ozaki, M. Yamada, T. Yoshihara
This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.
{"title":"Design methodology of the embedded DRAM with the virtual socket architecture","authors":"T. Yamauchi, M. Kinoshita, T. Amano, K. Dosaka, K. Arimoto, H. Ozaki, M. Yamada, T. Yoshihara","doi":"10.1109/CICC.2000.852664","DOIUrl":"https://doi.org/10.1109/CICC.2000.852664","url":null,"abstract":"This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72666500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852692
J. Lee, C. Tu, Wei-Hong Chen
A fully differential CMOS transconductor with 3 V linear input range is proposed. The Gm value of the transconductor is tunable through a current division scheme. A current mode arithmetic method is used to adaptively bias the transconductor tuning stage. A 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter using this highly linear transconductor achieves a IM3 distortion at 300 kHz of -62 dBc for a 2 Vppd input signal. The filter was fabricated with a double poly triple metal 0.35 /spl mu/m CMOS process and consumes 66 mW.
{"title":"A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSL","authors":"J. Lee, C. Tu, Wei-Hong Chen","doi":"10.1109/CICC.2000.852692","DOIUrl":"https://doi.org/10.1109/CICC.2000.852692","url":null,"abstract":"A fully differential CMOS transconductor with 3 V linear input range is proposed. The Gm value of the transconductor is tunable through a current division scheme. A current mode arithmetic method is used to adaptively bias the transconductor tuning stage. A 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter using this highly linear transconductor achieves a IM3 distortion at 300 kHz of -62 dBc for a 2 Vppd input signal. The filter was fabricated with a double poly triple metal 0.35 /spl mu/m CMOS process and consumes 66 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72760942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852606
R. Naiknaware, T. Fiez
A /spl Delta//spl Sigma/ ADC designed in a 0.6 /spl mu/m CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 k/spl Omega/ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply.
{"title":"142 dB /spl Delta//spl Sigma/ ADC with a 100 nV LSB in a 3 V CMOS process","authors":"R. Naiknaware, T. Fiez","doi":"10.1109/CICC.2000.852606","DOIUrl":"https://doi.org/10.1109/CICC.2000.852606","url":null,"abstract":"A /spl Delta//spl Sigma/ ADC designed in a 0.6 /spl mu/m CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 k/spl Omega/ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83449927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852713
Gregg N. Hoyer, C. Sechen
Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic's ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 /spl mu/m, 5 V CMOS process.
本地时钟(LC)动态逻辑是一种异步电路技术，它使用事件驱动控制器来调节由闭锁动态逻辑门组成的细粒度管道。本文扩展了该方法，以包括连续管道阶段之间的反馈。LC动态逻辑处理反馈的能力通过在1 /spl mu/m, 5 V CMOS工艺中实现的660mhz串行/并行乘法器的设计来说明。
{"title":"A locally-clocked dynamic logic serial/parallel multiplier","authors":"Gregg N. Hoyer, C. Sechen","doi":"10.1109/CICC.2000.852713","DOIUrl":"https://doi.org/10.1109/CICC.2000.852713","url":null,"abstract":"Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic's ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 /spl mu/m, 5 V CMOS process.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85770175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852679
J. Sevenhans
During the nineties we have witnessed a string of advances in Silicon RF integration: from the introduction of the first integrated Si bipolar radios for GSM and DECT in the late eighties to the full single chip integration capabilities today using SiGe BiCMOS technologies. Where RF design used to be a black art, it is becoming a "normal practice" today.
{"title":"Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS","authors":"J. Sevenhans","doi":"10.1109/CICC.2000.852679","DOIUrl":"https://doi.org/10.1109/CICC.2000.852679","url":null,"abstract":"During the nineties we have witnessed a string of advances in Silicon RF integration: from the introduction of the first integrated Si bipolar radios for GSM and DECT in the late eighties to the full single chip integration capabilities today using SiGe BiCMOS technologies. Where RF design used to be a black art, it is becoming a \"normal practice\" today.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91444377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852651
Gi-Young Yang, Y. Kim, Taek-Soo Kim, J. Kong
This paper describes the S-TFT model developed for poly-Si TFT which improves the accuracy dramatically. The proposed model emphasis is on deriving the large parasitic resistance characteristics at low Vds by adding the junction current to the on-current. The physical-based subthreshold and off-state current model are also considered. The model guarantees the continuities of the current and the derivatives. Compared to the RPI model, known to be the best model, the proposed model improved overall simulation speed by 40-50% due to the better convergence characteristics.
{"title":"S-TFT: an analytical model of polysilicon thin-film transistors for circuit simulation","authors":"Gi-Young Yang, Y. Kim, Taek-Soo Kim, J. Kong","doi":"10.1109/CICC.2000.852651","DOIUrl":"https://doi.org/10.1109/CICC.2000.852651","url":null,"abstract":"This paper describes the S-TFT model developed for poly-Si TFT which improves the accuracy dramatically. The proposed model emphasis is on deriving the large parasitic resistance characteristics at low Vds by adding the junction current to the on-current. The physical-based subthreshold and off-state current model are also considered. The model guarantees the continuities of the current and the derivatives. Compared to the RPI model, known to be the best model, the proposed model improved overall simulation speed by 40-50% due to the better convergence characteristics.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90673568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852619
T. Miwa, Junichi Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio
This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.
{"title":"NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors","authors":"T. Miwa, Junichi Yamada, H. Koike, H. Toyoshima, K. Amanuma, S. Kobayashi, T. Tatsumi, Y. Maejima, H. Hada, T. Kunio","doi":"10.1109/CICC.2000.852619","DOIUrl":"https://doi.org/10.1109/CICC.2000.852619","url":null,"abstract":"This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88529306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852674
F. Lu, J. Min, Sam Liu, K. Cameron, Christopher Jones, O. Lee, Johnson Li, A. Buchwald, S. Jantzi, C. Ward, K. Choi, Jim Searle, H. Samueli
This paper presents a single-chip cable upstream receiver which demodulates QPSK/16-QAM burst data in a frequency-agile, time-division multiple access (TDMA) scheme. An analog front end (AFE), an all-digital receiver and an FEC decoder are integrated on chip. The AFE performs coarse gain setting and signal quantization on either an IF input or baseband I/Q inputs. The digital QAM receiver contains a quadrature down-mixer, multi-stage decimators, Nyquist filters, carrier/timing acquisition loops, and an adaptive equalizer. The FEC decoder consists of a programmable descrambler and a versatile Reed-Solomon decoder. The chip occupies 4.7/spl times/7.8 mm/sup 2/ die area in a 0.35-/spl mu/m CMOS process, and consumes 1.0 W at 3.3 V in a 100-pin PQFP.
{"title":"A single-chip universal burst receiver for cable modem/digital cable-TV applications","authors":"F. Lu, J. Min, Sam Liu, K. Cameron, Christopher Jones, O. Lee, Johnson Li, A. Buchwald, S. Jantzi, C. Ward, K. Choi, Jim Searle, H. Samueli","doi":"10.1109/CICC.2000.852674","DOIUrl":"https://doi.org/10.1109/CICC.2000.852674","url":null,"abstract":"This paper presents a single-chip cable upstream receiver which demodulates QPSK/16-QAM burst data in a frequency-agile, time-division multiple access (TDMA) scheme. An analog front end (AFE), an all-digital receiver and an FEC decoder are integrated on chip. The AFE performs coarse gain setting and signal quantization on either an IF input or baseband I/Q inputs. The digital QAM receiver contains a quadrature down-mixer, multi-stage decimators, Nyquist filters, carrier/timing acquisition loops, and an adaptive equalizer. The FEC decoder consists of a programmable descrambler and a versatile Reed-Solomon decoder. The chip occupies 4.7/spl times/7.8 mm/sup 2/ die area in a 0.35-/spl mu/m CMOS process, and consumes 1.0 W at 3.3 V in a 100-pin PQFP.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89672565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852715
E. You, S. Choe, Chin-Man Kim, L. Varadadesikan, K. Aingaran, J. MacDonald
This paper discusses accuracy issues in parasitic extraction for the design of multimillion-transistor integrated circuits. The methodology reported aims at reducing the gap between the parasitic values estimated during implementation and the results of post-layout extraction. The objective is to obtain progressively refined interconnect models in hierarchical design flows. This methodology was developed for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.
{"title":"Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience","authors":"E. You, S. Choe, Chin-Man Kim, L. Varadadesikan, K. Aingaran, J. MacDonald","doi":"10.1109/CICC.2000.852715","DOIUrl":"https://doi.org/10.1109/CICC.2000.852715","url":null,"abstract":"This paper discusses accuracy issues in parasitic extraction for the design of multimillion-transistor integrated circuits. The methodology reported aims at reducing the gap between the parasitic values estimated during implementation and the results of post-layout extraction. The objective is to obtain progressively refined interconnect models in hierarchical design flows. This methodology was developed for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80858952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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