Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852681
A. Zolfaghari, A. Chan, Behzad Razavi
A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values of 5 nH to 266 nH and self-resonance frequencies of 11.2 GHz to 0.5 GHz. Closed-form expressions predicting the self-resonance frequency with less than 5% error have also been developed. A 1-to-2 transformer consisting of 3 stacked spirals achieves a voltage gain of 1.8 at 2.5 GHz. The structures have been fabricated in standard CMOS technologies with four and five metal layers.
{"title":"Stacked inductors and 1-to-2 transformers in CMOS technology","authors":"A. Zolfaghari, A. Chan, Behzad Razavi","doi":"10.1109/CICC.2000.852681","DOIUrl":"https://doi.org/10.1109/CICC.2000.852681","url":null,"abstract":"A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values of 5 nH to 266 nH and self-resonance frequencies of 11.2 GHz to 0.5 GHz. Closed-form expressions predicting the self-resonance frequency with less than 5% error have also been developed. A 1-to-2 transformer consisting of 3 stacked spirals achieves a voltage gain of 1.8 at 2.5 GHz. The structures have been fabricated in standard CMOS technologies with four and five metal layers.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84142503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852716
Y. Sasaki, K. Yano
We have developed a method to deal with the crosstalk effects in timing analysis. The method calculates quantitative delay degradation caused by crosstalk even when there are multiple aggressors for one victim and the signal arrival times dynamically change depending on the input patterns. The method can decrease design delay margins and is especially useful for designing high-performance LSIs.
{"title":"Multi-aggressor relative window method for timing analysis including crosstalk delay degradation","authors":"Y. Sasaki, K. Yano","doi":"10.1109/CICC.2000.852716","DOIUrl":"https://doi.org/10.1109/CICC.2000.852716","url":null,"abstract":"We have developed a method to deal with the crosstalk effects in timing analysis. The method calculates quantitative delay degradation caused by crosstalk even when there are multiple aggressors for one victim and the signal arrival times dynamically change depending on the input patterns. The method can decrease design delay margins and is especially useful for designing high-performance LSIs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86730566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852640
Qiuting Huang
In many wireless applications power consumption of an RF-IC is more important than integration level due to battery life time considerations. This has been a weak point for CMOS, which has prevented its general acceptance for demanding applications such as cellular and paging. Growing attention is now being paid to low power design of CMOS RF ICs. This paper addresses issues such as technology requirement, transceiver architecture, circuit topologies as well as the extent of integration, in the context of power consumption.
{"title":"CMOS RF design-the low power dimension","authors":"Qiuting Huang","doi":"10.1109/CICC.2000.852640","DOIUrl":"https://doi.org/10.1109/CICC.2000.852640","url":null,"abstract":"In many wireless applications power consumption of an RF-IC is more important than integration level due to battery life time considerations. This has been a weak point for CMOS, which has prevented its general acceptance for demanding applications such as cellular and paging. Growing attention is now being paid to low power design of CMOS RF ICs. This paper addresses issues such as technology requirement, transceiver architecture, circuit topologies as well as the extent of integration, in the context of power consumption.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90771769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852685
E. Abou-Allam, T. Manku, Michele Ting, M. Obrecht
In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 /spl mu/m, 0.25 /spl mu/m, 0.35 /spl mu/m, 0.5 /spl mu/m and 0.8 /spl mu/m. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 /spl mu/m for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 /spl mu/m and 50 /spl mu/m for the 0.8 /spl mu/m and 0.18 /spl mu/m gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 /spl mu/m and 0.18 /spl mu/m CMOS processes, respectively. This reduction in current is due to the fact that g/sub m//I/sub ds/ for a 0.18 /spl mu/m process is 25 V/sup -1/ whereas it is equal to 5 V/sup -1/ for a 0.5 /spl mu/m process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver.
{"title":"Impact of technology scaling on CMOS RF devices and circuits","authors":"E. Abou-Allam, T. Manku, Michele Ting, M. Obrecht","doi":"10.1109/CICC.2000.852685","DOIUrl":"https://doi.org/10.1109/CICC.2000.852685","url":null,"abstract":"In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 /spl mu/m, 0.25 /spl mu/m, 0.35 /spl mu/m, 0.5 /spl mu/m and 0.8 /spl mu/m. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 /spl mu/m for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 /spl mu/m and 50 /spl mu/m for the 0.8 /spl mu/m and 0.18 /spl mu/m gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 /spl mu/m and 0.18 /spl mu/m CMOS processes, respectively. This reduction in current is due to the fact that g/sub m//I/sub ds/ for a 0.18 /spl mu/m process is 25 V/sup -1/ whereas it is equal to 5 V/sup -1/ for a 0.5 /spl mu/m process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89159642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852643
J. Ryynänen, Kalle Kivekäs, J. Jussila, A. Pärssinen, K. Halonen
An RF front-end for dual-band, dual-mode operation is presented in this paper. The front-end consumes 22.5 mW from a 1.8 V supply and is designed to be used in direct conversion WCDMA and GSM receivers. The measured noise figure, gain, and IIP3 are 2.3 dB, 39.5 dB, and -19 dBm for GSM and 4.3 dB, 33 dB, and -14.5 dBm for WCDMA, respectively. The front-end has 27 dB gain control range in both systems.
{"title":"A dual-band RF front-end for WCDMA and GSM applications","authors":"J. Ryynänen, Kalle Kivekäs, J. Jussila, A. Pärssinen, K. Halonen","doi":"10.1109/CICC.2000.852643","DOIUrl":"https://doi.org/10.1109/CICC.2000.852643","url":null,"abstract":"An RF front-end for dual-band, dual-mode operation is presented in this paper. The front-end consumes 22.5 mW from a 1.8 V supply and is designed to be used in direct conversion WCDMA and GSM receivers. The measured noise figure, gain, and IIP3 are 2.3 dB, 39.5 dB, and -19 dBm for GSM and 4.3 dB, 33 dB, and -14.5 dBm for WCDMA, respectively. The front-end has 27 dB gain control range in both systems.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78443912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852709
E. Haratsch, K. Azadet
A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 /spl mu/m standard cell CMOS process for operation at 125 MHz.
{"title":"A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet","authors":"E. Haratsch, K. Azadet","doi":"10.1109/CICC.2000.852709","DOIUrl":"https://doi.org/10.1109/CICC.2000.852709","url":null,"abstract":"A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 /spl mu/m standard cell CMOS process for operation at 125 MHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78389131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852669
P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai
Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.
{"title":"Embedded DRAM: an element and circuit evaluation","authors":"P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai","doi":"10.1109/CICC.2000.852669","DOIUrl":"https://doi.org/10.1109/CICC.2000.852669","url":null,"abstract":"Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74316721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852707
M. Chapman, A. Demir, P. Feldmann
This paper introduces a novel, discrete optimization based method for the computation of coarsely quantized, oversampled finite length digital signals. The method, while only suitable for offline computation, is more general than the established sigma-delta encoding technique, due to its capacity to take into account complex specifications and design trade-offs. Signal generation is formulated as a linearly constrained, convex, integer quadratic programming problem which is solved through an application specific branch-and-bound algorithm. The optimization method is illustrated with a fractional-N frequency synthesizer based modulator design example.
{"title":"Finite-length signal quantization using discrete optimization","authors":"M. Chapman, A. Demir, P. Feldmann","doi":"10.1109/CICC.2000.852707","DOIUrl":"https://doi.org/10.1109/CICC.2000.852707","url":null,"abstract":"This paper introduces a novel, discrete optimization based method for the computation of coarsely quantized, oversampled finite length digital signals. The method, while only suitable for offline computation, is more general than the established sigma-delta encoding technique, due to its capacity to take into account complex specifications and design trade-offs. Signal generation is formulated as a linearly constrained, convex, integer quadratic programming problem which is solved through an application specific branch-and-bound algorithm. The optimization method is illustrated with a fractional-N frequency synthesizer based modulator design example.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75330695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852662
P. Ferguson, X. Haurie, G. Temes
A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.
{"title":"A highly linear low-power 10 bit DAC for GSM","authors":"P. Ferguson, X. Haurie, G. Temes","doi":"10.1109/CICC.2000.852662","DOIUrl":"https://doi.org/10.1109/CICC.2000.852662","url":null,"abstract":"A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73304654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852627
G. Martin, C. Lennard
The rapid advances in System-On-Chip (SOC) design enabled by improved process technology will be hindered unless major improvements are made in the specification, design and implementation of embedded software. Embedded software usually makes up at least half of the design content of an SOC device. In the future, it will constitute an even larger percentage of the design effort. In this paper we introduce a number of the major issues involved with design and integration of embedded software. We discuss some of the most recent standards, trends and capabilities that will provide effective solutions.
{"title":"Improving embedded software design and integration in SOCs","authors":"G. Martin, C. Lennard","doi":"10.1109/CICC.2000.852627","DOIUrl":"https://doi.org/10.1109/CICC.2000.852627","url":null,"abstract":"The rapid advances in System-On-Chip (SOC) design enabled by improved process technology will be hindered unless major improvements are made in the specification, design and implementation of embedded software. Embedded software usually makes up at least half of the design content of an SOC device. In the future, it will constitute an even larger percentage of the design effort. In this paper we introduce a number of the major issues involved with design and integration of embedded software. We discuss some of the most recent standards, trends and capabilities that will provide effective solutions.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83660232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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