Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852654
Paul Freud
This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.
{"title":"Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies","authors":"Paul Freud","doi":"10.1109/CICC.2000.852654","DOIUrl":"https://doi.org/10.1109/CICC.2000.852654","url":null,"abstract":"This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89983062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852626
M. Nagata, J. Nagai, T. Morie, A. Iwata
Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 /spl mu/V resolution. Activity in a digital block is a key parameter to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as ringing.
{"title":"Quantitative characterization of substrate noise for physical design guides in digital circuits","authors":"M. Nagata, J. Nagai, T. Morie, A. Iwata","doi":"10.1109/CICC.2000.852626","DOIUrl":"https://doi.org/10.1109/CICC.2000.852626","url":null,"abstract":"Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 /spl mu/V resolution. Activity in a digital block is a key parameter to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as ringing.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75958568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852704
P. Heydari, M. Pedram
Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 /spl mu/m CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model.
{"title":"Analysis of jitter due to power-supply noise in phase-locked loops","authors":"P. Heydari, M. Pedram","doi":"10.1109/CICC.2000.852704","DOIUrl":"https://doi.org/10.1109/CICC.2000.852704","url":null,"abstract":"Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 /spl mu/m CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79750700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852624
Albert Z. H. Wang
The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.
{"title":"A new design for complete on-chip ESD protection","authors":"Albert Z. H. Wang","doi":"10.1109/CICC.2000.852624","DOIUrl":"https://doi.org/10.1109/CICC.2000.852624","url":null,"abstract":"The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80242767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852635
I. Brynjolfson, Z. Zilic
Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management.
{"title":"Dynamic clock management for low power applications in FPGAs","authors":"I. Brynjolfson, Z. Zilic","doi":"10.1109/CICC.2000.852635","DOIUrl":"https://doi.org/10.1109/CICC.2000.852635","url":null,"abstract":"Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84372556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852727
Joerg Ritter, P. Molitor
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding (EZT) is a very efficient technique for image compression. However, the algorithms proposed in the literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding.
{"title":"A partitioned wavelet-based approach for image compression using FPGA's","authors":"Joerg Ritter, P. Molitor","doi":"10.1109/CICC.2000.852727","DOIUrl":"https://doi.org/10.1109/CICC.2000.852727","url":null,"abstract":"Discrete wavelet transformations (DWT) followed by embedded zerotree encoding (EZT) is a very efficient technique for image compression. However, the algorithms proposed in the literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89447400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852702
J. Phillips, K. Kundert
The proliferation of wireless and mobile products has dramatically increased the number and variety of low power, high performance electronic systems being designed. Noise is an important limiting factor in these systems. The noise generated is often cyclostationary. This type of noise cannot be predicted using SPICE, nor is it well handled by traditional test equipment such as spectrum analyzers or noise figure meters, but it is available from the new RF simulators. The origins and characteristics of cyclostationary noise are described in a way that allows designers to understand the impact of cyclostationarity on their circuits. In particular, cyclostationary noise in time-varying systems (mixers), sampling systems (switched filters and sample/holds), thresholding systems (logic circuitry), and autonomous systems (oscillators) is discussed.
{"title":"Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise","authors":"J. Phillips, K. Kundert","doi":"10.1109/CICC.2000.852702","DOIUrl":"https://doi.org/10.1109/CICC.2000.852702","url":null,"abstract":"The proliferation of wireless and mobile products has dramatically increased the number and variety of low power, high performance electronic systems being designed. Noise is an important limiting factor in these systems. The noise generated is often cyclostationary. This type of noise cannot be predicted using SPICE, nor is it well handled by traditional test equipment such as spectrum analyzers or noise figure meters, but it is available from the new RF simulators. The origins and characteristics of cyclostationary noise are described in a way that allows designers to understand the impact of cyclostationarity on their circuits. In particular, cyclostationary noise in time-varying systems (mixers), sampling systems (switched filters and sample/holds), thresholding systems (logic circuitry), and autonomous systems (oscillators) is discussed.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91462307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852729
H. Suzuki, H. Making, Y. Matsuda
A VLIW (very long instruction word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a single SIMD (single instruction, multiple data) architecture. To solve the code bloat problem in common with VLIW architectures, the proposed method enables one to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the compaction method are compared to a reference processor with the same instruction set and the same building blocks. The speed of the FP-VLIW is the fastest in all test cases. It is 26%-30% faster than the reference processor. The proposed compaction method keeps the 94% code density of the reference processor. The FP-VLIW architecture with the code compaction achieves 1.2-1.3 times of the speed performance without significant code-density deterioration.
{"title":"Novel VLIW code compaction method for a 3D geometry processor","authors":"H. Suzuki, H. Making, Y. Matsuda","doi":"10.1109/CICC.2000.852729","DOIUrl":"https://doi.org/10.1109/CICC.2000.852729","url":null,"abstract":"A VLIW (very long instruction word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a single SIMD (single instruction, multiple data) architecture. To solve the code bloat problem in common with VLIW architectures, the proposed method enables one to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the compaction method are compared to a reference processor with the same instruction set and the same building blocks. The speed of the FP-VLIW is the fastest in all test cases. It is 26%-30% faster than the reference processor. The proposed compaction method keeps the 94% code density of the reference processor. The FP-VLIW architecture with the code compaction achieves 1.2-1.3 times of the speed performance without significant code-density deterioration.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91409173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852689
Tsung-Hsien Lin, W. Kaiser
A 900 MHz PLL frequency synthesizer implemented in 0.6 /spl mu/m CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply.
{"title":"A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop","authors":"Tsung-Hsien Lin, W. Kaiser","doi":"10.1109/CICC.2000.852689","DOIUrl":"https://doi.org/10.1109/CICC.2000.852689","url":null,"abstract":"A 900 MHz PLL frequency synthesizer implemented in 0.6 /spl mu/m CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87495416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852738
M. Margarit, M. Deen
PLLs with a mixer in the loop can perform the up-conversion function in communication systems which use constant envelope modulation techniques. These loops, usually named Frequency Translational Loops (FTL), perform the up-conversion of the modulated signal from an intermediate frequency to the transmitter frequency. Frequency translational loops used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase noise and spurious levels. This paper presents the design of a monolithic FTL which operates in the IF frequency range from 100 MHz to 450 MHz and the frequency range from 900 MHz to 1.9 GHz. The output phase noise level is -120 dBc/Hz at 400 kHz offset and 165 dBc/Hz at 20 MHz offset from a 900 MHz carrier and the spurious levels are lower than 60 dB below the carrier. These characteristics make the FTL suitable for use in cellular telephony applications such as GSM/DCS.
{"title":"A low power high spectral purity frequency translational loop for wireless applications","authors":"M. Margarit, M. Deen","doi":"10.1109/CICC.2000.852738","DOIUrl":"https://doi.org/10.1109/CICC.2000.852738","url":null,"abstract":"PLLs with a mixer in the loop can perform the up-conversion function in communication systems which use constant envelope modulation techniques. These loops, usually named Frequency Translational Loops (FTL), perform the up-conversion of the modulated signal from an intermediate frequency to the transmitter frequency. Frequency translational loops used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase noise and spurious levels. This paper presents the design of a monolithic FTL which operates in the IF frequency range from 100 MHz to 450 MHz and the frequency range from 900 MHz to 1.9 GHz. The output phase noise level is -120 dBc/Hz at 400 kHz offset and 165 dBc/Hz at 20 MHz offset from a 900 MHz carrier and the spurious levels are lower than 60 dB below the carrier. These characteristics make the FTL suitable for use in cellular telephony applications such as GSM/DCS.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84558289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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