Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852714
X. Qi, Gaofeng Wang, Zhiping Yu, R. Dutton, T. Young, N. Chang
On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.
{"title":"On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation","authors":"X. Qi, Gaofeng Wang, Zhiping Yu, R. Dutton, T. Young, N. Chang","doi":"10.1109/CICC.2000.852714","DOIUrl":"https://doi.org/10.1109/CICC.2000.852714","url":null,"abstract":"On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"4 1","pages":"487-490"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79088077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852695
M. Allam, M. Anis, M. Elmasry
In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 /spl mu/m CMOS technologies.
{"title":"Effect of technology scaling on digital CMOS logic styles","authors":"M. Allam, M. Anis, M. Elmasry","doi":"10.1109/CICC.2000.852695","DOIUrl":"https://doi.org/10.1109/CICC.2000.852695","url":null,"abstract":"In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 /spl mu/m CMOS technologies.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"32 1","pages":"401-408"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90998667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852652
M. Borgatti, A. Rocchi, Marco Bisio, M. Besana, L. Navoni, P. Rolandi
A system-on-chip prototype implements a full integration of a 64-minute digital voice recorder/player embedding a 4 bit/cell multilevel digital flash memory. A speech coder/decoder (8 to 40 kbps), an MCU and an 8 Mcell/32 Mb multilevel flash memory with fully digital on-chip BIST solution are integrated in a 0.5 /spl mu/m embedded flash technology. The system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The chip counts 13M transistors at 225 mm/sup 2/ area.
{"title":"A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory","authors":"M. Borgatti, A. Rocchi, Marco Bisio, M. Besana, L. Navoni, P. Rolandi","doi":"10.1109/CICC.2000.852652","DOIUrl":"https://doi.org/10.1109/CICC.2000.852652","url":null,"abstract":"A system-on-chip prototype implements a full integration of a 64-minute digital voice recorder/player embedding a 4 bit/cell multilevel digital flash memory. A speech coder/decoder (8 to 40 kbps), an MCU and an 8 Mcell/32 Mb multilevel flash memory with fully digital on-chip BIST solution are integrated in a 0.5 /spl mu/m embedded flash technology. The system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The chip counts 13M transistors at 225 mm/sup 2/ area.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"31 1","pages":"219-222"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89654607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852666
Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba
A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.
{"title":"A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%","authors":"Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba","doi":"10.1109/CICC.2000.852666","DOIUrl":"https://doi.org/10.1109/CICC.2000.852666","url":null,"abstract":"A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"50 1","pages":"279-282"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74937190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852734
F. Svelto, S. Deantoni, R. Castello
A 2 V, 1 mA, 1.8 GHz to 2.45 GHz tuneable LC-tank CMOS VCO is presented. The tank is made of a MOS varactor (worked between accumulation and deep depletion) and a bondwire inductor, realized connecting two pads to a package frame lead, to be compatible with the production environment. This solution enables one to tune all components variations, while achieving the lowest phase noise times current consumption product, reported to date.
{"title":"A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO","authors":"F. Svelto, S. Deantoni, R. Castello","doi":"10.1109/CICC.2000.852734","DOIUrl":"https://doi.org/10.1109/CICC.2000.852734","url":null,"abstract":"A 2 V, 1 mA, 1.8 GHz to 2.45 GHz tuneable LC-tank CMOS VCO is presented. The tank is made of a MOS varactor (worked between accumulation and deep depletion) and a bondwire inductor, realized connecting two pads to a package frame lead, to be compatible with the production environment. This solution enables one to tune all components variations, while achieving the lowest phase noise times current consumption product, reported to date.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"39 1","pages":"577-580"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82087941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852693
P. Andreani, S. Mattisson
An 18/sup th/ (4/sup th/+14/sup th/) order g/sub m/-C IF filter for the Bluetooth short-range radio, implemented in a 0.6 /spl mu/m CMOS process, is presented. The filter bandwidth is 1 MHz, the center frequency f/sub c/ is 3 MHz, the in-band group delay variation is 0.75 /spl mu/s, and the stop-band attenuation at f/sub c//spl plusmn/1 MHz is at least 47 dB. The noise floor is 250 /spl mu/V/sub r.m.s./ and the spurious free dynamic range is at least 58 dB for out-of-band signals, thus exceeding the Bluetooth requirements. Current consumption is 2.4 mA from a 2.5 V power supply.
{"title":"A CMOS g/sub m/-C IF filter for Bluetooth","authors":"P. Andreani, S. Mattisson","doi":"10.1109/CICC.2000.852693","DOIUrl":"https://doi.org/10.1109/CICC.2000.852693","url":null,"abstract":"An 18/sup th/ (4/sup th/+14/sup th/) order g/sub m/-C IF filter for the Bluetooth short-range radio, implemented in a 0.6 /spl mu/m CMOS process, is presented. The filter bandwidth is 1 MHz, the center frequency f/sub c/ is 3 MHz, the in-band group delay variation is 0.75 /spl mu/s, and the stop-band attenuation at f/sub c//spl plusmn/1 MHz is at least 47 dB. The noise floor is 250 /spl mu/V/sub r.m.s./ and the spurious free dynamic range is at least 58 dB for out-of-band signals, thus exceeding the Bluetooth requirements. Current consumption is 2.4 mA from a 2.5 V power supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"187 1","pages":"391-394"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81529144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852726
R. Y. Omaki, Yu Dong, M. H. Miki, M. Furuie, Shohei Yamada, D. Taki, Masaya Tarui, G. Fujita, T. Onoye, I. Shirakawa
The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341 K transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in realtime.
{"title":"VLSI implementation of a realtime wavelet video coder","authors":"R. Y. Omaki, Yu Dong, M. H. Miki, M. Furuie, Shohei Yamada, D. Taki, Masaya Tarui, G. Fujita, T. Onoye, I. Shirakawa","doi":"10.1109/CICC.2000.852726","DOIUrl":"https://doi.org/10.1109/CICC.2000.852726","url":null,"abstract":"The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341 K transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in realtime.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"24 1","pages":"543-546"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82482573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852710
C. Deng, C. Chien
CDMA spread-spectrum systems require PN-acquisition to synchronize the transmitted signal at the receiver. Fast acquisition minimizes the amount of synchronization overhead required in the communication link for maximum system throughput. Yet, the fast acquisition should be done with low energy for portable applications. Conventional acquisition techniques using matched filters or serial correlators alone provide either fast pseudo-noise (PN) acquisition for CDMA or low power dissipation but not both. This paper presents an ASIC which implements a hybrid PN acquisition architecture that achieves both fast acquisition and up to 50% reduction in energy dissipation compared to conventional techniques. This ASIC has been fabricated using 0.5-/spl mu/m CMOS technology with an area of 23 mm. It operates at 20 MHz with a 3.3 V supply and dissipates 50 mW per acquisition, or less than 1.5 mW per 50 byte packet.
CDMA扩频系统需要pn采集来同步接收端发送的信号。快速采集最大限度地减少了通信链路中所需的同步开销，以实现最大的系统吞吐量。然而，对于便携式应用来说，快速采集应该以低能量完成。传统的采集技术使用匹配滤波器或串行相关器单独提供快速伪噪声(PN)采集或低功耗，但不能两者兼得。本文提出了一种实现混合PN采集架构的ASIC，与传统技术相比，该架构实现了快速采集和高达50%的能耗降低。该ASIC采用0.5-/spl μ m CMOS技术制造，面积为23 mm。它的工作频率为20mhz，电源为3.3 V，每次采集功耗为50mw，或每50字节数据包功耗小于1.5 mW。
{"title":"A PN-acquisition ASIC for wireless CDMA systems","authors":"C. Deng, C. Chien","doi":"10.1109/CICC.2000.852710","DOIUrl":"https://doi.org/10.1109/CICC.2000.852710","url":null,"abstract":"CDMA spread-spectrum systems require PN-acquisition to synchronize the transmitted signal at the receiver. Fast acquisition minimizes the amount of synchronization overhead required in the communication link for maximum system throughput. Yet, the fast acquisition should be done with low energy for portable applications. Conventional acquisition techniques using matched filters or serial correlators alone provide either fast pseudo-noise (PN) acquisition for CDMA or low power dissipation but not both. This paper presents an ASIC which implements a hybrid PN acquisition architecture that achieves both fast acquisition and up to 50% reduction in energy dissipation compared to conventional techniques. This ASIC has been fabricated using 0.5-/spl mu/m CMOS technology with an area of 23 mm. It operates at 20 MHz with a 3.3 V supply and dissipates 50 mW per acquisition, or less than 1.5 mW per 50 byte packet.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"11 1","pages":"469-472"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86771100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852641
A. Vouilloz, M. Declercq, C. Dehollain
A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35 /spl mu/m CMOS process is described. The receiver includes a LNA, a super-regenerative oscillator, an envelope detector, AGC circuitry with sample/hold capability and a baseband amplifier. The die-surface is equal to 0.25 mm/sup 2/. An overall noise figure of 14.7 dB is achieved. The power consumption is less than 1.2 mW at V/sub DD/=1.5 V. A 100 kHz saw tooth quench signal has been used to achieve an interferer rejection of -35.9 dB at 500 kHz from the center frequency.
{"title":"A low-power CMOS super-regenerative receiver at 1 GHz","authors":"A. Vouilloz, M. Declercq, C. Dehollain","doi":"10.1109/CICC.2000.852641","DOIUrl":"https://doi.org/10.1109/CICC.2000.852641","url":null,"abstract":"A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35 /spl mu/m CMOS process is described. The receiver includes a LNA, a super-regenerative oscillator, an envelope detector, AGC circuitry with sample/hold capability and a baseband amplifier. The die-surface is equal to 0.25 mm/sup 2/. An overall noise figure of 14.7 dB is achieved. The power consumption is less than 1.2 mW at V/sub DD/=1.5 V. A 100 kHz saw tooth quench signal has been used to achieve an interferer rejection of -35.9 dB at 500 kHz from the center frequency.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"43 1","pages":"167-170"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83686170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852690
S. Anand, B. Razavi
This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.
{"title":"A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology","authors":"S. Anand, B. Razavi","doi":"10.1109/CICC.2000.852690","DOIUrl":"https://doi.org/10.1109/CICC.2000.852690","url":null,"abstract":"This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"77 1","pages":"379-382"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86177402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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