Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852607
C. B. Wang
A 20 bit delta sigma A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply. It provides a 25 kHz data rate for high speed DC measurement while maintaining good performance required by accurate DC measurement such as noise, linearity and drift. The front-end programmable gain amplifier allows the users to optimize their system with different ranges of input level. Offset and finite gain compensation technique is used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta sigma converter section, low frequency error reduction is achieved through chopper stabilization technique. A novel frequency-shaped chopper stabilization scheme is used to alleviate the inter-modulation tone which commonly exists due to the use of fix frequency chopping in delta sigma modulators. This A/D converter achieves 2.8 ppm RMS noise and 12 ppm INL at a gain of one.
{"title":"A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme","authors":"C. B. Wang","doi":"10.1109/CICC.2000.852607","DOIUrl":"https://doi.org/10.1109/CICC.2000.852607","url":null,"abstract":"A 20 bit delta sigma A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply. It provides a 25 kHz data rate for high speed DC measurement while maintaining good performance required by accurate DC measurement such as noise, linearity and drift. The front-end programmable gain amplifier allows the users to optimize their system with different ranges of input level. Offset and finite gain compensation technique is used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta sigma converter section, low frequency error reduction is achieved through chopper stabilization technique. A novel frequency-shaped chopper stabilization scheme is used to alleviate the inter-modulation tone which commonly exists due to the use of fix frequency chopping in delta sigma modulators. This A/D converter achieves 2.8 ppm RMS noise and 12 ppm INL at a gain of one.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"7 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81904134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852735
Hui Wu, A. Hajimiri
A 10 GHz CMOS distributed voltage controlled oscillator (DVCO) is designed in a 0.35 /spl mu/m BiCMOS process technology using only CMOS transistors. The oscillator achieves a tuning range of 12% (9.3 GHz to 10.5 GHz) and a phase noise of -114 dBc/Hz at 1 MHz offset from a carrier frequency of 10.2 GHz. The VCO uses two different simultaneous tuning techniques which allow for a coarse and fine tuning of frequency in a frequency synthesizer. The oscillator provides an output power of -7 dBm without any buffering, drawing 14 mA of DC current from a 2.5 V power supply.
{"title":"A 10 GHz CMOS distributed voltage controlled oscillator","authors":"Hui Wu, A. Hajimiri","doi":"10.1109/CICC.2000.852735","DOIUrl":"https://doi.org/10.1109/CICC.2000.852735","url":null,"abstract":"A 10 GHz CMOS distributed voltage controlled oscillator (DVCO) is designed in a 0.35 /spl mu/m BiCMOS process technology using only CMOS transistors. The oscillator achieves a tuning range of 12% (9.3 GHz to 10.5 GHz) and a phase noise of -114 dBc/Hz at 1 MHz offset from a carrier frequency of 10.2 GHz. The VCO uses two different simultaneous tuning techniques which allow for a coarse and fine tuning of frequency in a frequency synthesizer. The oscillator provides an output power of -7 dBm without any buffering, drawing 14 mA of DC current from a 2.5 V power supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"35 1","pages":"581-584"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74772442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852721
E. Charbon, I. Torunoglu
New design paradigms based on the concept of system-on-chip are gradually replacing printed circuit board centric approaches. This trend is mainly due to two factors: far higher running speeds and greater miniaturization. The new paradigms will accelerate design cycles, which in turn will force designers to reuse existing and acquire new circuits ready to be integrated. Such acceleration will be possible only if highly specialized core authors, integrators, and foundries will be able to efficiently and safely exchange and handle their intellectual property, The field known as intellectual property protection is aimed at limiting all violations to intellectual property rights through appropriate design methodologies, tools, and infringement detection techniques. The paper surveys all published aspects of the intellectual properly protection problem, in the context of concerted VSIA efforts to define new standards and protocols.
{"title":"On intellectual property protection","authors":"E. Charbon, I. Torunoglu","doi":"10.1109/CICC.2000.852721","DOIUrl":"https://doi.org/10.1109/CICC.2000.852721","url":null,"abstract":"New design paradigms based on the concept of system-on-chip are gradually replacing printed circuit board centric approaches. This trend is mainly due to two factors: far higher running speeds and greater miniaturization. The new paradigms will accelerate design cycles, which in turn will force designers to reuse existing and acquire new circuits ready to be integrated. Such acceleration will be possible only if highly specialized core authors, integrators, and foundries will be able to efficiently and safely exchange and handle their intellectual property, The field known as intellectual property protection is aimed at limiting all violations to intellectual property rights through appropriate design methodologies, tools, and infringement detection techniques. The paper surveys all published aspects of the intellectual properly protection problem, in the context of concerted VSIA efforts to define new standards and protocols.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"16 1","pages":"517-523"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74812681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852724
Thomas Roewer, M. Stadler, M. Thalmann, H. Kaeslin, N. Felber, W. Fichtner
We have implemented a SONET/SDH compatible 155 Mbit/s input block using a new paradigm called programmable intellectual property. The module can be reconfigured by downloading new software versions into the IP embedded processor. This concept offers maximum flexibility for both hard- and soft-IP modules.
{"title":"A new paradigm for very flexible SONET/SDH IP-modules","authors":"Thomas Roewer, M. Stadler, M. Thalmann, H. Kaeslin, N. Felber, W. Fichtner","doi":"10.1109/CICC.2000.852724","DOIUrl":"https://doi.org/10.1109/CICC.2000.852724","url":null,"abstract":"We have implemented a SONET/SDH compatible 155 Mbit/s input block using a new paradigm called programmable intellectual property. The module can be reconfigured by downloading new software versions into the IP embedded processor. This concept offers maximum flexibility for both hard- and soft-IP modules.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"46 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80007287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852630
Cristinel Ababei, R. Marculescu, V. Sundarajan
In this paper we present a probabilistic approach for analyzing the dependence of crosstalk effects on input pattern correlations. In particular, we show that the effects of coupling between interconnections, in current VLSI ICs, are strongly dependent on the spatio-temporal correlations at the primary inputs. Consequently, a smaller fraction of the total number of nets poses true crosstalk problems and only that fraction should be considered at lower levels of abstraction. The analysis is carried out at the logic-level of abstraction, which provides efficient CPU run time and memory usage.
{"title":"Probabilistic aspects of crosstalk problems in CMOS ICs","authors":"Cristinel Ababei, R. Marculescu, V. Sundarajan","doi":"10.1109/CICC.2000.852630","DOIUrl":"https://doi.org/10.1109/CICC.2000.852630","url":null,"abstract":"In this paper we present a probabilistic approach for analyzing the dependence of crosstalk effects on input pattern correlations. In particular, we show that the effects of coupling between interconnections, in current VLSI ICs, are strongly dependent on the spatio-temporal correlations at the primary inputs. Consequently, a smaller fraction of the total number of nets poses true crosstalk problems and only that fraction should be considered at lower levels of abstraction. The analysis is carried out at the logic-level of abstraction, which provides efficient CPU run time and memory usage.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"14 1","pages":"117-120"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80380375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852618
T. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi
A new fabrication method for embedded DRAM of 0.18 /spl mu/m generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications.
{"title":"A fabrication method for high performance embedded DRAM of 0.18 /spl mu/m generation and beyond","authors":"T. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi","doi":"10.1109/CICC.2000.852618","DOIUrl":"https://doi.org/10.1109/CICC.2000.852618","url":null,"abstract":"A new fabrication method for embedded DRAM of 0.18 /spl mu/m generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"11 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84308713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852632
P. Buffet, Joseph Natonio, R. Proctor, Yu H. Sun, Gulsun Yasar
Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms.
{"title":"Methodology for I/O cell placement and checking in ASIC designs using area-array power grid","authors":"P. Buffet, Joseph Natonio, R. Proctor, Yu H. Sun, Gulsun Yasar","doi":"10.1109/CICC.2000.852632","DOIUrl":"https://doi.org/10.1109/CICC.2000.852632","url":null,"abstract":"Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"137 1","pages":"125-128"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77224359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852608
M. Dessouky, A. Kaiser
A 1 V, 1 mW, 14 bit delta-sigma modulator in a standard CMOS 0.35-/spl mu/m technology is presented. A modified symmetrical bootstrapped switch is used in order to allow rail-to-rail signal switching. A single-loop third-order topology with an oversampling ratio of 100 achieves a dynamic range of 88 dB, a peak SNR of 87 dB and a peak SNDR of 85 dB in a signal bandwidth of 25 kHz.
{"title":"A 1 V 1 mW digital-audio /spl Delta//spl Sigma/ modulator with 88 dB dynamic range using local switch bootstrapping","authors":"M. Dessouky, A. Kaiser","doi":"10.1109/CICC.2000.852608","DOIUrl":"https://doi.org/10.1109/CICC.2000.852608","url":null,"abstract":"A 1 V, 1 mW, 14 bit delta-sigma modulator in a standard CMOS 0.35-/spl mu/m technology is presented. A modified symmetrical bootstrapped switch is used in order to allow rail-to-rail signal switching. A single-loop third-order topology with an oversampling ratio of 100 achieves a dynamic range of 88 dB, a peak SNR of 87 dB and a peak SNDR of 85 dB in a signal bandwidth of 25 kHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"5 1","pages":"13-16"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76766898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852722
J. Nash, P. Smith
The conversion of existing embedded intellectual property (IP) from one automotive compatible mixed mode technology to another is analyzed with respect to the methods and resources required. Conclusions are drawn about advances required in tools and design processes to better aid this task.
{"title":"An analysis of the design processes required for the technology conversion of SoC intellectual property","authors":"J. Nash, P. Smith","doi":"10.1109/CICC.2000.852722","DOIUrl":"https://doi.org/10.1109/CICC.2000.852722","url":null,"abstract":"The conversion of existing embedded intellectual property (IP) from one automotive compatible mixed mode technology to another is analyzed with respect to the methods and resources required. Conclusions are drawn about advances required in tools and design processes to better aid this task.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"100 1","pages":"525-527"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82799508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852684
W. Winkler, F. Herzel
This paper presents an active substrate noise suppression circuit using a pair of concentric guard rings. The outer guard ring senses the substrate noise, which is inverted and amplified by a SiGe circuit. This on-chip amplifier drives the inner guard ring such that efficient noise cancellation is achieved. A ring oscillator is used to sense the residual substrate noise. The measured noise suppression bandwidth is as high as 400 MHz.
{"title":"Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings","authors":"W. Winkler, F. Herzel","doi":"10.1109/CICC.2000.852684","DOIUrl":"https://doi.org/10.1109/CICC.2000.852684","url":null,"abstract":"This paper presents an active substrate noise suppression circuit using a pair of concentric guard rings. The outer guard ring senses the substrate noise, which is inverted and amplified by a SiGe circuit. This on-chip amplifier drives the inner guard ring such that efficient noise cancellation is achieved. A ring oscillator is used to sense the residual substrate noise. The measured noise suppression bandwidth is as high as 400 MHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"27 1","pages":"357-360"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82823732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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