Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852728
S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung
This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.
本文介绍了一种名为FLOVA (FLOating-Point VLIW Architecture)的VLIW (very long instruction word)几何处理器，它是为加速三维图形的几何阶段而开发的。FLOVA在一个周期内执行4条指令，支持136条指令，其中包括35条SIMD(单指令多数据)指令，以加速几何阶段。描述了在3D图形几何阶段加速转换和照明操作的特殊功能。FLOVA可以在四个时钟周期内计算两个浮点数的功率值，精度损失可以忽略不计，而其他处理器则需要超过150个时钟周期。
{"title":"FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit","authors":"S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung","doi":"10.1109/CICC.2000.852728","DOIUrl":"https://doi.org/10.1109/CICC.2000.852728","url":null,"abstract":"This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"30 1","pages":"551-554"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91087961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852692
J. Lee, C. Tu, Wei-Hong Chen
A fully differential CMOS transconductor with 3 V linear input range is proposed. The Gm value of the transconductor is tunable through a current division scheme. A current mode arithmetic method is used to adaptively bias the transconductor tuning stage. A 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter using this highly linear transconductor achieves a IM3 distortion at 300 kHz of -62 dBc for a 2 Vppd input signal. The filter was fabricated with a double poly triple metal 0.35 /spl mu/m CMOS process and consumes 66 mW.
{"title":"A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSL","authors":"J. Lee, C. Tu, Wei-Hong Chen","doi":"10.1109/CICC.2000.852692","DOIUrl":"https://doi.org/10.1109/CICC.2000.852692","url":null,"abstract":"A fully differential CMOS transconductor with 3 V linear input range is proposed. The Gm value of the transconductor is tunable through a current division scheme. A current mode arithmetic method is used to adaptively bias the transconductor tuning stage. A 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter using this highly linear transconductor achieves a IM3 distortion at 300 kHz of -62 dBc for a 2 Vppd input signal. The filter was fabricated with a double poly triple metal 0.35 /spl mu/m CMOS process and consumes 66 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"46 1","pages":"387-390"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72760942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852664
T. Yamauchi, M. Kinoshita, T. Amano, K. Dosaka, K. Arimoto, H. Ozaki, M. Yamada, T. Yoshihara
This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.
{"title":"Design methodology of the embedded DRAM with the virtual socket architecture","authors":"T. Yamauchi, M. Kinoshita, T. Amano, K. Dosaka, K. Arimoto, H. Ozaki, M. Yamada, T. Yoshihara","doi":"10.1109/CICC.2000.852664","DOIUrl":"https://doi.org/10.1109/CICC.2000.852664","url":null,"abstract":"This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"78 4 1","pages":"271-274"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72666500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852708
Tai-Cheng Lee, B. Razavi
A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers by 50 taps. Designed in a 0.4 /spl mu/m CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3 V supply.
{"title":"A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire","authors":"Tai-Cheng Lee, B. Razavi","doi":"10.1109/CICC.2000.852708","DOIUrl":"https://doi.org/10.1109/CICC.2000.852708","url":null,"abstract":"A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers by 50 taps. Designed in a 0.4 /spl mu/m CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"23 1","pages":"461-464"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76594278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852656
Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang
This paper presents an integrated 8-VSB receiver IC which demodulates and decodes the ATSC-compliant terrestrial RF transmission signal. The design has been accomplished in an ASIC-vendor independent way using only HDL description and synthesis tools. It can receive any IF signal of 5.38 MHz or 44 MHz. The chip has been implemented with equivalent 300 k gates comprising 200 k logic parts and 100 k gate-equivalent memory parts in an area of 8.0/spl times/7.7 mm/sup 2/. The chip is operative at 50 MHz and consumes approximately 3.2 W under 5 volts in a commercial operating condition.
{"title":"A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV]","authors":"Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang","doi":"10.1109/CICC.2000.852656","DOIUrl":"https://doi.org/10.1109/CICC.2000.852656","url":null,"abstract":"This paper presents an integrated 8-VSB receiver IC which demodulates and decodes the ATSC-compliant terrestrial RF transmission signal. The design has been accomplished in an ASIC-vendor independent way using only HDL description and synthesis tools. It can receive any IF signal of 5.38 MHz or 44 MHz. The chip has been implemented with equivalent 300 k gates comprising 200 k logic parts and 100 k gate-equivalent memory parts in an area of 8.0/spl times/7.7 mm/sup 2/. The chip is operative at 50 MHz and consumes approximately 3.2 W under 5 volts in a commercial operating condition.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"37 1","pages":"235-238"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87064634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852677
R. Cappelletti, A. Baschirotto
A versatile low-power half-duplex FSK transceiver for power line communication network applications is presented. The proposed power-line modem (PLM) satisfies the requirement of several protocols for both power-line communications and home automation applications. The device operation is fully controlled and programmed through an internal 24 bit register. It operates from a single 9 V supply (5 V is possible if no power delivery is required). During transmission, the PLM is able to deliver 1 W on 16 /spl Omega/, while during reception if dissipates only 3.5 mA. The PLM is realized in a 0.6 /spl mu/m BCD technology.
{"title":"A versatile low-power power line FSK transceiver","authors":"R. Cappelletti, A. Baschirotto","doi":"10.1109/CICC.2000.852677","DOIUrl":"https://doi.org/10.1109/CICC.2000.852677","url":null,"abstract":"A versatile low-power half-duplex FSK transceiver for power line communication network applications is presented. The proposed power-line modem (PLM) satisfies the requirement of several protocols for both power-line communications and home automation applications. The device operation is fully controlled and programmed through an internal 24 bit register. It operates from a single 9 V supply (5 V is possible if no power delivery is required). During transmission, the PLM is able to deliver 1 W on 16 /spl Omega/, while during reception if dissipates only 3.5 mA. The PLM is realized in a 0.6 /spl mu/m BCD technology.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"98 1","pages":"323-326"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83601014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852616
T. Ning
The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz. However realization of this CMOS technology is far from certain due to the many technical difficulties that must be overcome. In the next few years, while the application of CMOS to RF will grow rapidly, performance of digital CMOS will saturate. While development towards 25-nm channel length will continue, CMOS development will also be focused on opportunities beyond scaling the bulk device.
{"title":"CMOS in the new millennium","authors":"T. Ning","doi":"10.1109/CICC.2000.852616","DOIUrl":"https://doi.org/10.1109/CICC.2000.852616","url":null,"abstract":"The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz. However realization of this CMOS technology is far from certain due to the many technical difficulties that must be overcome. In the next few years, while the application of CMOS to RF will grow rapidly, performance of digital CMOS will saturate. While development towards 25-nm channel length will continue, CMOS development will also be focused on opportunities beyond scaling the bulk device.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"75 1","pages":"49-56"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86354273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852668
R. McPartland, D. Loeper, F. Higgins, Raj Singh, G. MacDonald, G. Komoriya, S. Aymeloglu, M. DePaolis, C. Leung
This paper describes the use of low cost, flash EEPROM switches to control redundancy in SRAM embedded memories. Flash cell design, operation and process technology are described. A 768K-bit embedded SRAM memory with flash controlled column redundancy and built in self-repair is presented.
{"title":"SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy","authors":"R. McPartland, D. Loeper, F. Higgins, Raj Singh, G. MacDonald, G. Komoriya, S. Aymeloglu, M. DePaolis, C. Leung","doi":"10.1109/CICC.2000.852668","DOIUrl":"https://doi.org/10.1109/CICC.2000.852668","url":null,"abstract":"This paper describes the use of low cost, flash EEPROM switches to control redundancy in SRAM embedded memories. Flash cell design, operation and process technology are described. A 768K-bit embedded SRAM memory with flash controlled column redundancy and built in self-repair is presented.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"156 1","pages":"287-289"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86321630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852636
Sammy Cheung, Kar Keng Chua, B. Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, C. Sung, Kim Pin Tan, Yu Fong Tan, C. K. Wong
A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.
讨论了一种用于高性能系统集成的百万门可编程逻辑器件(PLD)。APEX 20K1000E采用0.18 /spl mu/m CMOS工艺制造。该芯片支持多种I/O标准，采用集成的LVDS (low voltage differential signaling)接口时，数据带宽可达622 Mbps。多个片上锁相环(PLL)提高性能并提供时钟频率合成。嵌入式内容可寻址内存(CAM)增强了快速搜索应用程序的性能。
{"title":"A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM","authors":"Sammy Cheung, Kar Keng Chua, B. Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, C. Sung, Kim Pin Tan, Yu Fong Tan, C. K. Wong","doi":"10.1109/CICC.2000.852636","DOIUrl":"https://doi.org/10.1109/CICC.2000.852636","url":null,"abstract":"A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"109 1","pages":"143-146"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79195344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-21DOI: 10.1109/CICC.2000.852634
A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian
The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.
{"title":"Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture","authors":"A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian","doi":"10.1109/CICC.2000.852634","DOIUrl":"https://doi.org/10.1109/CICC.2000.852634","url":null,"abstract":"The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"24 1","pages":"135-138"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84188183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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