Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012825
P. Coussy, A. Baganne, E. Martin
Successful integration of IP/VC blocks requires a set of views that provides the appropriate information for each IP block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a system-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-Socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed bus-functional model of the IP core towards cosimulation.
{"title":"A design methodology for integrating IP into SOC systems","authors":"P. Coussy, A. Baganne, E. Martin","doi":"10.1109/CICC.2002.1012825","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012825","url":null,"abstract":"Successful integration of IP/VC blocks requires a set of views that provides the appropriate information for each IP block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a system-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-Socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed bus-functional model of the IP core towards cosimulation.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133947423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012855
H. Igura, M. Hirata, J. Yamada, M. Yamashina, S. Ono
This paper presents the architecture of a demodulator developed for W-CDMA digital baseband processing. The demodulator features micro-DSPs specially designed for it and a variety of power-lowering and area-saving techniques such as detailed clock control, reduction of unnecessary signal transition and data compression. These features give the demodulator much lower power consumption and smaller size than a conventional one.
{"title":"A low-power W-CDMA demodulator using specially-designed micro-DSPs","authors":"H. Igura, M. Hirata, J. Yamada, M. Yamashina, S. Ono","doi":"10.1109/CICC.2002.1012855","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012855","url":null,"abstract":"This paper presents the architecture of a demodulator developed for W-CDMA digital baseband processing. The demodulator features micro-DSPs specially designed for it and a variety of power-lowering and area-saving techniques such as detailed clock control, reduction of unnecessary signal transition and data compression. These features give the demodulator much lower power consumption and smaller size than a conventional one.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127424308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012774
Jian-Hsing Lee, Yi-Hsun Wu, K. Peng, R. Chang, Talee Yu, T. Ong
Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, and a very low capacitance (/spl sim/50 fF) ESD protection (LCESD) device are developed successfully for output pad and input pad, respectively. In addition, a protection scheme, combining the power protection device and a n+ guard-ring, is proposed and proven to be capable of protecting four directions ESD zapping and without increasing the LCESD device capacitance.
{"title":"The embedded SCR NMOS and low capacitance ESD protection device","authors":"Jian-Hsing Lee, Yi-Hsun Wu, K. Peng, R. Chang, Talee Yu, T. Ong","doi":"10.1109/CICC.2002.1012774","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012774","url":null,"abstract":"Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, and a very low capacitance (/spl sim/50 fF) ESD protection (LCESD) device are developed successfully for output pad and input pad, respectively. In addition, a protection scheme, combining the power protection device and a n+ guard-ring, is proposed and proven to be capable of protecting four directions ESD zapping and without increasing the LCESD device capacitance.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133727184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012784
Zhan Yu, Meng-Lin Yu, Kamran Azadet, A. Willson
We describe the IC implementation and testing of a low-power adaptive FIR filter. A new technique is used in its implementation, one that can be employed in other digital signal processing applications where input signals have large dynamic ranges. We propose the use of a reduced 2's complement signal representation to conditionally disable the internal signal transitions in the most-significant-bits of a data path. The key idea is to generate the signal representation dynamically according to the signal magnitude. The proposed technique retains all of the easy-to-implement properties of the widely-used 2's complement number representation and is particularly suitable for the implementation of arithmetic operations. Over a 32% power savings has been achieved in our adaptive filter application.
{"title":"A low power adaptive filter using dynamic reduced 2's-complement representation","authors":"Zhan Yu, Meng-Lin Yu, Kamran Azadet, A. Willson","doi":"10.1109/CICC.2002.1012784","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012784","url":null,"abstract":"We describe the IC implementation and testing of a low-power adaptive FIR filter. A new technique is used in its implementation, one that can be employed in other digital signal processing applications where input signals have large dynamic ranges. We propose the use of a reduced 2's complement signal representation to conditionally disable the internal signal transitions in the most-significant-bits of a data path. The key idea is to generate the signal representation dynamically according to the signal magnitude. The proposed technique retains all of the easy-to-implement properties of the widely-used 2's complement number representation and is particularly suitable for the implementation of arithmetic operations. Over a 32% power savings has been achieved in our adaptive filter application.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115570145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012804
R. Gharpurey, Naveen K. Yanduru, F. Dantoni, P. Litmanen, Guglielmo Sirna, Terry Mayhugh, Charles Lin, I. Deng, P. Fontaine, Fang Lin
A highly integrated direct-conversion receiver that satisfies requirements of the third generation Wideband Code Division Multiple Access (WCDMA) mobile phone standard is described. The receiver IC includes the front-end low-noise amplifier, down-conversion mixers, channel select filters, baseband variable gain amplifiers, and the entire frequency synthesizer, including the voltage controlled oscillator, buffers and phase-locked loop.
{"title":"A direct conversion receiver for the 3G WCDMA standard","authors":"R. Gharpurey, Naveen K. Yanduru, F. Dantoni, P. Litmanen, Guglielmo Sirna, Terry Mayhugh, Charles Lin, I. Deng, P. Fontaine, Fang Lin","doi":"10.1109/CICC.2002.1012804","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012804","url":null,"abstract":"A highly integrated direct-conversion receiver that satisfies requirements of the third generation Wideband Code Division Multiple Access (WCDMA) mobile phone standard is described. The receiver IC includes the front-end low-noise amplifier, down-conversion mixers, channel select filters, baseband variable gain amplifiers, and the entire frequency synthesizer, including the voltage controlled oscillator, buffers and phase-locked loop.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124365088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012801
F. Rotella, Jeff Zachan
Pattern ground shield inductors have been shown to improve the performance of on-chip inductors by reducing the impact of the resistive substrate. This paper optimizes these inductors by separating the capacitive component and inductive component. The trade-offs are characterized and modeled. An optimized design is developed to improve the performance of a voltage controlled oscillator using a switched capacitor architecture.
{"title":"Modeling and optimization of inductors with patterned ground shields for a high performance fully integrated switched tuning VCO","authors":"F. Rotella, Jeff Zachan","doi":"10.1109/CICC.2002.1012801","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012801","url":null,"abstract":"Pattern ground shield inductors have been shown to improve the performance of on-chip inductors by reducing the impact of the resistive substrate. This paper optimizes these inductors by separating the capacitive component and inductive component. The trade-offs are characterized and modeled. An optimized design is developed to improve the performance of a voltage controlled oscillator using a switched capacitor architecture.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012762
Sang-Soo Lee
System optimization of the Analog Front End (AFE) and hybrid line interface is a key contributor in achieving high data rate and long reach for Asymmetric Digital Subscriber Line (ADSL) modems. Following a brief review of the ADSL system, the basic building blocks in an AFE, analog line interface, and hybrid matching issues are introduced. Integration trends of a single-channel AFE and circuit design challenges for multi-channel AFE are then presented. Line driver technologies and line receiver design issues are discussed with emphasis on the tradeoff between noise and linearity. Finally, design challenges for a highly integrated ADSL modem chipset with minimal external components are addressed.
{"title":"Integration and system design trends of ADSL analog front ends and hybrid line interfaces","authors":"Sang-Soo Lee","doi":"10.1109/CICC.2002.1012762","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012762","url":null,"abstract":"System optimization of the Analog Front End (AFE) and hybrid line interface is a key contributor in achieving high data rate and long reach for Asymmetric Digital Subscriber Line (ADSL) modems. Following a brief review of the ADSL system, the basic building blocks in an AFE, analog line interface, and hybrid matching issues are introduced. Integration trends of a single-channel AFE and circuit design challenges for multi-channel AFE are then presented. Line driver technologies and line receiver design issues are discussed with emphasis on the tradeoff between noise and linearity. Finally, design challenges for a highly integrated ADSL modem chipset with minimal external components are addressed.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012895
P. Heydari, S. Abbaspour, Massoud Pedram
In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay constraint is proposed. The energy formulations are obtained by using approximated expressions for the driving-point impedance of lossy coupled transmission lines which itself is derived by solving Telegrapher's equations. A comprehensive analysis of energy is performed for a wide variety range of the gate. aspect-ratios of the driving transistors. To accomplish this task, two stable circuits that are capable of modeling the transmission line for a broad range of frequencies are synthesized. Experimental results show that the energy calculated using these equivalent circuits are almost equal to the one calculated by solving the more complicated transmission line equations directly. Next, using a new performance metric the effect of geometrical variations of the interconnect and the driver on the energy optimization under the delay constraint is studied. The experimental results verify the accuracy of our models.
{"title":"A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters","authors":"P. Heydari, S. Abbaspour, Massoud Pedram","doi":"10.1109/CICC.2002.1012895","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012895","url":null,"abstract":"In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay constraint is proposed. The energy formulations are obtained by using approximated expressions for the driving-point impedance of lossy coupled transmission lines which itself is derived by solving Telegrapher's equations. A comprehensive analysis of energy is performed for a wide variety range of the gate. aspect-ratios of the driving transistors. To accomplish this task, two stable circuits that are capable of modeling the transmission line for a broad range of frequencies are synthesized. Experimental results show that the energy calculated using these equivalent circuits are almost equal to the one calculated by solving the more complicated transmission line equations directly. Next, using a new performance metric the effect of geometrical variations of the interconnect and the driver on the energy optimization under the delay constraint is studied. The experimental results verify the accuracy of our models.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132182036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012842
Wei-Zen Chen, Chao-Hsin Lu
A 3 V, single chip optical receiver analog front-end capable of operating at 2.5 Gbit/s is fabricated in a 0.35 /spl mu/m CMOS technology. The IC contains a transimpedance amplifier (TIA) with 54.5 dB/spl Omega/ conversion gain, f/sub -3 dB/ of 2.5 GHz, and a limiting amplifier with a conversion gain of 42 dB, f/sub -3 dB/ of 2.3 GHz. The TIA is DC coupled to the limiting amplifier. The measured eye diagram meets the OC-48 transition mask. Input referred noise current is about 800 nA.
{"title":"A 2.5 Gbps CMOS optical receiver analog front-end","authors":"Wei-Zen Chen, Chao-Hsin Lu","doi":"10.1109/CICC.2002.1012842","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012842","url":null,"abstract":"A 3 V, single chip optical receiver analog front-end capable of operating at 2.5 Gbit/s is fabricated in a 0.35 /spl mu/m CMOS technology. The IC contains a transimpedance amplifier (TIA) with 54.5 dB/spl Omega/ conversion gain, f/sub -3 dB/ of 2.5 GHz, and a limiting amplifier with a conversion gain of 42 dB, f/sub -3 dB/ of 2.3 GHz. The TIA is DC coupled to the limiting amplifier. The measured eye diagram meets the OC-48 transition mask. Input referred noise current is about 800 nA.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012856
A. Eltawil, B. Daneshrad
In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). The ROM size is consistently less than 1 Kbit for SFDR values up to 85 dBc.
{"title":"Piece-wise parabolic interpolation for direct digital frequency synthesis","authors":"A. Eltawil, B. Daneshrad","doi":"10.1109/CICC.2002.1012856","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012856","url":null,"abstract":"In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). The ROM size is consistently less than 1 Kbit for SFDR values up to 85 dBc.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121043746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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