Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012808
T. Itakura, H. Minamizaki, Tetsuya Saito, Tadashi Kuroda
A 402-output TFT-LCD driver with a power-controlling function by selecting a number of colors to be displayed is described. Power-controlling is realized by turning on and off reference voltage buffers used in DACs to convert RGB digital signals. The buffers must drive 1 to 402 capacitive loads. A phase compensation using a zero formed with the capacitive loads is proposed for the buffers. The analog section consumes 529 /spl mu/A, 182 /spl mu/A, 112 /spl mu/A for 262,144 colors, 4,096 colors, 512 colors, respectively.
{"title":"A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors","authors":"T. Itakura, H. Minamizaki, Tetsuya Saito, Tadashi Kuroda","doi":"10.1109/CICC.2002.1012808","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012808","url":null,"abstract":"A 402-output TFT-LCD driver with a power-controlling function by selecting a number of colors to be displayed is described. Power-controlling is realized by turning on and off reference voltage buffers used in DACs to convert RGB digital signals. The buffers must drive 1 to 402 capacitive loads. A phase compensation using a zero formed with the capacitive loads is proposed for the buffers. The analog section consumes 529 /spl mu/A, 182 /spl mu/A, 112 /spl mu/A for 262,144 colors, 4,096 colors, 512 colors, respectively.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012853
T. Wolf, D. Hocevar, A. Gatherer, Patrick Geremia, Armelle Laine
A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is based upon a partitioning of the workload between a DSP core and two flexible forward error correction coprocessors. This allows the DSP to handle a larger number of channels and/or to incorporate advanced algorithms.
1.2 V 600 MHz 4800 MIPS DSP是3G基站基带处理的解决方案。它基于一个DSP核心和两个灵活的前向纠错协处理器之间的工作负载划分。这允许DSP处理更多的通道和/或合并先进的算法。
{"title":"600 MHz DSP for baseband processing in 3G base stations","authors":"T. Wolf, D. Hocevar, A. Gatherer, Patrick Geremia, Armelle Laine","doi":"10.1109/CICC.2002.1012853","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012853","url":null,"abstract":"A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is based upon a partitioning of the workload between a DSP core and two flexible forward error correction coprocessors. This allows the DSP to handle a larger number of channels and/or to incorporate advanced algorithms.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114405789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012800
Yu Cao, R. Groves, N. Zamdmer, J. Plouchart, R. Wachnik, Xuejue Huang, T. King, C. Hu
A wide-band, physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Using frequency-independent RLC elements, it accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. This new model is fully compatible with both AC and transient analysis. Verification with measurement data demonstrates excellent scalability for a wide range of inductor configurations.
{"title":"Frequency-independent equivalent circuit model for on-chip spiral inductors","authors":"Yu Cao, R. Groves, N. Zamdmer, J. Plouchart, R. Wachnik, Xuejue Huang, T. King, C. Hu","doi":"10.1109/CICC.2002.1012800","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012800","url":null,"abstract":"A wide-band, physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Using frequency-independent RLC elements, it accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. This new model is fully compatible with both AC and transient analysis. Verification with measurement data demonstrates excellent scalability for a wide range of inductor configurations.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012837
M. Murakawa, T. Adachi, Yoshihiro Niino, Y. Kasai, E. Takahashi, K. Takasuka, T. Higuchi
We have developed an LSI for Gm-C IF filters, attaining (1) a 63% reduction in filter area, (2) a 38% reduction in power dissipation, compared to existing commercial products, and (3) a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm; an efficient AI technique for difficult optimization problems.
{"title":"An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions","authors":"M. Murakawa, T. Adachi, Yoshihiro Niino, Y. Kasai, E. Takahashi, K. Takasuka, T. Higuchi","doi":"10.1109/CICC.2002.1012837","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012837","url":null,"abstract":"We have developed an LSI for Gm-C IF filters, attaining (1) a 63% reduction in filter area, (2) a 38% reduction in power dissipation, compared to existing commercial products, and (3) a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm; an efficient AI technique for difficult optimization problems.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124779939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012840
T. Yoshimura, K. Ueda, Jun Takasoh, Yoshiki Wada, T. Oka, H. Kondoh, Osamu Chiba, Yoshihumi Azekawa, M. Ishiwaki
In this paper, we present a 10Gbase Ethernet Transceiver that is suitable for the 10 Gbit Ethernet applications. The 10Gbase Ethernet transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logic, is fabricated in a 0.18 /spl mu/m SOI/CMOS process and dissipates about 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of an advanced CMOS process, this 10GE transceiver realizes the low power, low cost and compact solutions for the exponential need of broadband network applications.
{"title":"A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 /spl mu/m SOI/CMOS technology","authors":"T. Yoshimura, K. Ueda, Jun Takasoh, Yoshiki Wada, T. Oka, H. Kondoh, Osamu Chiba, Yoshihumi Azekawa, M. Ishiwaki","doi":"10.1109/CICC.2002.1012840","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012840","url":null,"abstract":"In this paper, we present a 10Gbase Ethernet Transceiver that is suitable for the 10 Gbit Ethernet applications. The 10Gbase Ethernet transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logic, is fabricated in a 0.18 /spl mu/m SOI/CMOS process and dissipates about 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of an advanced CMOS process, this 10GE transceiver realizes the low power, low cost and compact solutions for the exponential need of broadband network applications.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012807
Mostafa A. I. Elmala, S. Embabi
This paper presents a modified image-reject Weaver architecture. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The design was fabricated in a 0.35 /spl mu/m CMOS process and dissipates 160 mW from a 3 V supply during on-line calibration.
{"title":"A self-calibration technique for mismatches in image-reject receivers","authors":"Mostafa A. I. Elmala, S. Embabi","doi":"10.1109/CICC.2002.1012807","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012807","url":null,"abstract":"This paper presents a modified image-reject Weaver architecture. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The design was fabricated in a 0.35 /spl mu/m CMOS process and dissipates 160 mW from a 3 V supply during on-line calibration.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122382625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012787
K. Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada
This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 /spl mu/m CMOS technology.
{"title":"Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems","authors":"K. Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada","doi":"10.1109/CICC.2002.1012787","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012787","url":null,"abstract":"This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 /spl mu/m CMOS technology.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012775
P. Fazan, S. Okhonin, M. Nagoga, J. Sallese
A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.
{"title":"A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs","authors":"P. Fazan, S. Okhonin, M. Nagoga, J. Sallese","doi":"10.1109/CICC.2002.1012775","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012775","url":null,"abstract":"A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012782
M. Tokumasu, H. Fujii, M. Ohta, T. Fuse, A. Kameyama
A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.
{"title":"A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)","authors":"M. Tokumasu, H. Fujii, M. Ohta, T. Fuse, A. Kameyama","doi":"10.1109/CICC.2002.1012782","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012782","url":null,"abstract":"A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012810
Sung-Hyun Yang, Kyoung-Rok Cho
In this paper, we propose a new image pixel structure for high dynamic range operation, which is based on a multiple sampling scheme and conditional reset circuits. To expand the dynamic range of the sensor, the output of the pixel is sampled multiple times in an integration time. In each sampling, the output of the pixel is compared with a reference voltage, and the result of this comparison activates the conditional reset circuit. The times of conditional reset during the integration contribute to the increase of the dynamic range of the sensor. Dynamic range can be increased to N, where N is the sampling times in an integration time. The test chip was fabricated with a 0.65-/spl mu/m CMOS technology (2-P, 2-M).
{"title":"High dynamic range CMOS image sensor with conditional reset","authors":"Sung-Hyun Yang, Kyoung-Rok Cho","doi":"10.1109/CICC.2002.1012810","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012810","url":null,"abstract":"In this paper, we propose a new image pixel structure for high dynamic range operation, which is based on a multiple sampling scheme and conditional reset circuits. To expand the dynamic range of the sensor, the output of the pixel is sampled multiple times in an integration time. In each sampling, the output of the pixel is compared with a reference voltage, and the result of this comparison activates the conditional reset circuit. The times of conditional reset during the integration contribute to the increase of the dynamic range of the sensor. Dynamic range can be increased to N, where N is the sampling times in an integration time. The test chip was fabricated with a 0.65-/spl mu/m CMOS technology (2-P, 2-M).","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133247807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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