Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012897
Kazutoshi Kobayashi, Junji Yamaguchi, H. Onodera
This paper describes measurement results of on-chip IR-drop. An IR-drop measurement circuit is implemented in an LSI. It can sense the voltage drop of a power node to alter a reference voltage and clock timing. A measured waveform can be obtained automatically by using the Shmoo plot functionality of an LSI tester. Measuring two different nodes along a VDD line, differential IR-drop waveforms can be successfully obtained.
{"title":"Measurement results of on-chip IR-drop","authors":"Kazutoshi Kobayashi, Junji Yamaguchi, H. Onodera","doi":"10.1109/CICC.2002.1012897","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012897","url":null,"abstract":"This paper describes measurement results of on-chip IR-drop. An IR-drop measurement circuit is implemented in an LSI. It can sense the voltage drop of a power node to alter a reference voltage and clock timing. A measured waveform can be obtained automatically by using the Shmoo plot functionality of an LSI tester. Measuring two different nodes along a VDD line, differential IR-drop waveforms can be successfully obtained.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131951127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012798
R. Kraus, G. Knoblinger
This paper presents a compact model considering the high-frequency and noise effects at the gate of MOS transistors which are caused by the channel resistance in series to the gate capacitance. The real part of input impedance, nonquasistatic charge variations and induced gate noise with correlation to the drain noise are the results. A model equation of the induced gate noise is developed for MOSFETs with very short channel lengths. Comparisons with measurements verify the accuracy of the model and its validity for short and long channel transistors.
{"title":"Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETs","authors":"R. Kraus, G. Knoblinger","doi":"10.1109/CICC.2002.1012798","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012798","url":null,"abstract":"This paper presents a compact model considering the high-frequency and noise effects at the gate of MOS transistors which are caused by the channel resistance in series to the gate capacitance. The real part of input impedance, nonquasistatic charge variations and induced gate noise with correlation to the drain noise are the results. A model equation of the induced gate noise is developed for MOSFETs with very short channel lengths. Comparisons with measurements verify the accuracy of the model and its validity for short and long channel transistors.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"103 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132066626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012779
L. Engh, A. Kordesch, C. Mai-Liu
The presented multi-level storage memory system uses a self-adaptive method that improves the cell model with each successive program cycle, and accommodates cell variations and noise. An accuracy of 5 mV is achieved within eight cycles, which total 125 /spl mu/s. Algorithm control circuits occupy 1 mm/sup 2/ of area in a 0.5 /spl mu/m SSI FLASH process.
{"title":"A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH","authors":"L. Engh, A. Kordesch, C. Mai-Liu","doi":"10.1109/CICC.2002.1012779","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012779","url":null,"abstract":"The presented multi-level storage memory system uses a self-adaptive method that improves the cell model with each successive program cycle, and accommodates cell variations and noise. An accuracy of 5 mV is achieved within eight cycles, which total 125 /spl mu/s. Algorithm control circuits occupy 1 mm/sup 2/ of area in a 0.5 /spl mu/m SSI FLASH process.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012814
C. DeVries, R. Mason
A Q-enhanced filter is presented which operates at a high Q and employs sub-sampling and direct digital tuning. The filter is suitable as an IF filter in applications such as Bluetooth or GPS. The filter operates from 1.2V - 1.8V and consumes 1.08 mW at 500MHz with a SFDR of 37 dB and a Q of 650, at 1.5V.
{"title":"A 0.18/spl mu/m CMOS, high Q-enhanced bandpass filter with direct digital tuning","authors":"C. DeVries, R. Mason","doi":"10.1109/CICC.2002.1012814","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012814","url":null,"abstract":"A Q-enhanced filter is presented which operates at a high Q and employs sub-sampling and direct digital tuning. The filter is suitable as an IF filter in applications such as Bluetooth or GPS. The filter operates from 1.2V - 1.8V and consumes 1.08 mW at 500MHz with a SFDR of 37 dB and a Q of 650, at 1.5V.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128318582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012806
W. Sheng, B. Xia, A. Emira, Chunyu Xin, S. T. Moon, A. Valero-López, E. Sánchez-Sinencio
A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.
{"title":"A monolithic CMOS low-IF Bluetooth receiver","authors":"W. Sheng, B. Xia, A. Emira, Chunyu Xin, S. T. Moon, A. Valero-López, E. Sánchez-Sinencio","doi":"10.1109/CICC.2002.1012806","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012806","url":null,"abstract":"A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012803
P. Vancorenland, P. Coppejans, W. D. Cock, M. Steyaert
A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.
{"title":"A quadrature direct digital downconverter","authors":"P. Vancorenland, P. Coppejans, W. D. Cock, M. Steyaert","doi":"10.1109/CICC.2002.1012803","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012803","url":null,"abstract":"A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133843315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012815
Fikret Duelgel, E. Sánchez-Sinencio, J. Silva-Martínez
A 2.1GHz, 1.3V, 5mW, fully integrated Q enhancement LC bandpass biquad programmable in peak gain, Q and f/sub o/ is implemented in 0.35/spl mu/m standard CMOS. The Q tuning is through an adjustable negative conductance generator. Measured frequency tuning (through varactors) is 13% around 2.1GHz. The filter sinks 4mA from 1.3V providing a Q of 40 at 2.19GHz with 1dB compression DR of 38dB and SFDR of 33dB. The silicon area is 0.1mm/sup 2/.
{"title":"A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35/spl mu/m CMOS","authors":"Fikret Duelgel, E. Sánchez-Sinencio, J. Silva-Martínez","doi":"10.1109/CICC.2002.1012815","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012815","url":null,"abstract":"A 2.1GHz, 1.3V, 5mW, fully integrated Q enhancement LC bandpass biquad programmable in peak gain, Q and f/sub o/ is implemented in 0.35/spl mu/m standard CMOS. The Q tuning is through an adjustable negative conductance generator. Measured frequency tuning (through varactors) is 13% around 2.1GHz. The filter sinks 4mA from 1.3V providing a Q of 40 at 2.19GHz with 1dB compression DR of 38dB and SFDR of 33dB. The silicon area is 0.1mm/sup 2/.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012864
C. Heng, B. Song
A synthesizer in 0.6 /spl mu/m CMOS with an on-chip multiphase VCO exhibits no spurs resulting from interpolated phase errors. The proposed architecture randomizes phase errors of the multi-phase VCO to eliminate spurious tones generated by phase mismatch. Phase noise measured at 1.715 GHz is lower than -80 dBc within 20 kHz loop bandwidth and -118 dBc at 1 MHz offset with fractional spur below -70 dBc. The chip consumes 140 mW at 3.3 V and occupies 3.7 mm/spl times/4.6 mm.
{"title":"A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO","authors":"C. Heng, B. Song","doi":"10.1109/CICC.2002.1012864","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012864","url":null,"abstract":"A synthesizer in 0.6 /spl mu/m CMOS with an on-chip multiphase VCO exhibits no spurs resulting from interpolated phase errors. The proposed architecture randomizes phase errors of the multi-phase VCO to eliminate spurious tones generated by phase mismatch. Phase noise measured at 1.715 GHz is lower than -80 dBc within 20 kHz loop bandwidth and -118 dBc at 1 MHz offset with fractional spur below -70 dBc. The chip consumes 140 mW at 3.3 V and occupies 3.7 mm/spl times/4.6 mm.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122921767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012781
R. Krishnamurthy, A. Alvandpour, V. De, S. Borkar
CMOS technology scaling is becoming difficult beyond 70 nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.
{"title":"High-performance and low-power challenges for sub-70 nm microprocessor circuits","authors":"R. Krishnamurthy, A. Alvandpour, V. De, S. Borkar","doi":"10.1109/CICC.2002.1012781","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012781","url":null,"abstract":"CMOS technology scaling is becoming difficult beyond 70 nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012871
J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert, G. Gielen
A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 /spl mu/m CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.
介绍了一种8位200MS/s 4-2插值A/D转换器。为了提高系统的动态性能，设计了一种新的输入级。使用平均技术可以增强静态性能。该芯片采用标准的0.35 /spl μ m CMOS工艺制造。INL/DNL为0.95/0.8 LSB。在低频时获得了44.3 dB的信噪比:对于30 MHz的输入信号，测量到的信噪比为43 dB。
{"title":"A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter","authors":"J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert, G. Gielen","doi":"10.1109/CICC.2002.1012871","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012871","url":null,"abstract":"A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 /spl mu/m CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124915285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：