Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012777
J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo, S. Kawashima
A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.
{"title":"A 16 kb 1T1C FeRAM test chip using current-based reference scheme","authors":"J. Siu, Y. Eslami, A. Sheikholeslami, P. Gulak, T. Endo, S. Kawashima","doi":"10.1109/CICC.2002.1012777","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012777","url":null,"abstract":"A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128646101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012835
J. Yan, R. Geiger
A fully differential CMOS operational amplifier using a negative conductance gain enhancement technique is presented. The amplifier was fabricated in an AMI 0.5 /spl mu/m CMOS process with an active area of 0.17 mm/sup 2/. With a 3 V supply, a DC gain of more than 80 dB was measured. The gain exceeded 60 dB for a 240 mV output swing.
{"title":"A high gain CMOS operational amplifier with negative conductance gain enhancement","authors":"J. Yan, R. Geiger","doi":"10.1109/CICC.2002.1012835","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012835","url":null,"abstract":"A fully differential CMOS operational amplifier using a negative conductance gain enhancement technique is presented. The amplifier was fabricated in an AMI 0.5 /spl mu/m CMOS process with an active area of 0.17 mm/sup 2/. With a 3 V supply, a DC gain of more than 80 dB was measured. The gain exceeded 60 dB for a 240 mV output swing.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134042368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012783
S. Mick, John M. Wilson, P. Franzon
AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.
{"title":"4 Gbps high-density AC coupled interconnection","authors":"S. Mick, John M. Wilson, P. Franzon","doi":"10.1109/CICC.2002.1012783","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012783","url":null,"abstract":"AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123818739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012887
D. Ozis, T. Fiez, K. Mayaram
An accurate substrate noise coupling macromodel for heavily doped CMOS processes is presented. The model is based on Z parameters that are scalable with contact separation and size. Extensive experimental validations of the model have demonstrated that the modeled Z parameters are most often accurate to within 2-8%.
{"title":"A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes","authors":"D. Ozis, T. Fiez, K. Mayaram","doi":"10.1109/CICC.2002.1012887","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012887","url":null,"abstract":"An accurate substrate noise coupling macromodel for heavily doped CMOS processes is presented. The model is based on Z parameters that are scalable with contact separation and size. Extensive experimental validations of the model have demonstrated that the modeled Z parameters are most often accurate to within 2-8%.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124713772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012765
M. Mar, B. Sullam, E. Blom
An architecture for one of the first mixed-signal field-programmable system-on-a-chip (FPSOC) is presented. The FPSOC integrates a 24-MHz 8-bit microcontroller, flash memory, SRAM, programmable analog and digital blocks, and on-chip clock generation. Programmable interconnect has been designed to allow analog and digital blocks to be combined to form a wide variety of functional modules.
{"title":"An architecture for a programmable mixed-signal device","authors":"M. Mar, B. Sullam, E. Blom","doi":"10.1109/CICC.2002.1012765","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012765","url":null,"abstract":"An architecture for one of the first mixed-signal field-programmable system-on-a-chip (FPSOC) is presented. The FPSOC integrates a 24-MHz 8-bit microcontroller, flash memory, SRAM, programmable analog and digital blocks, and on-chip clock generation. Programmable interconnect has been designed to allow analog and digital blocks to be combined to form a wide variety of functional modules.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127271129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012769
M. Boule, Z. Zilic
This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blue's move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).
{"title":"An FPGA based move generator for the game of chess","authors":"M. Boule, Z. Zilic","doi":"10.1109/CICC.2002.1012769","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012769","url":null,"abstract":"This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blue's move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128841654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012875
K. Leung, P. Mok, Chi Yat Leung
A 4th-order curvature-compensated CMOS bandgap reference, which uses a high-resistive poly resistor to a generate temperature dependent resistor ratio, is proposed. The proposed reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C and a line regulation of /spl plusmn/1.25 mV/V are achieved at 2-V supply. The improvement on temperature coefficient is about 5 times reduction compared to the conventional approach.
{"title":"A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C 4th-order curvature-compensated CMOS bandgap reference","authors":"K. Leung, P. Mok, Chi Yat Leung","doi":"10.1109/CICC.2002.1012875","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012875","url":null,"abstract":"A 4th-order curvature-compensated CMOS bandgap reference, which uses a high-resistive poly resistor to a generate temperature dependent resistor ratio, is proposed. The proposed reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C and a line regulation of /spl plusmn/1.25 mV/V are achieved at 2-V supply. The improvement on temperature coefficient is about 5 times reduction compared to the conventional approach.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121035738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012805
D. Manstretta, F. Svelto
Two mechanisms are responsible for second order intermodulation in CMOS down-converters: RF self-mixing and device non-linearity and mismatches. An intuitive model and analytical expressions are provided for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8 V supply, part of a fully integrated 0.18 /spl mu/m CMOS UMTS receiver front-end shows 66 dBm IIP2 and 16 dBm IIP3.
{"title":"Analysis and optimization of IIP2 in CMOS direct down-converters","authors":"D. Manstretta, F. Svelto","doi":"10.1109/CICC.2002.1012805","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012805","url":null,"abstract":"Two mechanisms are responsible for second order intermodulation in CMOS down-converters: RF self-mixing and device non-linearity and mismatches. An intuitive model and analytical expressions are provided for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8 V supply, part of a fully integrated 0.18 /spl mu/m CMOS UMTS receiver front-end shows 66 dBm IIP2 and 16 dBm IIP3.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012847
J. Frambach, R. Heijna, R. Krosschell
Today's networks encompass a myriad of bit rates, both new appearing rates as well as legacy ones. To cover all these bit rates, a continuous rate chip-set was developed, containing a continuous rate clock and data recovery, capable of recovering any bit rate between 30 Mbit/s and 3.2 Gbit/s. While using only one single reference frequency, a frequency acquisition loop, based on a fractional-N divider and a frequency window detector, provides 4.8 Hz frequency resolution. A built-in PRBS generator provides for high frequency testing.
{"title":"Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s","authors":"J. Frambach, R. Heijna, R. Krosschell","doi":"10.1109/CICC.2002.1012847","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012847","url":null,"abstract":"Today's networks encompass a myriad of bit rates, both new appearing rates as well as legacy ones. To cover all these bit rates, a continuous rate chip-set was developed, containing a continuous rate clock and data recovery, capable of recovering any bit rate between 30 Mbit/s and 3.2 Gbit/s. While using only one single reference frequency, a frequency acquisition loop, based on a fractional-N divider and a frequency window detector, provides 4.8 Hz frequency resolution. A built-in PRBS generator provides for high frequency testing.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122754170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012832
Xiaohong Peng, W. Sansen
A new frequency-compensation topology (NGRNMC) is proposed, which improves the frequency characteristics and transient response of multistage amplifiers while minimizing the power consumption. Comparisons are made to demonstrate the advantages of the topology. A three-stage fully-differential NGRNMC amplifier, driving two 16 pF capacitors with 80 MHz GBW, is fabricated in a 0.35 /spl mu/m CMOS process, confirming the experimental results. Criteria are proposed to accurately evaluate and compare amplifiers implemented in different operating conditions.
{"title":"Nested feed-forward Gm-stage and nulling resistor plus nested-Miller compensation for multistage amplifiers","authors":"Xiaohong Peng, W. Sansen","doi":"10.1109/CICC.2002.1012832","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012832","url":null,"abstract":"A new frequency-compensation topology (NGRNMC) is proposed, which improves the frequency characteristics and transient response of multistage amplifiers while minimizing the power consumption. Comparisons are made to demonstrate the advantages of the topology. A three-stage fully-differential NGRNMC amplifier, driving two 16 pF capacitors with 80 MHz GBW, is fabricated in a 0.35 /spl mu/m CMOS process, confirming the experimental results. Criteria are proposed to accurately evaluate and compare amplifiers implemented in different operating conditions.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115689928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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