Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012829
A. Fontanelli, S. Arrigoni, D. Raccagni, M. Rosin
The accelerating pace of the technology race towards more complex integrated systems is leading to a series of drawbacks: awfully high pin-count and clock-speed, increasing mask costs and wafer yield issues due to mixing device technologies, and unachievable time-to-market. In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible. The combination of these two technological trends is driving the evolution of IC and package design and verification, which must be considered, more and more, as a single whole. For this evolution, to be successful, however, three ingredients are required: a change in methodology, the availability of a new category of EDA tools, and a major shift in the profile of the designers and engineers involved.
{"title":"System-on-chip (SoC) requires IC and package co-design and co-verification","authors":"A. Fontanelli, S. Arrigoni, D. Raccagni, M. Rosin","doi":"10.1109/CICC.2002.1012829","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012829","url":null,"abstract":"The accelerating pace of the technology race towards more complex integrated systems is leading to a series of drawbacks: awfully high pin-count and clock-speed, increasing mask costs and wafer yield issues due to mixing device technologies, and unachievable time-to-market. In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible. The combination of these two technological trends is driving the evolution of IC and package design and verification, which must be considered, more and more, as a single whole. For this evolution, to be successful, however, three ingredients are required: a change in methodology, the availability of a new category of EDA tools, and a major shift in the profile of the designers and engineers involved.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133165088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012869
Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon
A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.
采用合并电容开关(MCS)技术的10 b多比特/级流水线ADC在120 MSample/s下可实现53 dB SNDR，在输入频率高达奈奎斯特的100 MSample/s下可实现54 dB SNDR和68 dB SFDR。测得的DNL和INL分别为/spl plusmn/0.40 LSB和/spl plusmn/0.48 LSB。该ADC采用0.25 /spl μ m CMOS工艺制造，占用3.6 mm/sup / /有源芯片面积，在2.5 V电源下功耗为208 mW。
{"title":"A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR","authors":"Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon","doi":"10.1109/CICC.2002.1012869","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012869","url":null,"abstract":"A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114437609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012851
A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. Weijers, L. Perre
Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 /spl mu/s and a power consumption of less than 50 nJ/bit. The 14.7 mm/sup 2/ full-duplex full-parallel core, implemented in a CMOS 0.18 /spl mu/m technology, is a complete flexible solution for broadband turbo coding.
{"title":"A 80 Mb/s low-power scalable turbo codec core","authors":"A. Giulietti, B. Bougard, V. Derudder, S. Dupont, J. Weijers, L. Perre","doi":"10.1109/CICC.2002.1012851","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012851","url":null,"abstract":"Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 /spl mu/s and a power consumption of less than 50 nJ/bit. The 14.7 mm/sup 2/ full-duplex full-parallel core, implemented in a CMOS 0.18 /spl mu/m technology, is a complete flexible solution for broadband turbo coding.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012844
J. Sonntag, J. Stonick, J. Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, K. Lee, Bob Lefferts, David A. Yokoyama-Martin, U. Moon, Amber Sengir, Steve Titus, Gu-Yeon Wei, D. Weinlader, Yaohua Yang
This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.
{"title":"An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 /spl mu/m CMOS","authors":"J. Sonntag, J. Stonick, J. Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, K. Lee, Bob Lefferts, David A. Yokoyama-Martin, U. Moon, Amber Sengir, Steve Titus, Gu-Yeon Wei, D. Weinlader, Yaohua Yang","doi":"10.1109/CICC.2002.1012844","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012844","url":null,"abstract":"This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012831
Hoi Lee, P. Mok
This paper describes a novel active-feedback frequency compensation (AFFC) technique for low-power multi-stage amplifiers. With a high-speed active feedback block, the proposed compensation technique significantly improves both the frequency and the transient responses of the amplifier. Implemented by a standard 0.8/spl mu/m CMOS process, a three-stage AFFC amplifier achieves 100dB gain, 4.5MHz gain-bandwidth product, 65/spl deg/ phase margin and 1.5V//spl mu/s slew rate with 0.4mW power consumption when driving a 100pF capacitive load.
{"title":"Active-feedback frequency compensation for low-power multi-stage amplifiers","authors":"Hoi Lee, P. Mok","doi":"10.1109/CICC.2002.1012831","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012831","url":null,"abstract":"This paper describes a novel active-feedback frequency compensation (AFFC) technique for low-power multi-stage amplifiers. With a high-speed active feedback block, the proposed compensation technique significantly improves both the frequency and the transient responses of the amplifier. Implemented by a standard 0.8/spl mu/m CMOS process, a three-stage AFFC amplifier achieves 100dB gain, 4.5MHz gain-bandwidth product, 65/spl deg/ phase margin and 1.5V//spl mu/s slew rate with 0.4mW power consumption when driving a 100pF capacitive load.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115962988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012758
Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, T. King
An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.
{"title":"Loop-based interconnect modeling and optimization approach for multi-GHz clock network design","authors":"Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, T. King","doi":"10.1109/CICC.2002.1012758","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012758","url":null,"abstract":"An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121515870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012877
D. Chang, Lei Wu, U. Moon
A low-voltage opamp-reset switching technique (ORST) which avoids clock boosting/bootstrapping, switched-opamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10-bit 25 MSPS pipelined ADC. The prototype ADC demonstrates 55 dB SNR, 55 dB SFDR, and 48 dB SNDR at 1.4 V power supply. The ADC operates down to 1.3 V power supply (|V/sub TH,P/|=0-9 V) with 5 dB degradation in performance. Maximum operating frequency is 32 MSPS. The ORST is fully compatible with future low-voltage submicron CMOS processes.
提出了一种低压运放复位开关技术(ORST)，该技术可避免时钟升压/自启动、开关运放和阈值电压缩放。将该开关技术应用于一个10位25msps流水线ADC的设计。原型ADC在1.4 V电源下演示了55 dB信噪比、55 dB SFDR和48 dB SNDR。ADC工作在低至1.3 V的电源(|V/sub TH,P/|=0-9 V)下，性能下降5db。最大工作频率为32msps。ORST与未来的低压亚微米CMOS工艺完全兼容。
{"title":"Low-voltage pipelined ADC using opamp-reset switching technique","authors":"D. Chang, Lei Wu, U. Moon","doi":"10.1109/CICC.2002.1012877","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012877","url":null,"abstract":"A low-voltage opamp-reset switching technique (ORST) which avoids clock boosting/bootstrapping, switched-opamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10-bit 25 MSPS pipelined ADC. The prototype ADC demonstrates 55 dB SNR, 55 dB SFDR, and 48 dB SNDR at 1.4 V power supply. The ADC operates down to 1.3 V power supply (|V/sub TH,P/|=0-9 V) with 5 dB degradation in performance. Maximum operating frequency is 32 MSPS. The ORST is fully compatible with future low-voltage submicron CMOS processes.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121751141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012766
A. Roopchansingh, Jonathan Rose
Several commercial FPGA architectures provide fast connections between adjacent logic blocks that decrease the best-case delay between circuit elements with the goal of increasing overall performance. This paper explores the architecture of these Nearest Neighbour (NN) interconnects to determine topologies, quantities and distances that are best for performance and area. We show that certain architectures can achieve a 7.4% performance improvement at the cost of a 6.3% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.
{"title":"Nearest neighbour interconnect architecture in deep submicron FPGAs","authors":"A. Roopchansingh, Jonathan Rose","doi":"10.1109/CICC.2002.1012766","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012766","url":null,"abstract":"Several commercial FPGA architectures provide fast connections between adjacent logic blocks that decrease the best-case delay between circuit elements with the goal of increasing overall performance. This paper explores the architecture of these Nearest Neighbour (NN) interconnects to determine topologies, quantities and distances that are best for performance and area. We show that certain architectures can achieve a 7.4% performance improvement at the cost of a 6.3% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"35 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012796
Srinivasaraman Chandrasekaran, W. Black
A sigma-delta (SD) modulator has been developed for baseband processing in a direct conversion receiver (DCR). A second-order SD modulator with a subsampling mixer, inside the feedback loop, down-converts the incoming RF signals directly to baseband, digitizes them and attenuates noise as well as interferers. A prototype was fabricated in a TSMC 0.25 /spl mu/m process for use in a CDMA2000 transceiver. SNR greater than 53 dB was measured for single-ended baseband inputs and a SNR/sub max/ of 32 dB was measured for differential inputs at 900 MHz, over a 2 MHz bandwidth.
{"title":"Sub-sampling sigma-delta modulator for baseband processing","authors":"Srinivasaraman Chandrasekaran, W. Black","doi":"10.1109/CICC.2002.1012796","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012796","url":null,"abstract":"A sigma-delta (SD) modulator has been developed for baseband processing in a direct conversion receiver (DCR). A second-order SD modulator with a subsampling mixer, inside the feedback loop, down-converts the incoming RF signals directly to baseband, digitizes them and attenuates noise as well as interferers. A prototype was fabricated in a TSMC 0.25 /spl mu/m process for use in a CDMA2000 transceiver. SNR greater than 53 dB was measured for single-ended baseband inputs and a SNR/sub max/ of 32 dB was measured for differential inputs at 900 MHz, over a 2 MHz bandwidth.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012768
Ernie Lin, S. Wilton
Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.
{"title":"The architecture of dual-mode FPGA embedded system blocks","authors":"Ernie Lin, S. Wilton","doi":"10.1109/CICC.2002.1012768","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012768","url":null,"abstract":"Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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