Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012829
A. Fontanelli, S. Arrigoni, D. Raccagni, M. Rosin
The accelerating pace of the technology race towards more complex integrated systems is leading to a series of drawbacks: awfully high pin-count and clock-speed, increasing mask costs and wafer yield issues due to mixing device technologies, and unachievable time-to-market. In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible. The combination of these two technological trends is driving the evolution of IC and package design and verification, which must be considered, more and more, as a single whole. For this evolution, to be successful, however, three ingredients are required: a change in methodology, the availability of a new category of EDA tools, and a major shift in the profile of the designers and engineers involved.
{"title":"System-on-chip (SoC) requires IC and package co-design and co-verification","authors":"A. Fontanelli, S. Arrigoni, D. Raccagni, M. Rosin","doi":"10.1109/CICC.2002.1012829","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012829","url":null,"abstract":"The accelerating pace of the technology race towards more complex integrated systems is leading to a series of drawbacks: awfully high pin-count and clock-speed, increasing mask costs and wafer yield issues due to mixing device technologies, and unachievable time-to-market. In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible. The combination of these two technological trends is driving the evolution of IC and package design and verification, which must be considered, more and more, as a single whole. For this evolution, to be successful, however, three ingredients are required: a change in methodology, the availability of a new category of EDA tools, and a major shift in the profile of the designers and engineers involved.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133165088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012872
P. Drennan, C. McAndrew
This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, Vt and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in the prediction of mismatch. This model is applied to MOSFET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.
{"title":"Understanding MOSFET mismatch for analog design","authors":"P. Drennan, C. McAndrew","doi":"10.1109/CICC.2002.1012872","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012872","url":null,"abstract":"This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, Vt and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in the prediction of mismatch. This model is applied to MOSFET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114394761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012862
N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, C. Plett, Gerry Tarr
A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.
{"title":"A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS","authors":"N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, C. Plett, Gerry Tarr","doi":"10.1109/CICC.2002.1012862","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012862","url":null,"abstract":"A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"93 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012869
Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon
A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.
采用合并电容开关(MCS)技术的10 b多比特/级流水线ADC在120 MSample/s下可实现53 dB SNDR，在输入频率高达奈奎斯特的100 MSample/s下可实现54 dB SNDR和68 dB SFDR。测得的DNL和INL分别为/spl plusmn/0.40 LSB和/spl plusmn/0.48 LSB。该ADC采用0.25 /spl μ m CMOS工艺制造，占用3.6 mm/sup / /有源芯片面积，在2.5 V电源下功耗为208 mW。
{"title":"A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR","authors":"Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon","doi":"10.1109/CICC.2002.1012869","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012869","url":null,"abstract":"A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114437609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012844
J. Sonntag, J. Stonick, J. Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, K. Lee, Bob Lefferts, David A. Yokoyama-Martin, U. Moon, Amber Sengir, Steve Titus, Gu-Yeon Wei, D. Weinlader, Yaohua Yang
This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.
{"title":"An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 /spl mu/m CMOS","authors":"J. Sonntag, J. Stonick, J. Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, K. Lee, Bob Lefferts, David A. Yokoyama-Martin, U. Moon, Amber Sengir, Steve Titus, Gu-Yeon Wei, D. Weinlader, Yaohua Yang","doi":"10.1109/CICC.2002.1012844","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012844","url":null,"abstract":"This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm/sup 2/ device is implemented in a 0.25 /spl mu/m CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012877
D. Chang, Lei Wu, U. Moon
A low-voltage opamp-reset switching technique (ORST) which avoids clock boosting/bootstrapping, switched-opamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10-bit 25 MSPS pipelined ADC. The prototype ADC demonstrates 55 dB SNR, 55 dB SFDR, and 48 dB SNDR at 1.4 V power supply. The ADC operates down to 1.3 V power supply (|V/sub TH,P/|=0-9 V) with 5 dB degradation in performance. Maximum operating frequency is 32 MSPS. The ORST is fully compatible with future low-voltage submicron CMOS processes.
提出了一种低压运放复位开关技术(ORST)，该技术可避免时钟升压/自启动、开关运放和阈值电压缩放。将该开关技术应用于一个10位25msps流水线ADC的设计。原型ADC在1.4 V电源下演示了55 dB信噪比、55 dB SFDR和48 dB SNDR。ADC工作在低至1.3 V的电源(|V/sub TH,P/|=0-9 V)下，性能下降5db。最大工作频率为32msps。ORST与未来的低压亚微米CMOS工艺完全兼容。
{"title":"Low-voltage pipelined ADC using opamp-reset switching technique","authors":"D. Chang, Lei Wu, U. Moon","doi":"10.1109/CICC.2002.1012877","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012877","url":null,"abstract":"A low-voltage opamp-reset switching technique (ORST) which avoids clock boosting/bootstrapping, switched-opamp, and threshold voltage scaling is presented. The switching technique is applied to the design of a 10-bit 25 MSPS pipelined ADC. The prototype ADC demonstrates 55 dB SNR, 55 dB SFDR, and 48 dB SNDR at 1.4 V power supply. The ADC operates down to 1.3 V power supply (|V/sub TH,P/|=0-9 V) with 5 dB degradation in performance. Maximum operating frequency is 32 MSPS. The ORST is fully compatible with future low-voltage submicron CMOS processes.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121751141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012790
M. Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, M. Yoshimoto
This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13 /spl mu/m CMOS technology and contains approximately 7 M-transistors on 4.50 mm /spl times/ 3.35 mm area. The estimated power consumption is less than 100 mW at 81 MHz and 1.0 V. It features a gradient descent search (GDS) algorithm that drastically reduces the required computation power to 7 GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.
{"title":"An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm","authors":"M. Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, M. Yoshimoto","doi":"10.1109/CICC.2002.1012790","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012790","url":null,"abstract":"This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13 /spl mu/m CMOS technology and contains approximately 7 M-transistors on 4.50 mm /spl times/ 3.35 mm area. The estimated power consumption is less than 100 mW at 81 MHz and 1.0 V. It features a gradient descent search (GDS) algorithm that drastically reduces the required computation power to 7 GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121874659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012822
Hiroyulu Tsujikawa, K. Shimazaki, S. Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno
The main objective of our work is to develop a fast and accurate total solution for dramatically reducing electromagnetic interference (EMI) noise in high-performance LSI microchips at the design stage through unifying estimation, reduction, and verification. This innovative methodology has been proven in the successful design of a 32-bit microprocessor with very low EMI noise.
{"title":"A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification","authors":"Hiroyulu Tsujikawa, K. Shimazaki, S. Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno","doi":"10.1109/CICC.2002.1012822","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012822","url":null,"abstract":"The main objective of our work is to develop a fast and accurate total solution for dramatically reducing electromagnetic interference (EMI) noise in high-performance LSI microchips at the design stage through unifying estimation, reduction, and verification. This innovative methodology has been proven in the successful design of a 32-bit microprocessor with very low EMI noise.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012880
Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun
Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.
{"title":"Application-dependent scaling tradeoffs and optimization in the SoC era","authors":"Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun","doi":"10.1109/CICC.2002.1012880","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012880","url":null,"abstract":"Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126330226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012768
Ernie Lin, S. Wilton
Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.
{"title":"The architecture of dual-mode FPGA embedded system blocks","authors":"Ernie Lin, S. Wilton","doi":"10.1109/CICC.2002.1012768","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012768","url":null,"abstract":"Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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