Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012860
Albert Z. H. Wang, H. Feng, R. Zhan, Guang Chen, Q. Wu
The challenge in RF ESD protection circuit design, still a problem in definition, is to address the complex interactions between the ESD protection network and the circuit being protected in both directions. This paper discusses related key factors, e.g., switching and accidental triggering of ESD protection networks, as well as ESD-induced parasitic capacitive, resistive, noise coupling and self-generated noise effects. Evaluation techniques include S-parameter, Q-factor and overall specification examination. Low-parasitic compact structures are the solutions to RF ESD protection.
{"title":"ESD protection design for RF integrated circuits: new challenges","authors":"Albert Z. H. Wang, H. Feng, R. Zhan, Guang Chen, Q. Wu","doi":"10.1109/CICC.2002.1012860","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012860","url":null,"abstract":"The challenge in RF ESD protection circuit design, still a problem in definition, is to address the complex interactions between the ESD protection network and the circuit being protected in both directions. This paper discusses related key factors, e.g., switching and accidental triggering of ESD protection networks, as well as ESD-induced parasitic capacitive, resistive, noise coupling and self-generated noise effects. Evaluation techniques include S-parameter, Q-factor and overall specification examination. Low-parasitic compact structures are the solutions to RF ESD protection.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117204691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012894
R. Bashirullah, Wentai Liu, R. Cavin
In this paper, closed-form expressions of delay and power dissipation based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed, exhibiting an accuracy that is within 5% for a wide range of parameters. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling. A new power dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on these formulations, a comparison between voltage-mode repeater insertion technique and current-mode signaling over long global deep submicron interconnects is presented.
{"title":"Delay and power model for current-mode signaling in deep submicron global interconnects","authors":"R. Bashirullah, Wentai Liu, R. Cavin","doi":"10.1109/CICC.2002.1012894","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012894","url":null,"abstract":"In this paper, closed-form expressions of delay and power dissipation based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed, exhibiting an accuracy that is within 5% for a wide range of parameters. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling. A new power dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on these formulations, a comparison between voltage-mode repeater insertion technique and current-mode signaling over long global deep submicron interconnects is presented.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115426377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012826
J. Nabicht, Jeanne K. Pitz, P. Siniscalchi, C. Betty, Stephen Maggiotto, D. Richardson, S. M. DeSoto, Sucheendran Sridharan, S. Vemulapalli, Kenneth Downs, D. G. Gata, Ali K. Dweik, D. Guidry, Kyle D. Muskoff, Brandon Beckham, Glenn H. Westphal
An IF-baseband multi-chip module, fabricated in 3.3V 0.35/spl mu/m mixed-signal and 1.8V 0.18 /spl mu/m digital CMOS provides OQPSK demodulation with carrier recovery, memory and control, voice-companding codecs, and SLIC interfaces (SIs) for a CATV telephony distribution system. The die area of the mixed-signal IC is 84.9mm/sup 2/ and 15.2mm/sup 2/ for the digital IC. The power dissipation is 660mW.
{"title":"A voice processing and control module for cable telephony applications","authors":"J. Nabicht, Jeanne K. Pitz, P. Siniscalchi, C. Betty, Stephen Maggiotto, D. Richardson, S. M. DeSoto, Sucheendran Sridharan, S. Vemulapalli, Kenneth Downs, D. G. Gata, Ali K. Dweik, D. Guidry, Kyle D. Muskoff, Brandon Beckham, Glenn H. Westphal","doi":"10.1109/CICC.2002.1012826","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012826","url":null,"abstract":"An IF-baseband multi-chip module, fabricated in 3.3V 0.35/spl mu/m mixed-signal and 1.8V 0.18 /spl mu/m digital CMOS provides OQPSK demodulation with carrier recovery, memory and control, voice-companding codecs, and SLIC interfaces (SIs) for a CATV telephony distribution system. The die area of the mixed-signal IC is 84.9mm/sup 2/ and 15.2mm/sup 2/ for the digital IC. The power dissipation is 660mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116137292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012778
J. Moon, W. Athas, P. Beerel, J. Draper
This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.
{"title":"Low-power sequential access memory design","authors":"J. Moon, W. Athas, P. Beerel, J. Draper","doi":"10.1109/CICC.2002.1012778","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012778","url":null,"abstract":"This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012809
K. Fujii, M. Nakanishi, S. Shigematsu, H. Morimura, T. Hatano, N. Ikeda, T. Shimamura, Y. Okazaki, H. Kyuragi
A 500-dpi cellular-logic processing array performs all fingerprint identification steps on one chip, from image acquisition, enhancement, to verification. Morphological functions for executing these steps are implemented in a 30/spl times/50-/spl mu/m/sup 2/ processing unit. A single-cycle datapath and a shared logic structure enable compact implementation of the processing unit. A fabricated 224/spl times/256-pixel fingerprint identification LSI demonstrates fully-functional image processing and practical accuracy of identification.
{"title":"A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification","authors":"K. Fujii, M. Nakanishi, S. Shigematsu, H. Morimura, T. Hatano, N. Ikeda, T. Shimamura, Y. Okazaki, H. Kyuragi","doi":"10.1109/CICC.2002.1012809","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012809","url":null,"abstract":"A 500-dpi cellular-logic processing array performs all fingerprint identification steps on one chip, from image acquisition, enhancement, to verification. Morphological functions for executing these steps are implemented in a 30/spl times/50-/spl mu/m/sup 2/ processing unit. A single-cycle datapath and a shared logic structure enable compact implementation of the processing unit. A fabricated 224/spl times/256-pixel fingerprint identification LSI demonstrates fully-functional image processing and practical accuracy of identification.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012764
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
In this paper, a wide range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. Using the phase selection circuit and the start-controlled circuit enlarges the operating frequency range of this DLL and eliminates the harmonic locking problems. The operating frequency range of the DLL can be from 1/T/sub Dmin/ to 1/(N/spl times/T/sub Dmax/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. Fabricated in a 0.35 /spl mu/m 1P3M standard CMOS process, the DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz. The measurement results show that the operating frequency range is from 6 MHz to 130 MHz and the latency is just one clock cycle. From the entire operating frequency range, the maximum r.m.s. jitter would not exceed 25 ps.
{"title":"A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay","authors":"Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu","doi":"10.1109/CICC.2002.1012764","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012764","url":null,"abstract":"In this paper, a wide range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. Using the phase selection circuit and the start-controlled circuit enlarges the operating frequency range of this DLL and eliminates the harmonic locking problems. The operating frequency range of the DLL can be from 1/T/sub Dmin/ to 1/(N/spl times/T/sub Dmax/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. Fabricated in a 0.35 /spl mu/m 1P3M standard CMOS process, the DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz. The measurement results show that the operating frequency range is from 6 MHz to 130 MHz and the latency is just one clock cycle. From the entire operating frequency range, the maximum r.m.s. jitter would not exceed 25 ps.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131668816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012850
C. Nicol, M. Cooke
This paper describes the architecture of integrated circuits for base-band processing in 3rd Generation (3G) mobile wireless systems. Wideband CDMA receiver functions including the RAKE, rate de/matching, channel de/interleaving, channel de/coding and multi-user detection are described. Silicon implementations of a 3GPP channel decoder and also a multi-user base-band signal processor are presented. The high speed downlink packet access (HSDPA) system providing downlink data rates in excess of 10 Mbps and the 20 Mbps multiple input/multiple output (MIMO) extensions are also described. The architecture of a 21.6 Mbps MIMO HSDPA receiver for mobile terminals with 2 or 4 antennas is shown that uses the V-BLAST MIMO detection algorithm.
本文介绍了第三代移动无线系统中用于基带处理的集成电路体系结构。描述了宽带CDMA接收机的RAKE、速率解/匹配、信道解/交织、信道解/编码和多用户检测等功能。给出了一个3GPP信道解码器和一个多用户基带信号处理器的硅实现。高速下行分组接入(HSDPA)系统提供下行数据速率超过10 Mbps和20 Mbps多输入/多输出(MIMO)扩展。给出了采用V-BLAST MIMO检测算法的移动终端21.6 Mbps MIMO HSDPA接收机的结构。
{"title":"Integrated circuits for 3GPP mobile wireless systems","authors":"C. Nicol, M. Cooke","doi":"10.1109/CICC.2002.1012850","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012850","url":null,"abstract":"This paper describes the architecture of integrated circuits for base-band processing in 3rd Generation (3G) mobile wireless systems. Wideband CDMA receiver functions including the RAKE, rate de/matching, channel de/interleaving, channel de/coding and multi-user detection are described. Silicon implementations of a 3GPP channel decoder and also a multi-user base-band signal processor are presented. The high speed downlink packet access (HSDPA) system providing downlink data rates in excess of 10 Mbps and the 20 Mbps multiple input/multiple output (MIMO) extensions are also described. The architecture of a 21.6 Mbps MIMO HSDPA receiver for mobile terminals with 2 or 4 antennas is shown that uses the V-BLAST MIMO detection algorithm.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115129084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012868
M. Clara, A. Wiesbauer, F. Kuttner
A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.
{"title":"A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 /spl mu/m CMOS","authors":"M. Clara, A. Wiesbauer, F. Kuttner","doi":"10.1109/CICC.2002.1012868","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012868","url":null,"abstract":"A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129717228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012865
B. Song, T. Cho, D. Kang, S. Dow
An IQ processor in 0.18 /spl mu/m CMOS implements Bluetooth low-IF functions at 2 MHz with 7/sup th/-order complex Bessel bandpass IF filter, limiter, quadricorrelator baseband FM demodulator, and differential slope sensing bit slicer. The sensitivity is -46 dBm at 0.1% BER. The chip consumes 50 mW at 1.8 V and occupies 2 mm/spl times/2.8 mm.
{"title":"A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicer","authors":"B. Song, T. Cho, D. Kang, S. Dow","doi":"10.1109/CICC.2002.1012865","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012865","url":null,"abstract":"An IQ processor in 0.18 /spl mu/m CMOS implements Bluetooth low-IF functions at 2 MHz with 7/sup th/-order complex Bessel bandpass IF filter, limiter, quadricorrelator baseband FM demodulator, and differential slope sensing bit slicer. The sensitivity is -46 dBm at 0.1% BER. The chip consumes 50 mW at 1.8 V and occupies 2 mm/spl times/2.8 mm.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 11 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125744270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012890
N. Barton, D. Ozis, T. Fiez, K. Mayaram
Measurements, simulations and equations show that differential and single-ended ring oscillators have comparable performance when subjected to the same deterministic noise sources. Both topologies are shown to have a much greater sensitivity to supply noise than substrate noise. It is also shown that symmetrical/asymmetrical noise injection must be considered. The measured results are compared to predictive jitter equations and Spectre/spl reg/ time domain simulations. It is shown that the measurements are in agreement with the simulations and equations.
{"title":"The effect of supply and substrate noise on jitter in ring oscillators","authors":"N. Barton, D. Ozis, T. Fiez, K. Mayaram","doi":"10.1109/CICC.2002.1012890","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012890","url":null,"abstract":"Measurements, simulations and equations show that differential and single-ended ring oscillators have comparable performance when subjected to the same deterministic noise sources. Both topologies are shown to have a much greater sensitivity to supply noise than substrate noise. It is also shown that symmetrical/asymmetrical noise injection must be considered. The measured results are compared to predictive jitter equations and Spectre/spl reg/ time domain simulations. It is shown that the measurements are in agreement with the simulations and equations.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"10 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134574919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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