Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012822
Hiroyulu Tsujikawa, K. Shimazaki, S. Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno
The main objective of our work is to develop a fast and accurate total solution for dramatically reducing electromagnetic interference (EMI) noise in high-performance LSI microchips at the design stage through unifying estimation, reduction, and verification. This innovative methodology has been proven in the successful design of a 32-bit microprocessor with very low EMI noise.
{"title":"A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification","authors":"Hiroyulu Tsujikawa, K. Shimazaki, S. Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno","doi":"10.1109/CICC.2002.1012822","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012822","url":null,"abstract":"The main objective of our work is to develop a fast and accurate total solution for dramatically reducing electromagnetic interference (EMI) noise in high-performance LSI microchips at the design stage through unifying estimation, reduction, and verification. This innovative methodology has been proven in the successful design of a 32-bit microprocessor with very low EMI noise.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012795
Matthew R. Miller, C. Petrie
A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.
{"title":"A multi-bit sigma-delta ADC for multi-mode receivers","authors":"Matthew R. Miller, C. Petrie","doi":"10.1109/CICC.2002.1012795","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012795","url":null,"abstract":"A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012862
N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, C. Plett, Gerry Tarr
A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.
{"title":"A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS","authors":"N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, C. Plett, Gerry Tarr","doi":"10.1109/CICC.2002.1012862","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012862","url":null,"abstract":"A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"93 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012872
P. Drennan, C. McAndrew
This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, Vt and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in the prediction of mismatch. This model is applied to MOSFET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.
{"title":"Understanding MOSFET mismatch for analog design","authors":"P. Drennan, C. McAndrew","doi":"10.1109/CICC.2002.1012872","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012872","url":null,"abstract":"This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, Vt and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in the prediction of mismatch. This model is applied to MOSFET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114394761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012790
M. Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, M. Yoshimoto
This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13 /spl mu/m CMOS technology and contains approximately 7 M-transistors on 4.50 mm /spl times/ 3.35 mm area. The estimated power consumption is less than 100 mW at 81 MHz and 1.0 V. It features a gradient descent search (GDS) algorithm that drastically reduces the required computation power to 7 GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.
{"title":"An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm","authors":"M. Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, M. Yoshimoto","doi":"10.1109/CICC.2002.1012790","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012790","url":null,"abstract":"This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13 /spl mu/m CMOS technology and contains approximately 7 M-transistors on 4.50 mm /spl times/ 3.35 mm area. The estimated power consumption is less than 100 mW at 81 MHz and 1.0 V. It features a gradient descent search (GDS) algorithm that drastically reduces the required computation power to 7 GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121874659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012880
Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun
Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.
{"title":"Application-dependent scaling tradeoffs and optimization in the SoC era","authors":"Carlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun","doi":"10.1109/CICC.2002.1012880","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012880","url":null,"abstract":"Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126330226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012874
K. Krishna, W. Bright, D. Dye, K. Muhammad, Yin Hu
Spatial gradients often limit the matching accuracy of element arrays in ADC's and DAC's. We cast. the problem of spatial gradients formally and present a global optimization-based solution that does not require the gradients to be pre-characterized precisely or limit them to being linear and/or quadratic. Si results from a standalone BiCMOS DAC and a CMOS DAC, part of the industry's first DOCSIS 1.1 certified cable modem solution, are presented.
{"title":"Spatial averaging and ordering in matched element arrays","authors":"K. Krishna, W. Bright, D. Dye, K. Muhammad, Yin Hu","doi":"10.1109/CICC.2002.1012874","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012874","url":null,"abstract":"Spatial gradients often limit the matching accuracy of element arrays in ADC's and DAC's. We cast. the problem of spatial gradients formally and present a global optimization-based solution that does not require the gradients to be pre-characterized precisely or limit them to being linear and/or quadratic. Si results from a standalone BiCMOS DAC and a CMOS DAC, part of the industry's first DOCSIS 1.1 certified cable modem solution, are presented.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127655576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012773
Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang
A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.
{"title":"High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies","authors":"Chung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, S. Tu, Mark Chen, Mi-Chang Chang","doi":"10.1109/CICC.2002.1012773","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012773","url":null,"abstract":"A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012836
A. Zolfaghari, B. Razavi
A fourth-order filter incorporates a method of suppressing interferers without filtering the desired signal, relaxing the trade-offs between noise, linearity, and power dissipation. Designed for the baseband of a 2.4 GHz receiver and fabricated in a 0.25 /spl mu/m CMOS technology, the filter exhibits an input-referred noise of 17 nV//spl radic/(Hz) while dissipating 2 mW from a 2.5 V supply and the receiver achieves a noise figure of 6 dB with a power consumption of 17.5 mW.
{"title":"A noninvasive channel-select filter for a CMOS Bluetooth receiver","authors":"A. Zolfaghari, B. Razavi","doi":"10.1109/CICC.2002.1012836","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012836","url":null,"abstract":"A fourth-order filter incorporates a method of suppressing interferers without filtering the desired signal, relaxing the trade-offs between noise, linearity, and power dissipation. Designed for the baseband of a 2.4 GHz receiver and fabricated in a 0.25 /spl mu/m CMOS technology, the filter exhibits an input-referred noise of 17 nV//spl radic/(Hz) while dissipating 2 mW from a 2.5 V supply and the receiver achieves a noise figure of 6 dB with a power consumption of 17.5 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128958372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/CICC.2002.1012785
H. Kuo, I. Verbauwhede, P. Schaumont
In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.
{"title":"A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology","authors":"H. Kuo, I. Verbauwhede, P. Schaumont","doi":"10.1109/CICC.2002.1012785","DOIUrl":"https://doi.org/10.1109/CICC.2002.1012785","url":null,"abstract":"In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128449334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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