Qi Zhang, Haichun Yang, Y. Hsieh, Jiajun Chen, Jiaying Yang, T. Xie, Shanyu Wang, H. Chung
With Moore’s law continues to drive IC feature size and device density, advanced technology evolves to enable not only smaller feature size but also 3D structures for logic and memory chipmakers.1 The associated process requires precise surface/interface functionality and material loss control, as a result plasma damage free process and isotropic etch with high selectivity became crucial for advanced 3D transistor manufacturing. High density radical based processes provide ideal solutions with very low electron temperature, excellent step coverage and ultra-high selectivity. The highly reactive radicals can largely reduce thermal budget as well. In this article radical based surface treatments and material modifications including metal treatment, surface reduction and surface smoothing are discussed. Furthermore, the benefits of combining such surface treatment and radical based selective etch are also presented with examples of Si and TiN etch processes. Both surface treatment and selective etch processes are enabled by high density ICP plasmas generated radicals.
{"title":"Radical-based surface treatment and selective etch enabled by high density ICP remote plasma source","authors":"Qi Zhang, Haichun Yang, Y. Hsieh, Jiajun Chen, Jiaying Yang, T. Xie, Shanyu Wang, H. Chung","doi":"10.1117/12.2662532","DOIUrl":"https://doi.org/10.1117/12.2662532","url":null,"abstract":"With Moore’s law continues to drive IC feature size and device density, advanced technology evolves to enable not only smaller feature size but also 3D structures for logic and memory chipmakers.1 The associated process requires precise surface/interface functionality and material loss control, as a result plasma damage free process and isotropic etch with high selectivity became crucial for advanced 3D transistor manufacturing. High density radical based processes provide ideal solutions with very low electron temperature, excellent step coverage and ultra-high selectivity. The highly reactive radicals can largely reduce thermal budget as well. In this article radical based surface treatments and material modifications including metal treatment, surface reduction and surface smoothing are discussed. Furthermore, the benefits of combining such surface treatment and radical based selective etch are also presented with examples of Si and TiN etch processes. Both surface treatment and selective etch processes are enabled by high density ICP plasmas generated radicals.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thorsten Last, M. Mongillo, T. Ivanov, Adriaan Rol, A. Lawrence, G. Alberts, D. Wan, A. Potočnik, K. De Greve
Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.
{"title":"Key ingredients for manufacturing superconducting quantum processors at scale","authors":"Thorsten Last, M. Mongillo, T. Ivanov, Adriaan Rol, A. Lawrence, G. Alberts, D. Wan, A. Potočnik, K. De Greve","doi":"10.1117/12.2657319","DOIUrl":"https://doi.org/10.1117/12.2657319","url":null,"abstract":"Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"12497 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129815758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xisen Hou, Yinjie Cen, Paul Baranowsky, D. Kang, Cong Liu, C. Xu
The semiconductor industry is on the rise of maturing EUV lithography in high volume manufacturing (HVM). There remain, however, challenges to be overcome in the advancement of photoresist to improve yield and reduce cost of ownership. Herein, we report a novel chemical trimming overcoat process as a post-lithography spin-on solution to enhance EUV photoresist performance, enabling effective photospeed reduction as well as process window enhancement, such as reducing bridging defect at underdose. This is a highly versatile and tunable process for most chemically amplified photoresists, therefore allowing it to become a general process for a wide range of applications across EUV lithography.
{"title":"Chemical trimming overcoat: an advanced spin-on process for photoresist enhancement in EUV lithography","authors":"Xisen Hou, Yinjie Cen, Paul Baranowsky, D. Kang, Cong Liu, C. Xu","doi":"10.1117/12.2658882","DOIUrl":"https://doi.org/10.1117/12.2658882","url":null,"abstract":"The semiconductor industry is on the rise of maturing EUV lithography in high volume manufacturing (HVM). There remain, however, challenges to be overcome in the advancement of photoresist to improve yield and reduce cost of ownership. Herein, we report a novel chemical trimming overcoat process as a post-lithography spin-on solution to enhance EUV photoresist performance, enabling effective photospeed reduction as well as process window enhancement, such as reducing bridging defect at underdose. This is a highly versatile and tunable process for most chemically amplified photoresists, therefore allowing it to become a general process for a wide range of applications across EUV lithography.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices. In addition, we present a reverse tone pattern transfer process that has the potential to further reduce GCDU and EPE for NIL.
{"title":"Nanoimprint post processing techniques to address edge placement error","authors":"Makoto Ogusu, Masaki Ishida, Masahiro Tamura, Keita Sakai, Toshiki Ito, Yuto Ito, I. Kawata, Hideki Kunugi, Shuhei Tamura, Ryuichi Asako, Keisuke Tanaka, Tomohito Yamaji","doi":"10.1117/12.2658125","DOIUrl":"https://doi.org/10.1117/12.2658125","url":null,"abstract":"Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices. In addition, we present a reverse tone pattern transfer process that has the potential to further reduce GCDU and EPE for NIL.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ji Young Park, Thanh Cuong Nguyen, Deakeon Kim, Hyun-Ji Song, Suk-Koo Hong, W. Son, Hyoshin Ahn, I. Jang, Dae Sin Kim
Theoretical lithography performance prediction of photoresist material has important role to design better material but the exact prediction was still difficult because there are too many conditions to be considered together. We investigated the EUV-induced photochemical reactions of conventional triphenylsulfonium (Ph3S+; TPS) PAG-cation in both “electron-trapping” and “internal excitation” mechanisms using atomic-scale materials modeling. By obtaining full energy profiles of protonation process of TPS molecule, we could find that the acid generation yield strongly depends on two main factors: the LUMO of PAG-cation in which the lower LUMO of PAG-cation, the reduction step of PAG-cation is easier and the proton (H+) dissociation ability (pKa) at the ortho-positions of thiol ether fragment cation(Ph2S+), in which lower pKa will give high acid generation. By matching computational analysis with experimental results, we developed a two-parameter model to predict the EUV exposure Dose from the target PAG–cation’s LUMO and pKa of thiol ether-derivatives. We applied our new model to other three sets of TPS samples and they also shows good correlation with experimental data. Finally, we proposed a strategy to design new PAG molecules for sensitivity improvement by functionalization of TSP-cation with electron donating group. Our new strategy can be a powerful tool to design novel PAG cation for EUV photoresist for improving Resolution-LER-Sensitivity trade-off.
{"title":"EUV-induced activation mechanism of photoacid generators: key factors affecting EUV sensitivity","authors":"Ji Young Park, Thanh Cuong Nguyen, Deakeon Kim, Hyun-Ji Song, Suk-Koo Hong, W. Son, Hyoshin Ahn, I. Jang, Dae Sin Kim","doi":"10.1117/12.2652345","DOIUrl":"https://doi.org/10.1117/12.2652345","url":null,"abstract":"Theoretical lithography performance prediction of photoresist material has important role to design better material but the exact prediction was still difficult because there are too many conditions to be considered together. We investigated the EUV-induced photochemical reactions of conventional triphenylsulfonium (Ph3S+; TPS) PAG-cation in both “electron-trapping” and “internal excitation” mechanisms using atomic-scale materials modeling. By obtaining full energy profiles of protonation process of TPS molecule, we could find that the acid generation yield strongly depends on two main factors: the LUMO of PAG-cation in which the lower LUMO of PAG-cation, the reduction step of PAG-cation is easier and the proton (H+) dissociation ability (pKa) at the ortho-positions of thiol ether fragment cation(Ph2S+), in which lower pKa will give high acid generation. By matching computational analysis with experimental results, we developed a two-parameter model to predict the EUV exposure Dose from the target PAG–cation’s LUMO and pKa of thiol ether-derivatives. We applied our new model to other three sets of TPS samples and they also shows good correlation with experimental data. Finally, we proposed a strategy to design new PAG molecules for sensitivity improvement by functionalization of TSP-cation with electron donating group. Our new strategy can be a powerful tool to design novel PAG cation for EUV photoresist for improving Resolution-LER-Sensitivity trade-off.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132648377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ever since IBM pioneered microelectronics packaging, IBM Research has continued to innovate to ensure that packaging and heterogeneous integration technology is available to satisfy the needs for performance, complexity, and memory and logic density with regard to high performance computing systems. In this era of ever-expanding need for high-performance computing and ever-pervasive artificial intelligence, traditional scaling economics headwinds combined with the need for versatility and fast product development mandate a system-level approach to generate the efficiencies the industry has been able to provide in the past through more traditional scaling approaches. This system-level approach renders imperative the use of chiplet-based architectures and the use of heterogeneous integration and advanced packaging to achieve the disaggregation with best-performing and most efficient IP components to sustain a viable economic model while achieving performance targets. In this talk we will discuss several key process and integration considerations that drive the use of various horizontal and vertical interconnection technology elements that must be implemented to enable the successful realization of efficient and cost-effective high-performance systems in the AI era. Future progress on these technology fronts will depend on disruptive innovation in two critical areas: (a) wafer-level and die-level processes, such as lithographic patterning, wafer-wafer bonding and debonding, bond and assembly processes, etc. that can enable packaging of these heterogeneous structures without compromising performance and reliability, (b) commensurate improvements and enablement of adequate metrology and inspection solutions to address the challenges stemming from these new chiplet-interconnecting methods and the associated topographic implications.
{"title":"The evolution of heterogeneous integration and packaging for the age of chiplets","authors":"S. Skordas","doi":"10.1117/12.2659730","DOIUrl":"https://doi.org/10.1117/12.2659730","url":null,"abstract":"Ever since IBM pioneered microelectronics packaging, IBM Research has continued to innovate to ensure that packaging and heterogeneous integration technology is available to satisfy the needs for performance, complexity, and memory and logic density with regard to high performance computing systems. In this era of ever-expanding need for high-performance computing and ever-pervasive artificial intelligence, traditional scaling economics headwinds combined with the need for versatility and fast product development mandate a system-level approach to generate the efficiencies the industry has been able to provide in the past through more traditional scaling approaches. This system-level approach renders imperative the use of chiplet-based architectures and the use of heterogeneous integration and advanced packaging to achieve the disaggregation with best-performing and most efficient IP components to sustain a viable economic model while achieving performance targets. In this talk we will discuss several key process and integration considerations that drive the use of various horizontal and vertical interconnection technology elements that must be implemented to enable the successful realization of efficient and cost-effective high-performance systems in the AI era. Future progress on these technology fronts will depend on disruptive innovation in two critical areas: (a) wafer-level and die-level processes, such as lithographic patterning, wafer-wafer bonding and debonding, bond and assembly processes, etc. that can enable packaging of these heterogeneous structures without compromising performance and reliability, (b) commensurate improvements and enablement of adequate metrology and inspection solutions to address the challenges stemming from these new chiplet-interconnecting methods and the associated topographic implications.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Evrard, N. Sadegh, C. Hsu, N. Mahne, A. Giglia, S. Nannarone, Y. Ekinci, M. Vockenhuber, A. Nishimura, T. Goya, T. Sugioka, A. Brouwer
In this work we assess the effect of the change of counter-anions on the photolithography properties of butyl-Sn12 oxo hydroxo cages. The hydroxide anions were exchanged with tetrakis(pentafluorophenyl)borate (B(PFP)4)- and (phenyl) trifluoroborate (BF3Ph)- anions which exhibit a photoabsorption cross section at 92 eV that is similar to that of the butyl-Sn12 oxo hydroxo cages. The degradation of the EUV photoresist was monitored via in-situ EUV exposure followed by X-ray photoelectron spectroscopy (XPS) at the BEAR beamline (Elettra, Italy) at the C1s-edge. Both systems exhibit similar carbon losses of around 25% for 100 mJ/cm2 dose. The Sn12 cluster with acetate anions, as a reference compound, exhibit a loss of C1s XPS signal from the butyl chains of around 23% for the same 100 mJ/cm2 EUV exposure dose indicating a larger degradation of the Sn12 cluster for the latter. We also evaluated the patterning performance of the Sn12(B(PFP)4) resist via interference lithography at the XIL-II beamline (PSI, Switzerland) and found the positive tone character of the resist and its ability to write lines with 50 nm half pitch resolution for doses of 30 mJ/cm2. In contrast, Sn12(BF3Ph) acts as a sensitive negative tone resist, with doses of 12.5 mJ/cm2 sufficient to write 50 nm half pitch lines.
{"title":"Influence of the anion in tin-based EUV photoresists properties","authors":"Q. Evrard, N. Sadegh, C. Hsu, N. Mahne, A. Giglia, S. Nannarone, Y. Ekinci, M. Vockenhuber, A. Nishimura, T. Goya, T. Sugioka, A. Brouwer","doi":"10.1117/12.2658498","DOIUrl":"https://doi.org/10.1117/12.2658498","url":null,"abstract":"In this work we assess the effect of the change of counter-anions on the photolithography properties of butyl-Sn12 oxo hydroxo cages. The hydroxide anions were exchanged with tetrakis(pentafluorophenyl)borate (B(PFP)4)- and (phenyl) trifluoroborate (BF3Ph)- anions which exhibit a photoabsorption cross section at 92 eV that is similar to that of the butyl-Sn12 oxo hydroxo cages. The degradation of the EUV photoresist was monitored via in-situ EUV exposure followed by X-ray photoelectron spectroscopy (XPS) at the BEAR beamline (Elettra, Italy) at the C1s-edge. Both systems exhibit similar carbon losses of around 25% for 100 mJ/cm2 dose. The Sn12 cluster with acetate anions, as a reference compound, exhibit a loss of C1s XPS signal from the butyl chains of around 23% for the same 100 mJ/cm2 EUV exposure dose indicating a larger degradation of the Sn12 cluster for the latter. We also evaluated the patterning performance of the Sn12(B(PFP)4) resist via interference lithography at the XIL-II beamline (PSI, Switzerland) and found the positive tone character of the resist and its ability to write lines with 50 nm half pitch resolution for doses of 30 mJ/cm2. In contrast, Sn12(BF3Ph) acts as a sensitive negative tone resist, with doses of 12.5 mJ/cm2 sufficient to write 50 nm half pitch lines.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115151712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Verstraete, H. Suh, Julie Van Bel, Purnota Hannan Timi, Rémi Vallat, P. Bézard, J. Vandereyken, Matteo Beggiato, A. Tamaddon, C. Beral, Waikin Li, Mihir Gupta, R. Fallica
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.
{"title":"Mitigating stochastics in EUV lithography by directed self-assembly","authors":"L. Verstraete, H. Suh, Julie Van Bel, Purnota Hannan Timi, Rémi Vallat, P. Bézard, J. Vandereyken, Matteo Beggiato, A. Tamaddon, C. Beral, Waikin Li, Mihir Gupta, R. Fallica","doi":"10.1117/12.2657939","DOIUrl":"https://doi.org/10.1117/12.2657939","url":null,"abstract":"Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123253646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modelling the pattern formation process in photoresist materials for extreme ultraviolet (EUV) lithography in a stochastic and mechanistic manner, with molecular-scale resolution, should enable predicting the effect of variations of material parameters and process conditions, leading to insights into the ultimate resolution limits. In this work, we present the results of the first steps toward that goal. We describe the physics of the development with time of cascades of electrons and holes, created by the stochastic absorption of 92 eV photons, using a kinetic Monte Carlo model with molecular resolution. The thin film material is modelled assuming a cubic array of lattice sites, at a distance that is consistent with the molecular density of the photoresist material that is considered. The simulation of the cascading process is based on the experimental optical energy loss function, extended to include also excitations with momentum transfer. The method allows for including the Coulomb interactions between charges. In contrast to earlier work, within which the high-energy electrons move ballistically until scattering takes place, the trajectories are in our model formed by stochastically determined interconnected molecular sites. In future extensions of the model, this approach will facilitate including in a natural way a transition from delocalized electron transport at high energies to hopping transport of localized electrons at low energies. The simulations are used to study the sensitivity of the average number of degradations per absorbed photon and the average electron blur length on the rates of elastic scattering and of molecular degradation, and on the energy that is lost upon a molecular degradation process.
{"title":"Towards molecular-scale kinetic Monte Carlo simulation of pattern formation in photoresist materials for EUV nanolithography","authors":"Lois Fernandez Miguez, P. Bobbert, R. Coehoorn","doi":"10.1117/12.2658404","DOIUrl":"https://doi.org/10.1117/12.2658404","url":null,"abstract":"Modelling the pattern formation process in photoresist materials for extreme ultraviolet (EUV) lithography in a stochastic and mechanistic manner, with molecular-scale resolution, should enable predicting the effect of variations of material parameters and process conditions, leading to insights into the ultimate resolution limits. In this work, we present the results of the first steps toward that goal. We describe the physics of the development with time of cascades of electrons and holes, created by the stochastic absorption of 92 eV photons, using a kinetic Monte Carlo model with molecular resolution. The thin film material is modelled assuming a cubic array of lattice sites, at a distance that is consistent with the molecular density of the photoresist material that is considered. The simulation of the cascading process is based on the experimental optical energy loss function, extended to include also excitations with momentum transfer. The method allows for including the Coulomb interactions between charges. In contrast to earlier work, within which the high-energy electrons move ballistically until scattering takes place, the trajectories are in our model formed by stochastically determined interconnected molecular sites. In future extensions of the model, this approach will facilitate including in a natural way a transition from delocalized electron transport at high energies to hopping transport of localized electrons at low energies. The simulations are used to study the sensitivity of the average number of degradations per absorbed photon and the average electron blur length on the rates of elastic scattering and of molecular degradation, and on the energy that is lost upon a molecular degradation process.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124209138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The manufacturing process of advanced logic devices has become ever more challenging than before due to continued shrinkage in dimensions from scaling down and increased complexity from the integration of new transistor structures such as gate-all-around (GAA). Underlayers are utilized as a mask to protect targeted device structures while selected areas of deposited metal is removed by wet etchant during replacement metal gate (RMG) process to construct the transistor. Reported studies describing the developmental strategies for such underlayers have been mostly focused on how to strengthen the adhesion towards the substrate with the designed film properties. In this paper, we identify the effect of plasma during dry etching of the RMG process as the factor to be considered in designing of the wet etch resistant underlayer. Physical and chemical properties of organic films after dry etching with plasmas of different gases have been investigated using various analysis techniques, and the subsequent effect of plasma-modification on the film properties such as resistance towards wet chemicals for various films was evaluated.
{"title":"Modification of organic underlayers by plasma during dry etching and its effect on the film properties","authors":"Soojung Leem, Jae Hwan Sim, Youngeun Bae","doi":"10.1117/12.2658118","DOIUrl":"https://doi.org/10.1117/12.2658118","url":null,"abstract":"The manufacturing process of advanced logic devices has become ever more challenging than before due to continued shrinkage in dimensions from scaling down and increased complexity from the integration of new transistor structures such as gate-all-around (GAA). Underlayers are utilized as a mask to protect targeted device structures while selected areas of deposited metal is removed by wet etchant during replacement metal gate (RMG) process to construct the transistor. Reported studies describing the developmental strategies for such underlayers have been mostly focused on how to strengthen the adhesion towards the substrate with the designed film properties. In this paper, we identify the effect of plasma during dry etching of the RMG process as the factor to be considered in designing of the wet etch resistant underlayer. Physical and chemical properties of organic films after dry etching with plasmas of different gases have been investigated using various analysis techniques, and the subsequent effect of plasma-modification on the film properties such as resistance towards wet chemicals for various films was evaluated.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125429642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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