Julie Van Bel, L. Verstraete, H. Suh, S. De Gendt, P. Bézard, J. Vandereyken, Waikin Li, Matteo Beggiato, A. Tamaddon, C. Beral, Andreia Santos, Boaz Alperson, Y. Her
For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.1 In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.
{"title":"EUV lithography line-space pattern rectification using block copolymer directed self-assembly: a roughness and defectivity study","authors":"Julie Van Bel, L. Verstraete, H. Suh, S. De Gendt, P. Bézard, J. Vandereyken, Waikin Li, Matteo Beggiato, A. Tamaddon, C. Beral, Andreia Santos, Boaz Alperson, Y. Her","doi":"10.1117/12.2657990","DOIUrl":"https://doi.org/10.1117/12.2657990","url":null,"abstract":"For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.1 In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127460238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yang H. Ban, Leandro Medina, Michael Da Silva, Sebastian Naranjo, Meghali J. Chopra
Reducing process development time and speeding up time to market are perennial challenges in the microelectronics industry. The development of etch models that permit optimizations across the wafer would enable manufacturers to optimize process design flows and predict process defects before a single wafer is run. The challenges of across-wafer uniformity optimizations include the large variety of features across the wafer, etch variations that occur at multiple scales within the plasma chamber, feature metrology, and computationally expensive model development. Compounding these challenges are trade-offs between data quality and time/cost-effectiveness, the wide variety of measurement information provided by different tools, and the sparsity and inconsistency of human-collected data. We address these challenges with a feature and wafer level modeling approach. First, experiments are conducted for a variety of etch conditions (e.g., pressure, gas composition, flow rate, temperature, power, and bias). Second, a feature level model is calibrated at multiple sites across the wafer based on OCD and/or cross-sectional SEM measurements. Finally, the calibrated model is used to predict an optimal set of process conditions to preserve uniformity across the wafer and to meet recipe targets. We demonstrate the methodology using SandBox Studio™ AI for a FinFET application. Specifically, we show the rapid and automated calibration of feature level models using experimental measurements of the 3D feature etch at a variety of process conditions. Automated image segmentation of X-SEM data is also performed here for single case using Weave® to demonstrate how such data can be acquired quickly in a development environment. We then demonstrate the effectiveness of the reduced-order model to predict optimal recipe conditions to improve overall recipe performance. We show how, with this hybrid-metrology computational approach, a process window that yields 89.2% of the wafer can be captured.
{"title":"A method for achieving sub-2nm across-wafer uniformity performance","authors":"Yang H. Ban, Leandro Medina, Michael Da Silva, Sebastian Naranjo, Meghali J. Chopra","doi":"10.1117/12.2662423","DOIUrl":"https://doi.org/10.1117/12.2662423","url":null,"abstract":"Reducing process development time and speeding up time to market are perennial challenges in the microelectronics industry. The development of etch models that permit optimizations across the wafer would enable manufacturers to optimize process design flows and predict process defects before a single wafer is run. The challenges of across-wafer uniformity optimizations include the large variety of features across the wafer, etch variations that occur at multiple scales within the plasma chamber, feature metrology, and computationally expensive model development. Compounding these challenges are trade-offs between data quality and time/cost-effectiveness, the wide variety of measurement information provided by different tools, and the sparsity and inconsistency of human-collected data. We address these challenges with a feature and wafer level modeling approach. First, experiments are conducted for a variety of etch conditions (e.g., pressure, gas composition, flow rate, temperature, power, and bias). Second, a feature level model is calibrated at multiple sites across the wafer based on OCD and/or cross-sectional SEM measurements. Finally, the calibrated model is used to predict an optimal set of process conditions to preserve uniformity across the wafer and to meet recipe targets. We demonstrate the methodology using SandBox Studio™ AI for a FinFET application. Specifically, we show the rapid and automated calibration of feature level models using experimental measurements of the 3D feature etch at a variety of process conditions. Automated image segmentation of X-SEM data is also performed here for single case using Weave® to demonstrate how such data can be acquired quickly in a development environment. We then demonstrate the effectiveness of the reduced-order model to predict optimal recipe conditions to improve overall recipe performance. We show how, with this hybrid-metrology computational approach, a process window that yields 89.2% of the wafer can be captured.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126395167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qi Yan, H. Shao, Junjie Li, Z. Kong, Xiaobin He, Junfeng Li, Tao-mei Yang, Rui Chen, Yayi Wei
Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern pitch and stack layer thickness on lateral etch results have been studied by simulation.
{"title":"Study of selective isotropic etching effects of Si1-xGex in gate-all-around nanosheet transistor process","authors":"Qi Yan, H. Shao, Junjie Li, Z. Kong, Xiaobin He, Junfeng Li, Tao-mei Yang, Rui Chen, Yayi Wei","doi":"10.1117/12.2658312","DOIUrl":"https://doi.org/10.1117/12.2658312","url":null,"abstract":"Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern pitch and stack layer thickness on lateral etch results have been studied by simulation.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Shamoun, Z. Alberti, I. Bucay, S. Ellis, Michael Erickson, B. Liu, M. Chandramouli, A. Sowers, F. Abboud, G. Hochleitner, M. Tomandl, C. Klein, E. Platzgummer
The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements. EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.
{"title":"Multi-beam patterning technology and mask making beyond 5nm","authors":"B. Shamoun, Z. Alberti, I. Bucay, S. Ellis, Michael Erickson, B. Liu, M. Chandramouli, A. Sowers, F. Abboud, G. Hochleitner, M. Tomandl, C. Klein, E. Platzgummer","doi":"10.1117/12.2657746","DOIUrl":"https://doi.org/10.1117/12.2657746","url":null,"abstract":"The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements. EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132109512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shuo Huang, Premkumar Panneerchelvam, Chad M. Huard, Shyam Sridhar, P. Ventzek, Mark D. Smith
In today’s advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, ProETCH®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles.
{"title":"Process optimization for shallow trench isolation etch using computational models","authors":"Shuo Huang, Premkumar Panneerchelvam, Chad M. Huard, Shyam Sridhar, P. Ventzek, Mark D. Smith","doi":"10.1117/12.2664977","DOIUrl":"https://doi.org/10.1117/12.2664977","url":null,"abstract":"In today’s advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, ProETCH®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129447821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Hirano, Motoki Takahashi, Kuniteru Soeda, Masaki Kadowaki, Komei Hirahara, Takayuki Hosono, Jun Koshiyama, Tomoyuki Yazawa
The control of wet particles (WPs) is more stringent as the resolution of photolithography increases, especially in advanced photolithography such as extreme ultraviolet lithography (EUVL). Owing to continuing advancements in technology and resolution, it is expected that WPs smaller than the EUVL photoresist (PR) pattern sizes will need to be eliminated from silicon wafer surfaces in the near future. WPs are mainly comprised of micro/nano bubbles or organic/inorganic contaminants. The contaminants are eluted from equipment components, such as liquid filters and tubing, prior to the coating process. Flushing with conventional solvents used in photolithography eliminates WPs, however it consumes a great deal of time and solvent. TRICTM-007, a novel cleaner, was developed to remove contaminants effectively and efficiently. A PR coating equipment with a point-of-use filter installed was used for testing. Flushing with TRICTM-007 followed by a conventional solvent allowed for shorter flushing times relative to flushing with solvent alone. In addition, the amount of solvent needed to flush the equipment after using TRICTM-007 was significantly less than that of using only solvent. Furthermore, the photolithographic performance of the PR was tested by running wafer repeatability test. Tests using a filter flushed with the cleaner followed by solvent were compared to tests using a filter flushed with solvent alone. All results were similar and within specifications, proving that TRICTM- 007 did not affect the quality of the PR.
{"title":"Development of a novel cleaner for contaminant removal in equipment used in semiconductor manufacturing which reduces time and solvent waste","authors":"I. Hirano, Motoki Takahashi, Kuniteru Soeda, Masaki Kadowaki, Komei Hirahara, Takayuki Hosono, Jun Koshiyama, Tomoyuki Yazawa","doi":"10.1117/12.2656914","DOIUrl":"https://doi.org/10.1117/12.2656914","url":null,"abstract":"The control of wet particles (WPs) is more stringent as the resolution of photolithography increases, especially in advanced photolithography such as extreme ultraviolet lithography (EUVL). Owing to continuing advancements in technology and resolution, it is expected that WPs smaller than the EUVL photoresist (PR) pattern sizes will need to be eliminated from silicon wafer surfaces in the near future. WPs are mainly comprised of micro/nano bubbles or organic/inorganic contaminants. The contaminants are eluted from equipment components, such as liquid filters and tubing, prior to the coating process. Flushing with conventional solvents used in photolithography eliminates WPs, however it consumes a great deal of time and solvent. TRICTM-007, a novel cleaner, was developed to remove contaminants effectively and efficiently. A PR coating equipment with a point-of-use filter installed was used for testing. Flushing with TRICTM-007 followed by a conventional solvent allowed for shorter flushing times relative to flushing with solvent alone. In addition, the amount of solvent needed to flush the equipment after using TRICTM-007 was significantly less than that of using only solvent. Furthermore, the photolithographic performance of the PR was tested by running wafer repeatability test. Tests using a filter flushed with the cleaner followed by solvent were compared to tests using a filter flushed with solvent alone. All results were similar and within specifications, proving that TRICTM- 007 did not affect the quality of the PR.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Fuchs, James H. G. Owen, Afshin Alipour, Emma Fowler, S. Moheimani, J. N. Randall
Current lithographic techniques are limited to a resolution of a few nm with poor relative precision. Scanning Tunneling Microscope (STM) based lithography[1], removes H from H-passivated Si 2x1 (100) by a mode distinct from usual imaging. This technique is generally called Hydrogen Depassivation Lithography (HDL) and since it scans a beam of electrons around on a surface exposing a resist, it is a form of E-beam Lithography. The HDL approach is not effective with standard resists and, at present, has only a limited number of pattern transfer methods. The two primary ones are patterning 2D delta doped Si devices for solid state quantum devices and selective Atomic Layer Deposition metal oxides that can be used as hard etch masks. However, electron stimulated desorption of atoms and molecules is a fairly generic process and its use can be anticipated on a wide variety of substrates. Sub-nm resolution (0.768 nm) has been demonstrated and used for numerous research purposes, such as dopant positioning for quantum devices[2]. While sub-nm resolution is easily obtainable with standard Ultra-High Vacuum (UHV) STMs, the repeatability and accuracy of the patterning has limited its applications. In this paper we report on progress to dramatically scale HDL’s throughput while maintaining sub-nm resolution.
{"title":"Scalable digital atomic precision lithography","authors":"E. Fuchs, James H. G. Owen, Afshin Alipour, Emma Fowler, S. Moheimani, J. N. Randall","doi":"10.1117/12.2661599","DOIUrl":"https://doi.org/10.1117/12.2661599","url":null,"abstract":"Current lithographic techniques are limited to a resolution of a few nm with poor relative precision. Scanning Tunneling Microscope (STM) based lithography[1], removes H from H-passivated Si 2x1 (100) by a mode distinct from usual imaging. This technique is generally called Hydrogen Depassivation Lithography (HDL) and since it scans a beam of electrons around on a surface exposing a resist, it is a form of E-beam Lithography. The HDL approach is not effective with standard resists and, at present, has only a limited number of pattern transfer methods. The two primary ones are patterning 2D delta doped Si devices for solid state quantum devices and selective Atomic Layer Deposition metal oxides that can be used as hard etch masks. However, electron stimulated desorption of atoms and molecules is a fairly generic process and its use can be anticipated on a wide variety of substrates. Sub-nm resolution (0.768 nm) has been demonstrated and used for numerous research purposes, such as dopant positioning for quantum devices[2]. While sub-nm resolution is easily obtainable with standard Ultra-High Vacuum (UHV) STMs, the repeatability and accuracy of the patterning has limited its applications. In this paper we report on progress to dramatically scale HDL’s throughput while maintaining sub-nm resolution.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128570087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Shao, Panpan Lai, Junjie Li, G. Bai, Qi Yan, Junfeng Li, Tao-mei Yang, Rui Chen, Yayi Wei
Gate-all-around nanosheet (GAA-NS) transistors are commonly considered to be most competitive logic device in the future. In the GAA nanosheet transistor device fabrication process, the inner spacer formation is a critical step as it physically isolates the gate from the source/drain, and defines the gate length. After the selective lateral etch of the SiGe in alternative Si/SiGe stack, inner spacer material is deposited and SiNx is commonly used. This gap filling process demands for highly uniform growth of materials in order to minimize transistor variability. As moving to three-dimensional stacked structure, lateral open features bring challenges to conventional deposition manners such as chemical vapor deposition (CVD). In our previous work, we have compared the filling performance between low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), and demonstrated good SiNx growth conformity by LPCVD in Si/SiGe indentation cavities. The cavity geometry was also found to pose significant impact on growth profile. However these works were carried out on isolated Si/SiGe nanosheet structure without neighboring unit. CVD process performance may degrade when moving from isolated to dense structures, especially when the critical dimension goes into tens of nanometers. In this paper, we present our latest simulation progress on the profile evolution of SiNx CVD in dense Si/SiGe nanosheet structures with varying geometry and density of units. The SiNx profile simulation indicates that LPCVD still maintains promising coverage performance in cavities, the SiNx film thickness in the inner and outer side of unit are pretty close, while necking signature emerges near the unit top as process time increases. In contrast, PECVD exhibits pin holes within the cavity at the beginning of process, and the necking effect is relatively severe both in the cavity and near top of unit. We conduct systematic study on periodic stack structure array with different SiGe indentations. Pin holes are observed and get more pronounced in the PECVD process when the space between units is narrowed down. As the indentation decreases, pin holes become much smaller and exhibit better filling performance inside the lateral cavity.
{"title":"Modeling of SiNx growth by chemical vapor deposition in nanosheet indentation","authors":"H. Shao, Panpan Lai, Junjie Li, G. Bai, Qi Yan, Junfeng Li, Tao-mei Yang, Rui Chen, Yayi Wei","doi":"10.1117/12.2658152","DOIUrl":"https://doi.org/10.1117/12.2658152","url":null,"abstract":"Gate-all-around nanosheet (GAA-NS) transistors are commonly considered to be most competitive logic device in the future. In the GAA nanosheet transistor device fabrication process, the inner spacer formation is a critical step as it physically isolates the gate from the source/drain, and defines the gate length. After the selective lateral etch of the SiGe in alternative Si/SiGe stack, inner spacer material is deposited and SiNx is commonly used. This gap filling process demands for highly uniform growth of materials in order to minimize transistor variability. As moving to three-dimensional stacked structure, lateral open features bring challenges to conventional deposition manners such as chemical vapor deposition (CVD). In our previous work, we have compared the filling performance between low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), and demonstrated good SiNx growth conformity by LPCVD in Si/SiGe indentation cavities. The cavity geometry was also found to pose significant impact on growth profile. However these works were carried out on isolated Si/SiGe nanosheet structure without neighboring unit. CVD process performance may degrade when moving from isolated to dense structures, especially when the critical dimension goes into tens of nanometers. In this paper, we present our latest simulation progress on the profile evolution of SiNx CVD in dense Si/SiGe nanosheet structures with varying geometry and density of units. The SiNx profile simulation indicates that LPCVD still maintains promising coverage performance in cavities, the SiNx film thickness in the inner and outer side of unit are pretty close, while necking signature emerges near the unit top as process time increases. In contrast, PECVD exhibits pin holes within the cavity at the beginning of process, and the necking effect is relatively severe both in the cavity and near top of unit. We conduct systematic study on periodic stack structure array with different SiGe indentations. Pin holes are observed and get more pronounced in the PECVD process when the space between units is narrowed down. As the indentation decreases, pin holes become much smaller and exhibit better filling performance inside the lateral cavity.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122087635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Huli, Kanzo Kato, Steven Gueci, N. Antonovich, Steven Grzeskowiak, D. Hetzer, E. Liu, Alexandra Krawicz, S. Shimura, S. Kawakami, Soichiro Okada, K. Petrillo, Luciana Meli, N. Latham, Y. Cabrera, Belle Antonovich
Extreme ultraviolet lithography (EUVL) has overcome significant challenges to become an essential enabler to the logic and memory scaling roadmap. Despite its significant progress, resist photo speed, and defectivity remains the main concerns for high-volume manufacturing. To overcome these issues, high-performance EUV resist processes are needed. The high-performance resist process must simultaneously meet multiple requirements, such as a high resolution, high sensitivity, low roughness, low defect level, and good global CD uniformity (CDU). One of the high-performance resist candidates for future EUV scaling, and high NA EUV is Metal Oxide Resist (MOR). In our work, we introduce the new coater/developer hardware and new resist development techniques to improve photo speed, defectivity, and CDU without degradation of roughness in MOR. We will show that the new development methods significantly improve EUV dose to size (DtS) and micro-bridge (MB) while maintaining resist roughness performance post litho and post-etch. The new coater/developer hardware and processes are evaluated through a robust characterization methodology that includes an understanding of the defect modes at ADI (after development inspection) and AEI (after etch inspection), as well its ultimate correlation to electrical yield.
{"title":"Optimization of spin-on metal oxide resist performance via new development techniques on sub-30nm pitch patterning","authors":"L. Huli, Kanzo Kato, Steven Gueci, N. Antonovich, Steven Grzeskowiak, D. Hetzer, E. Liu, Alexandra Krawicz, S. Shimura, S. Kawakami, Soichiro Okada, K. Petrillo, Luciana Meli, N. Latham, Y. Cabrera, Belle Antonovich","doi":"10.1117/12.2658880","DOIUrl":"https://doi.org/10.1117/12.2658880","url":null,"abstract":"Extreme ultraviolet lithography (EUVL) has overcome significant challenges to become an essential enabler to the logic and memory scaling roadmap. Despite its significant progress, resist photo speed, and defectivity remains the main concerns for high-volume manufacturing. To overcome these issues, high-performance EUV resist processes are needed. The high-performance resist process must simultaneously meet multiple requirements, such as a high resolution, high sensitivity, low roughness, low defect level, and good global CD uniformity (CDU). One of the high-performance resist candidates for future EUV scaling, and high NA EUV is Metal Oxide Resist (MOR). In our work, we introduce the new coater/developer hardware and new resist development techniques to improve photo speed, defectivity, and CDU without degradation of roughness in MOR. We will show that the new development methods significantly improve EUV dose to size (DtS) and micro-bridge (MB) while maintaining resist roughness performance post litho and post-etch. The new coater/developer hardware and processes are evaluated through a robust characterization methodology that includes an understanding of the defect modes at ADI (after development inspection) and AEI (after etch inspection), as well its ultimate correlation to electrical yield.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125042804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yejin Ku, Hyungju Ahn, Jin-Kyun Lee, Jiho Kim, Byeong-Gyu Park, Sangsul Lee, Y. Jang, B. Jung, C. Koh, T. Nishi, Hyun-woo Kim
Extreme UV (EUV) lithography is entering full-scale production of high-end IC chips. This transition gives researchers in academia and industry ample motivation to propose new chemistries that will contribute to alleviating the resolution-line edge roughness-sensitivity trade-off dilemma of EUV lithography. We also have a great interest in the radical chemistry of carbon-fluorine bonds working under EUV and have explored its applicability as a platform for implementing novel EUV resists. While it was checked that the chemical concept is viable by using fluorinated small molecules and polymers, it needed to be upgraded in terms of patterning resolution and sensitivity. Recently, we extended successfully the radical-based strategy to the tin-oxo nano cluster resist concept. Soluble fluorinated tin-oxo clusters could be prepared, and they were cast into thin films from a fluorous solution. When the thin film was exposed to EUV radiation, it lost solubility, resulting in the formation of negative-tone images. Under an EUV lithographic condition, the thin film could be tailored down to 10 nm or smaller sized features. In addition, their unique solubility in chemically orthogonal solvents also enabled the build-up of a bilayer structure composed of a non-fluorinated reactive polymer underlayer without curing. The stacked film structure was found to be helpful for the sensitivity improvement. These results propose another interesting EUV resist candidate possessing unique capabilities in thin film processing.
{"title":"Fluoroalkylated tin-oxo nano clusters as resist candidates for extreme UV lithography","authors":"Yejin Ku, Hyungju Ahn, Jin-Kyun Lee, Jiho Kim, Byeong-Gyu Park, Sangsul Lee, Y. Jang, B. Jung, C. Koh, T. Nishi, Hyun-woo Kim","doi":"10.1117/12.2658210","DOIUrl":"https://doi.org/10.1117/12.2658210","url":null,"abstract":"Extreme UV (EUV) lithography is entering full-scale production of high-end IC chips. This transition gives researchers in academia and industry ample motivation to propose new chemistries that will contribute to alleviating the resolution-line edge roughness-sensitivity trade-off dilemma of EUV lithography. We also have a great interest in the radical chemistry of carbon-fluorine bonds working under EUV and have explored its applicability as a platform for implementing novel EUV resists. While it was checked that the chemical concept is viable by using fluorinated small molecules and polymers, it needed to be upgraded in terms of patterning resolution and sensitivity. Recently, we extended successfully the radical-based strategy to the tin-oxo nano cluster resist concept. Soluble fluorinated tin-oxo clusters could be prepared, and they were cast into thin films from a fluorous solution. When the thin film was exposed to EUV radiation, it lost solubility, resulting in the formation of negative-tone images. Under an EUV lithographic condition, the thin film could be tailored down to 10 nm or smaller sized features. In addition, their unique solubility in chemically orthogonal solvents also enabled the build-up of a bilayer structure composed of a non-fluorinated reactive polymer underlayer without curing. The stacked film structure was found to be helpful for the sensitivity improvement. These results propose another interesting EUV resist candidate possessing unique capabilities in thin film processing.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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