The improvement of accuracy and efficiency in simulating the profile of the chemically amplified resist (CAR) is always a key point in lithography. With the development of machine learning, many models have been successfully applied in optical proximity correction (OPC), hotspot detection, and other lithographic fields. In this work, we developed a neural network for predicting the critical features’ sizes of the CAR profile. By using a pre-calibrated physical resist model, the effectiveness of this model is demonstrated from numerical simulation. The results indicate that for the critical dimensions (CDs) of the CAR profile, this model shows great speed and accuracy. After applying the tuned neural network on the test sets, it shows 92.98% of the test sets have a mean square error (MSE) less than 1%.
{"title":"Predicting the critical features of the chemically-amplified resist profile based on machine learning","authors":"Pengjie Kong, Lisong Dong, Xu Ma, Yayi Wei","doi":"10.1117/12.2658664","DOIUrl":"https://doi.org/10.1117/12.2658664","url":null,"abstract":"The improvement of accuracy and efficiency in simulating the profile of the chemically amplified resist (CAR) is always a key point in lithography. With the development of machine learning, many models have been successfully applied in optical proximity correction (OPC), hotspot detection, and other lithographic fields. In this work, we developed a neural network for predicting the critical features’ sizes of the CAR profile. By using a pre-calibrated physical resist model, the effectiveness of this model is demonstrated from numerical simulation. The results indicate that for the critical dimensions (CDs) of the CAR profile, this model shows great speed and accuracy. After applying the tuned neural network on the test sets, it shows 92.98% of the test sets have a mean square error (MSE) less than 1%.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Servin, Alexandre Téolis, A. Bazin, A. Sarrazin, Paule Durin, O. Sysova, Corinne Gablin, Benoît Saudet, D. Léonard, O. Soppera, J. Leclercq, Y. Chevolot, R. Tiron, T. Delair, S. Trombotto
DUV photolithography, as the major process of nanofabrication, typically requires high volumes of toxic chemicals within resist formulation, solvent and developer. In this context, alternative chemistries to current petroleum-derived photoresists are proposed to reduce environmental impacts. Chitosan represents a bio-sourced resist allowing water-based patterning processes free of organic solvent and alkali-based developers, by substitution with a green solvent (deionized (DI) water). This paper present last stepwise process in the patterning integration with a chitosan-based resist. Preliminary results using a 300 mm pilot line scale at CEA-Leti demonstrate patterns resolution down to 800 nm along with plasma etch transfer into Si substrate. Finally, the environmental impact through life cycle analysis (LCA) of the whole process based on chitosan resist is assessed and compared to conventional solvent-based processes.
{"title":"Chitosan as a water-based photoresist for DUV lithography","authors":"I. Servin, Alexandre Téolis, A. Bazin, A. Sarrazin, Paule Durin, O. Sysova, Corinne Gablin, Benoît Saudet, D. Léonard, O. Soppera, J. Leclercq, Y. Chevolot, R. Tiron, T. Delair, S. Trombotto","doi":"10.1117/12.2658423","DOIUrl":"https://doi.org/10.1117/12.2658423","url":null,"abstract":"DUV photolithography, as the major process of nanofabrication, typically requires high volumes of toxic chemicals within resist formulation, solvent and developer. In this context, alternative chemistries to current petroleum-derived photoresists are proposed to reduce environmental impacts. Chitosan represents a bio-sourced resist allowing water-based patterning processes free of organic solvent and alkali-based developers, by substitution with a green solvent (deionized (DI) water). This paper present last stepwise process in the patterning integration with a chitosan-based resist. Preliminary results using a 300 mm pilot line scale at CEA-Leti demonstrate patterns resolution down to 800 nm along with plasma etch transfer into Si substrate. Finally, the environmental impact through life cycle analysis (LCA) of the whole process based on chitosan resist is assessed and compared to conventional solvent-based processes.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126249500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. Nguyen, B. Chan, F. Lazzarino
In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.
{"title":"Challenges for spacer and source/drain cavity patterning in CFET devices","authors":"G. Mannaert, H. Mertens, M. Hosseini, S. Demuynck, V. Nguyen, B. Chan, F. Lazzarino","doi":"10.1117/12.2658073","DOIUrl":"https://doi.org/10.1117/12.2658073","url":null,"abstract":"In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128130473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-optics are in great demand and indispensable key enabling elements in various emerging markets. High quality wafer-level micro-optics attract huge commercial interest in prestigious applications like 3D sensing and imaging for AR/VR in smart devices and automotive lighting [1]. The consumers aspire to have comprehensive functionalities on their smart gadgets, to enhance their view of the real environment by superimposing a virtual world. 3D sensing cameras with Time-of-Flight (ToF) modules provide a revolutionary virtual reality and imaging. A typical ToF module demands various highly efficient nano and micro-optical elements [2,3]. The next generation imprint equipment provided by SUSS MicroTec offers a versatile and sophisticated imprint mechanism to resolve complex microscale structures on a single imprint equipment. The advanced technical features include enhanced imprint gap measurement and a levelling mechanism, tunable forces during imprint, advanced design of microscopes for high alignment accuracy and cost-effective UV-LED flood exposure with high intensities. These comprehensive functionalities also make it possible to manufacture larger sets of stacked micro lens arrays with low aberration and minimal distortion of lens geometry. In this talk, we will present the capabilities of SUSS equipment for imprinting micro lens arrays (MLA) with alignment accuracy ≤ 1μm and less geometry variation < 1 %, over a 200 mm wafer surface. Moreover, in a high volume manufacturing environment, key to productivity are consistent and repeatable fabrication processes and operations. Therefore, we will also show the reliability of our equipment and the repeatability of producing high quality MLAs.
{"title":"Next generation imprint equipment for patterning high quality micro-optical elements","authors":"V. Kolli, F. Kloiber, S. Drieschner","doi":"10.1117/12.2657936","DOIUrl":"https://doi.org/10.1117/12.2657936","url":null,"abstract":"Micro-optics are in great demand and indispensable key enabling elements in various emerging markets. High quality wafer-level micro-optics attract huge commercial interest in prestigious applications like 3D sensing and imaging for AR/VR in smart devices and automotive lighting [1]. The consumers aspire to have comprehensive functionalities on their smart gadgets, to enhance their view of the real environment by superimposing a virtual world. 3D sensing cameras with Time-of-Flight (ToF) modules provide a revolutionary virtual reality and imaging. A typical ToF module demands various highly efficient nano and micro-optical elements [2,3]. The next generation imprint equipment provided by SUSS MicroTec offers a versatile and sophisticated imprint mechanism to resolve complex microscale structures on a single imprint equipment. The advanced technical features include enhanced imprint gap measurement and a levelling mechanism, tunable forces during imprint, advanced design of microscopes for high alignment accuracy and cost-effective UV-LED flood exposure with high intensities. These comprehensive functionalities also make it possible to manufacture larger sets of stacked micro lens arrays with low aberration and minimal distortion of lens geometry. In this talk, we will present the capabilities of SUSS equipment for imprinting micro lens arrays (MLA) with alignment accuracy ≤ 1μm and less geometry variation < 1 %, over a 200 mm wafer surface. Moreover, in a high volume manufacturing environment, key to productivity are consistent and repeatable fabrication processes and operations. Therefore, we will also show the reliability of our equipment and the repeatability of producing high quality MLAs.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134395890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Si Li, Joyce A. Lowes, Ruimeng Zhang, M. Luo, Kelsey E. Brakensiek, V. V. Driessche, D. Guerrero
In EUV lithography, good resist patterning requires an assist layer beneath it to provide adhesion to prevent pattern collapse of small features and allow for higher aspect ratios. In addition, future EUV high numerical aperture (NA) is expected to require a decrease in thickness from the overall patterning stack. In this study, we are exploring a fundamentally new approach to developing an alternative and cost-effective underlayer to functionalize surfaces and enable EUV patterning. Rather than forming a 5-nm polymer film between the resist and its substrate, we propose to modify the substrate by spin-coating a thinner layer. In contrast to conventional underlayers (5–10 nm), the substrate is modified by a sub-1-nm layer during baking. Comprehensive analysis of the surface modification and coating was conducted by GPC, ellipsometer, and contact angle to identify the structure, stability, coating quality, and surface energy. Lithographic performance of existing EUV resist with the assist of this thin layer on Si wafers and different silicon hardmasks was evaluated using NXE3400 EUV exposure system to print HP14nm line-space features. It has been demonstrated that this sub-1-nm layer is able to realize HP14nm with a wider process window, higher depth of focus, and lower LWR on a Si wafer. Moreover, a silicon hardmask that could not realize printable features had significantly improved lithographic performance with the assist of this layer. Comparisons were also made with the industry-standard HMDS priming. Systematic analysis indicates that a sub-1-nm layer exemplifies a novel and effective way to enhance photoresist-substrate compatibility and improve EUV lithographic performance.
{"title":"Novel assist layers to enhance EUV lithography performance of photoresists on different substrates","authors":"Si Li, Joyce A. Lowes, Ruimeng Zhang, M. Luo, Kelsey E. Brakensiek, V. V. Driessche, D. Guerrero","doi":"10.1117/12.2658529","DOIUrl":"https://doi.org/10.1117/12.2658529","url":null,"abstract":"In EUV lithography, good resist patterning requires an assist layer beneath it to provide adhesion to prevent pattern collapse of small features and allow for higher aspect ratios. In addition, future EUV high numerical aperture (NA) is expected to require a decrease in thickness from the overall patterning stack. In this study, we are exploring a fundamentally new approach to developing an alternative and cost-effective underlayer to functionalize surfaces and enable EUV patterning. Rather than forming a 5-nm polymer film between the resist and its substrate, we propose to modify the substrate by spin-coating a thinner layer. In contrast to conventional underlayers (5–10 nm), the substrate is modified by a sub-1-nm layer during baking. Comprehensive analysis of the surface modification and coating was conducted by GPC, ellipsometer, and contact angle to identify the structure, stability, coating quality, and surface energy. Lithographic performance of existing EUV resist with the assist of this thin layer on Si wafers and different silicon hardmasks was evaluated using NXE3400 EUV exposure system to print HP14nm line-space features. It has been demonstrated that this sub-1-nm layer is able to realize HP14nm with a wider process window, higher depth of focus, and lower LWR on a Si wafer. Moreover, a silicon hardmask that could not realize printable features had significantly improved lithographic performance with the assist of this layer. Comparisons were also made with the industry-standard HMDS priming. Systematic analysis indicates that a sub-1-nm layer exemplifies a novel and effective way to enhance photoresist-substrate compatibility and improve EUV lithographic performance.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126036485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seungjin Mun, Lina Yoo, Jongdeok Hong, J. Ahn, Kyung-yub Jeon, Ke Bai
As device scale down to sub 3nm, NMOS/PMOS boundary patterning becomes critical in logic product. This patterning requires highly directional etching while maintaining high selectivity to the base metal layer. In this paper, we demonstrated that the ion energy has the trade-off between the profile verticality and the surface damage. The ion energy was strongly controlled by the bias voltage and surface damage was improved with lower bias voltage, but profile verticality was deteriorated because of the ion angle dispersion. To enhance the profile verticality the carbon rich gas was added as the top passivation. The proposed method will be a practical in sub-3nm logic boundary patterning.
{"title":"The damage control of sub layer while ion-driven etching with vertical carbon profile implemented","authors":"Seungjin Mun, Lina Yoo, Jongdeok Hong, J. Ahn, Kyung-yub Jeon, Ke Bai","doi":"10.1117/12.2657249","DOIUrl":"https://doi.org/10.1117/12.2657249","url":null,"abstract":"As device scale down to sub 3nm, NMOS/PMOS boundary patterning becomes critical in logic product. This patterning requires highly directional etching while maintaining high selectivity to the base metal layer. In this paper, we demonstrated that the ion energy has the trade-off between the profile verticality and the surface damage. The ion energy was strongly controlled by the bias voltage and surface damage was improved with lower bias voltage, but profile verticality was deteriorated because of the ion angle dispersion. To enhance the profile verticality the carbon rich gas was added as the top passivation. The proposed method will be a practical in sub-3nm logic boundary patterning.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114448108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Galleni, Faegheh S. Sajjadian, T. Conard, I. Pollentier, K. Dorney, F. Holzmeier, E. Larsen, Daniel Escudero, G. Pourtois, M. V. van Setten, Paul A. W. van der Heide, J. Petersen
Science stands on three legs: hypothesis, experiment, and simulation. This holds true for researching extreme ultraviolet (EUV) exposure of photoresist. Hypothesis: For resist exposure as patterns get smaller and closer together, approaching molecular units in width and resist-height, the molecular dynamics will limit the working resolution of the resist due to the formation of printing defects. Without taking proper consideration of these dynamics, the single-patterning lithography roadmap may end prematurely. Experimentally we are developing methods for sub-picosecond tracking of photoionization-induced processes. Using ultrashort pulses of light to excite and probe new materials with techniques that show the interactive dynamics of electronic and nuclear motion at the very limits of light-speed. This certainly holds true for exposing photoresists with EUV where ultrafast photoreactions induce chemical change via multiple pathways such as high-energy ionization fragmentation, recombination, and multispecies combination that ideally end in low-energy electron transfer reactions, analogous to lower energy photoreaction (but with a charge). In the nonideal case, these reaction processes lead to incompatible byproducts of the radiolysis that lead to types of stochastic defects. To do ultrafast studies we must build a foundation of knowledge using atomistic simulation to interpret transient molecular dynamic processes. Before we can do this, we need to learn how to simulate various spectral modalities to provide a starting point. In this work, we examine X-ray Photoelectron Spectroscopy of a model resist and use atomistic simulation to interpret the reactant-product composition of the spectral samples.
{"title":"A scientific framework for establishing ultrafast molecular dynamic research in imec’s AttoLab","authors":"L. Galleni, Faegheh S. Sajjadian, T. Conard, I. Pollentier, K. Dorney, F. Holzmeier, E. Larsen, Daniel Escudero, G. Pourtois, M. V. van Setten, Paul A. W. van der Heide, J. Petersen","doi":"10.1117/12.2660047","DOIUrl":"https://doi.org/10.1117/12.2660047","url":null,"abstract":"Science stands on three legs: hypothesis, experiment, and simulation. This holds true for researching extreme ultraviolet (EUV) exposure of photoresist. Hypothesis: For resist exposure as patterns get smaller and closer together, approaching molecular units in width and resist-height, the molecular dynamics will limit the working resolution of the resist due to the formation of printing defects. Without taking proper consideration of these dynamics, the single-patterning lithography roadmap may end prematurely. Experimentally we are developing methods for sub-picosecond tracking of photoionization-induced processes. Using ultrashort pulses of light to excite and probe new materials with techniques that show the interactive dynamics of electronic and nuclear motion at the very limits of light-speed. This certainly holds true for exposing photoresists with EUV where ultrafast photoreactions induce chemical change via multiple pathways such as high-energy ionization fragmentation, recombination, and multispecies combination that ideally end in low-energy electron transfer reactions, analogous to lower energy photoreaction (but with a charge). In the nonideal case, these reaction processes lead to incompatible byproducts of the radiolysis that lead to types of stochastic defects. To do ultrafast studies we must build a foundation of knowledge using atomistic simulation to interpret transient molecular dynamic processes. Before we can do this, we need to learn how to simulate various spectral modalities to provide a starting point. In this work, we examine X-ray Photoelectron Spectroscopy of a model resist and use atomistic simulation to interpret the reactant-product composition of the spectral samples.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121006220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yinjie Cen, Choong-Sun Lee, Li Cui, S. Coley, J. Park, Benjamin D. Naab-Rafael, E. Aqad, Rochelle Rena, Tyler R Paul, Thomas Penniman, Jason Behnke, Julia T Early, Benjamin Foltz
Chemically amplified resist (CAR) materials are widely used in advanced node patterning by extreme ultraviolet lithography (EUVL). To support the continuous requirement of reducing critical dimension (CD), CAR has been designed to process at tens of nanometer coating thickness while taking into consideration film roughness, aspect ratio, and etch transfer challenge. In this study, we investigated the impact of the photoresist’s different spin speed for same film thickness on resolution, line width roughness, and sensitivity (RLS) trade-off for Line and Space (L/S) patterns. We selected photoresists with identical chemical composition that differed only in total wt solid% in the solution. Photoresist films at constant thickness were investigated for the spin speed impacts on photoresist film density, hydrophobicity on the film surface, and film surface roughness. The corresponding EUV lithographic performance will be presented.
{"title":"Spin speed impact on photoresist thin film properties and EUV lithographic performance","authors":"Yinjie Cen, Choong-Sun Lee, Li Cui, S. Coley, J. Park, Benjamin D. Naab-Rafael, E. Aqad, Rochelle Rena, Tyler R Paul, Thomas Penniman, Jason Behnke, Julia T Early, Benjamin Foltz","doi":"10.1117/12.2659101","DOIUrl":"https://doi.org/10.1117/12.2659101","url":null,"abstract":"Chemically amplified resist (CAR) materials are widely used in advanced node patterning by extreme ultraviolet lithography (EUVL). To support the continuous requirement of reducing critical dimension (CD), CAR has been designed to process at tens of nanometer coating thickness while taking into consideration film roughness, aspect ratio, and etch transfer challenge. In this study, we investigated the impact of the photoresist’s different spin speed for same film thickness on resolution, line width roughness, and sensitivity (RLS) trade-off for Line and Space (L/S) patterns. We selected photoresists with identical chemical composition that differed only in total wt solid% in the solution. Photoresist films at constant thickness were investigated for the spin speed impacts on photoresist film density, hydrophobicity on the film surface, and film surface roughness. The corresponding EUV lithographic performance will be presented.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128045736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Takeuchi, Genna Hasegawa, T. Komukai, T. Iwasaki, M. Hatano, M. Komori, T. Kono
Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained.
{"title":"Fabrication of dual damascene structure with nanoimprint lithography and dry-etching","authors":"N. Takeuchi, Genna Hasegawa, T. Komukai, T. Iwasaki, M. Hatano, M. Komori, T. Kono","doi":"10.1117/12.2657912","DOIUrl":"https://doi.org/10.1117/12.2657912","url":null,"abstract":"Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128124159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeeyong Lee, Yangwoo Heo, Ryanggeun Lee, Sangwook Kim, Jisuk Hong, K. Koo, Chang-Yeol Yim, Jungmin Kim, Sooyong Lee, Joonsung Kim, Dongho Kim, Seung-Hune Yang, Seongtae Jeong
Patterning, a major process in semiconductor manufacturing, aims to transfer the design layout to the wafer. Accordingly, the "process proximity correction" method was developed to overcome the difference in after-cleaninginspected CD (critical dimension) between patterns of similar shapes. However, its physical model is often limited in the predictive performance. Therefore, recent studies have introduced ML (machine learning) technology to supplement model accuracy, but this approach often has an inherent risk of overfitting depending on the type of sampled pattern. In this study, we present a newly invented flow capable of stable etch-process-aware ML modeling by model reconstruction and large amounts of measurement data. The new modeling flow can also be performed within a reasonable runtime through efficient feature extraction. Based on the new model and its related layout targeting platform, intensive improvements were made to CD targeting and spread; for a given layout, in comparison with delicate rule-based modification, the CD targeting accuracy was improved by 4 times and approaches the limit of metrology error.
{"title":"A novel approach to etch-process-aware intensive layout retarget","authors":"Jeeyong Lee, Yangwoo Heo, Ryanggeun Lee, Sangwook Kim, Jisuk Hong, K. Koo, Chang-Yeol Yim, Jungmin Kim, Sooyong Lee, Joonsung Kim, Dongho Kim, Seung-Hune Yang, Seongtae Jeong","doi":"10.1117/12.2657880","DOIUrl":"https://doi.org/10.1117/12.2657880","url":null,"abstract":"Patterning, a major process in semiconductor manufacturing, aims to transfer the design layout to the wafer. Accordingly, the \"process proximity correction\" method was developed to overcome the difference in after-cleaninginspected CD (critical dimension) between patterns of similar shapes. However, its physical model is often limited in the predictive performance. Therefore, recent studies have introduced ML (machine learning) technology to supplement model accuracy, but this approach often has an inherent risk of overfitting depending on the type of sampled pattern. In this study, we present a newly invented flow capable of stable etch-process-aware ML modeling by model reconstruction and large amounts of measurement data. The new modeling flow can also be performed within a reasonable runtime through efficient feature extraction. Based on the new model and its related layout targeting platform, intensive improvements were made to CD targeting and spread; for a given layout, in comparison with delicate rule-based modification, the CD targeting accuracy was improved by 4 times and approaches the limit of metrology error.","PeriodicalId":212235,"journal":{"name":"Advanced Lithography","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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