Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609586
R. Degraeve
Summary form only given. Hard breakdown, analog and digital soft breakdown, micro breakdown, progressive breakdown, stress-induced leakage current, anomalous stress-induced leakage current, etc. When a constant voltage stress is applied to a thin (<10 nm) oxide layer many degradation phenomena are observed. All of these have in common that they are localized stress-induced leakage paths involving electrical trap centers in the bulk of the oxide, but different names are in use depending on the magnitude of the leakage current or on the application where they are typically measured. Some of these stress-induced leakage paths can be negligible artifacts for one application while they are showstoppers for another application. This tutorial aims at presenting a comprehensive overview of all these dielectric breakdown phenomena, explaining their origin and showing what test methods and structures are needed to observe and study them. Examples are presented on SiO/sub 2/, SiON and some high-k dielectrics.
{"title":"From micro breakdown to hard breakdown - from artifact to destructive failure?","authors":"R. Degraeve","doi":"10.1109/IRWS.2005.1609586","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609586","url":null,"abstract":"Summary form only given. Hard breakdown, analog and digital soft breakdown, micro breakdown, progressive breakdown, stress-induced leakage current, anomalous stress-induced leakage current, etc. When a constant voltage stress is applied to a thin (<10 nm) oxide layer many degradation phenomena are observed. All of these have in common that they are localized stress-induced leakage paths involving electrical trap centers in the bulk of the oxide, but different names are in use depending on the magnitude of the leakage current or on the application where they are typically measured. Some of these stress-induced leakage paths can be negligible artifacts for one application while they are showstoppers for another application. This tutorial aims at presenting a comprehensive overview of all these dielectric breakdown phenomena, explaining their origin and showing what test methods and structures are needed to observe and study them. Examples are presented on SiO/sub 2/, SiON and some high-k dielectrics.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128873738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609562
T. Di Gilio, A. Bravaix
In this paper, we show that the effect of hot hole injections in ultra-thin oxide P-MOSFETs, is merged into the hole tunneling through the gate oxide. Thus, extrapolated lifetime techniques have to take into account both mechanisms. Even if quantitative distinction is difficult, we propose a first attempt to distinguish both contributions. This modelling allows to separate both mechanism consequences in relation to the extension of drain space charge region /spl Delta/L.
{"title":"Lifetime prediction of ultra-thin gate oxide PMOSFETs submitted to hot hole injections","authors":"T. Di Gilio, A. Bravaix","doi":"10.1109/IRWS.2005.1609562","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609562","url":null,"abstract":"In this paper, we show that the effect of hot hole injections in ultra-thin oxide P-MOSFETs, is merged into the hole tunneling through the gate oxide. Thus, extrapolated lifetime techniques have to take into account both mechanisms. Even if quantitative distinction is difficult, we propose a first attempt to distinguish both contributions. This modelling allows to separate both mechanism consequences in relation to the extension of drain space charge region /spl Delta/L.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122511262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609572
R. Vollertsen, H. Nielen
Efficient, quantitative inline monitoring of reliability parameters requires considering various dependencies and influences. This work deals with monitoring of conducting hot carrier degradation - but works for other device stress types as well - and develops a single but comprehensive parameter for a control card, that takes into account the device length variation, deviation from a reference device (e.g. the nominal device) and deviation from device reliability model as determined during the process qualification. The derivation and implementation of the method and parameter is described in detail. Alternative parameter calculations are discussed. Examples are given to illustrate the feasibility and usability of the simple and comprehensive parameter
{"title":"Efficient fWLR inline monitoring of hot carrier reliability by means of one simple, comprehensive parameter","authors":"R. Vollertsen, H. Nielen","doi":"10.1109/IRWS.2005.1609572","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609572","url":null,"abstract":"Efficient, quantitative inline monitoring of reliability parameters requires considering various dependencies and influences. This work deals with monitoring of conducting hot carrier degradation - but works for other device stress types as well - and develops a single but comprehensive parameter for a control card, that takes into account the device length variation, deviation from a reference device (e.g. the nominal device) and deviation from device reliability model as determined during the process qualification. The derivation and implementation of the method and parameter is described in detail. Alternative parameter calculations are discussed. Examples are given to illustrate the feasibility and usability of the simple and comprehensive parameter","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"15 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120935596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609579
S.Y. Chen, J.C. Lin, H.W. Chen, Z. Jhou, H. Lin, S. Chou, J. Ko, T. Lei, H. Haung
In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature
{"title":"An investigation on substrate current and hot carrier degradation at elevated temperatures for nMOSFETs of 0.13 /spl mu/m technology","authors":"S.Y. Chen, J.C. Lin, H.W. Chen, Z. Jhou, H. Lin, S. Chou, J. Ko, T. Lei, H. Haung","doi":"10.1109/IRWS.2005.1609579","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609579","url":null,"abstract":"In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609588
L. Stout
Summary form only given. This tutorial provides practical information on two techniques that are of use to anyone doing statistical data analysis and making statistical inferences. Reliability engineers often base their decisions on fitting lifetime data to a particular type of distribution (e.g. lognormal, exponential, Weibull). Statistical bootstrapping is a tool that allows us to explore data and make useful inferences (e.g. mean, confidence intervals) about it without the need for assuming that the data is from a particular underlying distribution. Bootstrapping was introduced in the late 1970's and is a computationally intensive Monte-Carlo procedure that is simple to understand and implement. To bootstrap a statistic (e.g. the sample mean), we draw for example 1000 random resamples with replacement from the original sample data, calculate the statistic of interest (sample mean) for each resample, then estimate the overall sample mean by taking the average of all the 1000 resampled means. Inferences about our statistic can then be made by inspecting the resulting bootstrap distribution of our 1000 resampled values of the statistic of interest. The key idea here is that the bootstrap distribution approximates the sampling distribution of the statistic and we use it as a way to estimate the variation in a statistic based on the original data. The second topic of discussion in this tutorial was an introduction to extreme value statistics. Extreme values statistics have proven useful in ocean engineering (e.g. highest wave height), meteorology (highest amount of rainfall, maximum wind speed), and in investigating fatigue strength and corrosion. Here the focus was on the extremes of a measured parameter instead of the typical focus on centralized tendencies such as the mean or median. I believe that they could also prove useful in exploring electrical reliability issues such as the highest (lowest) use temperature for a metal line, maximum use current flow through a specific device, or the highest use voltage across a capacitor.
{"title":"Reliability engineering tools: bootstrapping and extreme value statistics","authors":"L. Stout","doi":"10.1109/IRWS.2005.1609588","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609588","url":null,"abstract":"Summary form only given. This tutorial provides practical information on two techniques that are of use to anyone doing statistical data analysis and making statistical inferences. Reliability engineers often base their decisions on fitting lifetime data to a particular type of distribution (e.g. lognormal, exponential, Weibull). Statistical bootstrapping is a tool that allows us to explore data and make useful inferences (e.g. mean, confidence intervals) about it without the need for assuming that the data is from a particular underlying distribution. Bootstrapping was introduced in the late 1970's and is a computationally intensive Monte-Carlo procedure that is simple to understand and implement. To bootstrap a statistic (e.g. the sample mean), we draw for example 1000 random resamples with replacement from the original sample data, calculate the statistic of interest (sample mean) for each resample, then estimate the overall sample mean by taking the average of all the 1000 resampled means. Inferences about our statistic can then be made by inspecting the resulting bootstrap distribution of our 1000 resampled values of the statistic of interest. The key idea here is that the bootstrap distribution approximates the sampling distribution of the statistic and we use it as a way to estimate the variation in a statistic based on the original data. The second topic of discussion in this tutorial was an introduction to extreme value statistics. Extreme values statistics have proven useful in ocean engineering (e.g. highest wave height), meteorology (highest amount of rainfall, maximum wind speed), and in investigating fatigue strength and corrosion. Here the focus was on the extremes of a measured parameter instead of the typical focus on centralized tendencies such as the mean or median. I believe that they could also prove useful in exploring electrical reliability issues such as the highest (lowest) use temperature for a metal line, maximum use current flow through a specific device, or the highest use voltage across a capacitor.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124390266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609556
D. Ney, X. Federspiel, V. Girault, O. Thomas, P. Gergaud
The electromigration threshold in copper interconnect is reported in this study. The critical product jLc was first determined for copper-oxide interconnects in the temperature range 250/spl deg/C-350/spl deg/C from package level experiments. It is shown that the product does not significantly change in this temperature range. Then jLc was extracted for copper-low k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than for oxide dielectric was found. Finally, a correlation between n values from Black's model and jL conditions was established for both dielectrics.
{"title":"Blech effect in dual damascene copper-low k interconnects","authors":"D. Ney, X. Federspiel, V. Girault, O. Thomas, P. Gergaud","doi":"10.1109/IRWS.2005.1609556","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609556","url":null,"abstract":"The electromigration threshold in copper interconnect is reported in this study. The critical product jLc was first determined for copper-oxide interconnects in the temperature range 250/spl deg/C-350/spl deg/C from package level experiments. It is shown that the product does not significantly change in this temperature range. Then jLc was extracted for copper-low k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than for oxide dielectric was found. Finally, a correlation between n values from Black's model and jL conditions was established for both dielectrics.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123158759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609575
J.C. Lin, S.Y. Chen, H.W. Chen, H. Lin, Z. Jhou, S. Chou, J. Ko, T. Lei, H. Haung
In this report, hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.15 /spl mu/m CMOS technology is presented for the first time. The research reveals that HCI does degrade matching of nMOSFETs' properties, but, for pMOSFETs, the changes are minor. Due to matching variation after HCI stress, for analog circuits' parameters, it is found that the after stress lines of n and pMOSFETs exhibit cross points for both /spl sigma/ (/spl square/ V/sub t,op/) and /spl sigma/ (/spl square/I/sub ds,op//I/sub ds,op/) drawings. It is suggested that the cross points can be used to indicate the minimal size for n and p pairs to have the same degree of mismatch in designing analog circuits. In addition, the interpretations for the differences in n to pMOSFETs and I/sub ds,op/ to I/sub ds,sat/ mismatches are provided with experimental verifications.
{"title":"Matching variation after HCI stress in advanced CMOS technology for analog applications","authors":"J.C. Lin, S.Y. Chen, H.W. Chen, H. Lin, Z. Jhou, S. Chou, J. Ko, T. Lei, H. Haung","doi":"10.1109/IRWS.2005.1609575","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609575","url":null,"abstract":"In this report, hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.15 /spl mu/m CMOS technology is presented for the first time. The research reveals that HCI does degrade matching of nMOSFETs' properties, but, for pMOSFETs, the changes are minor. Due to matching variation after HCI stress, for analog circuits' parameters, it is found that the after stress lines of n and pMOSFETs exhibit cross points for both /spl sigma/ (/spl square/ V/sub t,op/) and /spl sigma/ (/spl square/I/sub ds,op//I/sub ds,op/) drawings. It is suggested that the cross points can be used to indicate the minimal size for n and p pairs to have the same degree of mismatch in designing analog circuits. In addition, the interpretations for the differences in n to pMOSFETs and I/sub ds,op/ to I/sub ds,sat/ mismatches are provided with experimental verifications.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609571
E. Bouyssou, S. Bruyère, G. Guégan, C. Anceau, R. Jérisian
Wafer level reliability is a key tool for the development of new technologies, since it enables to anticipate the lifetime of these technologies in operating conditions. In this paper, we present a testing methodology for lifetime extrapolation of high density PZT capacitors. This study is related to a basic time-dependent dielectric breakdown characterization, from which we could identify several failure mechanisms, depending on the applied voltage stress level. The proposed testing methodology, based on cumulated voltage and temperature accelerations, enables to emulate only the relevant failure mechanism for lifetime extrapolation. Assuming an E model for voltage extrapolation and a top electrode perimeter scaling for geometry dependency, we finally developed a complete reliability model that takes into account the temperature, voltage and geometry influences on capacitors lifetime.
{"title":"Testing methodology for lifetime extrapolation of PZT capacitors","authors":"E. Bouyssou, S. Bruyère, G. Guégan, C. Anceau, R. Jérisian","doi":"10.1109/IRWS.2005.1609571","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609571","url":null,"abstract":"Wafer level reliability is a key tool for the development of new technologies, since it enables to anticipate the lifetime of these technologies in operating conditions. In this paper, we present a testing methodology for lifetime extrapolation of high density PZT capacitors. This study is related to a basic time-dependent dielectric breakdown characterization, from which we could identify several failure mechanisms, depending on the applied voltage stress level. The proposed testing methodology, based on cumulated voltage and temperature accelerations, enables to emulate only the relevant failure mechanism for lifetime extrapolation. Assuming an E model for voltage extrapolation and a top electrode perimeter scaling for geometry dependency, we finally developed a complete reliability model that takes into account the temperature, voltage and geometry influences on capacitors lifetime.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609557
P. Sun, E. Bei, Y.W. Chen, T. Hu, F. Ji, C. Liao, V. Ruan, A. Tsai, D.L. Wang, S. Wu, G. Zhang, A. Fan, I. Chen
As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of copper and low k dielectrics become obvious. The integration of copper interconnects and low k dielectrics generates new failure modes and reliability issues. Once the numerous chip-level copper/low k integration problems are worked through, the greatest challenges lie in obtaining production-worthy, high yielding devices that can be packaged and pass standard reliability tests. This work investigates different integrated solutions to solve a packaging problem we encountered. By carefully managing stress, optimizing film stack and packaging condition, an integrated solution has been found and implemented with good yield, manufacturability, reliability and packaging performance.
{"title":"An integrated solution with a novel bi-layer etch stop to eliminate 90 nm Cu/low k package fail","authors":"P. Sun, E. Bei, Y.W. Chen, T. Hu, F. Ji, C. Liao, V. Ruan, A. Tsai, D.L. Wang, S. Wu, G. Zhang, A. Fan, I. Chen","doi":"10.1109/IRWS.2005.1609557","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609557","url":null,"abstract":"As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of copper and low k dielectrics become obvious. The integration of copper interconnects and low k dielectrics generates new failure modes and reliability issues. Once the numerous chip-level copper/low k integration problems are worked through, the greatest challenges lie in obtaining production-worthy, high yielding devices that can be packaged and pass standard reliability tests. This work investigates different integrated solutions to solve a packaging problem we encountered. By carefully managing stress, optimizing film stack and packaging condition, an integrated solution has been found and implemented with good yield, manufacturability, reliability and packaging performance.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114192757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609563
M. Ruat, R. Angers, G. Ghibaudo, N. Revil, G. Pananakakis
This work shows and discusses the occurrence of a new failure mechanism affecting both collector and base currents under reverse BE junction stress. This is evident for very advanced SiGe and SiGe:C HBTs. This failure mode only affects the first steps of the degradation, exhibiting a correlated decrease of both base and collector currents, while keeping their ideality. Several experiments and analyses have been conducted for better understanding of this failure mode
{"title":"A new degradation mode for advanced heterojunction bipolar transistors under reverse bias stress","authors":"M. Ruat, R. Angers, G. Ghibaudo, N. Revil, G. Pananakakis","doi":"10.1109/IRWS.2005.1609563","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609563","url":null,"abstract":"This work shows and discusses the occurrence of a new failure mechanism affecting both collector and base currents under reverse BE junction stress. This is evident for very advanced SiGe and SiGe:C HBTs. This failure mode only affects the first steps of the degradation, exhibiting a correlated decrease of both base and collector currents, while keeping their ideality. Several experiments and analyses have been conducted for better understanding of this failure mode","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"30 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129118469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：