Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609564
M. Ogas, P. Price, J. Kiepert, R. J. Baker, G. Bersuker, W. B. Knowlton
CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.
{"title":"Degradation of rise time in NAND gates using 2.0 nm gate dielectrics","authors":"M. Ogas, P. Price, J. Kiepert, R. J. Baker, G. Bersuker, W. B. Knowlton","doi":"10.1109/IRWS.2005.1609564","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609564","url":null,"abstract":"CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128455570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609559
J. Lloyd, T. Shaw, E. Liniger
In a study of the TDDB performance of an ultra-low-k (ULK) dielectric (JSR 5537 k = 2.3) it was found that the presence of moisture significantly reduced the TDDB lifetime as well as increased leakage and capacitance. It was also observed that the field coefficient (/spl gamma/) in an "E" TDDB lifetime model was significantly larger in "dry" samples than in "wet" samples.
在对超低k (ULK)电介质(JSR 5537 k = 2.3)的TDDB性能的研究中发现，水分的存在显著降低了TDDB的寿命，并增加了泄漏和电容。还观察到，在“E”TDDB寿命模型中，“干”样品的场系数(/spl gamma/)明显大于“湿”样品。
{"title":"Effect of moisture on the time dependent dielectric breakdown (TDDB) behavior in an ultra-low-k (ULK) dielectric","authors":"J. Lloyd, T. Shaw, E. Liniger","doi":"10.1109/IRWS.2005.1609559","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609559","url":null,"abstract":"In a study of the TDDB performance of an ultra-low-k (ULK) dielectric (JSR 5537 k = 2.3) it was found that the presence of moisture significantly reduced the TDDB lifetime as well as increased leakage and capacitance. It was also observed that the field coefficient (/spl gamma/) in an \"E\" TDDB lifetime model was significantly larger in \"dry\" samples than in \"wet\" samples.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126100639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/irws.2005.1609601
J. Suehle, R. Lacoe, L. Stout, Chadwin D. Young, Chittoor Parthasarathy, G. Ribes, Siddarth A. Krishnan, D. Tanner, Dimitris Ioannou, A. Modelli, Nitish Mathur, Yuan Chen, L. Westergard, E. Hammerl, M. Impronta, G. Alers, G. Tao, A. Turner, M. Ogas, C. Christiansen, E. Bouyssou, R. Degraeve, T. Sullivan, X. Federspiel, Julien Micheon, M. Ruat, M. Bailon, P. Gaitonde, B. Knowlton, Yuwen Chen, R. Vollertsen, G. Lucovsky, J. Conley, P. Lenahan, David Catlett, G. Goffman, Bill Tonti, Y. Nelson, Sharad Prasad, R. Southwick, J. Ryan, Françoise Marc, James Chen, R. Vollertsen
{"title":"2005 IIR Attendees","authors":"J. Suehle, R. Lacoe, L. Stout, Chadwin D. Young, Chittoor Parthasarathy, G. Ribes, Siddarth A. Krishnan, D. Tanner, Dimitris Ioannou, A. Modelli, Nitish Mathur, Yuan Chen, L. Westergard, E. Hammerl, M. Impronta, G. Alers, G. Tao, A. Turner, M. Ogas, C. Christiansen, E. Bouyssou, R. Degraeve, T. Sullivan, X. Federspiel, Julien Micheon, M. Ruat, M. Bailon, P. Gaitonde, B. Knowlton, Yuwen Chen, R. Vollertsen, G. Lucovsky, J. Conley, P. Lenahan, David Catlett, G. Goffman, Bill Tonti, Y. Nelson, Sharad Prasad, R. Southwick, J. Ryan, Françoise Marc, James Chen, R. Vollertsen","doi":"10.1109/irws.2005.1609601","DOIUrl":"https://doi.org/10.1109/irws.2005.1609601","url":null,"abstract":"","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130620952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IRWS.2005.1609590
A. Modelli, A. Visconti
Summary form only given. Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met. The tutorial discussed the failure mechanisms limiting memory endurance and data retention. Reference was made to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array. The first part of the tutorial was dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection were examined. The second part dealt with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the stress-induced leakage current observed in large area capacitors was discussed. Design solutions to solve, or at least ease, this issue was considered.
{"title":"Flash memory reliability","authors":"A. Modelli, A. Visconti","doi":"10.1109/IRWS.2005.1609590","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609590","url":null,"abstract":"Summary form only given. Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met. The tutorial discussed the failure mechanisms limiting memory endurance and data retention. Reference was made to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array. The first part of the tutorial was dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection were examined. The second part dealt with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the stress-induced leakage current observed in large area capacitors was discussed. Design solutions to solve, or at least ease, this issue was considered.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123903761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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