Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609589
R. Locoe
Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.
{"title":"Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects","authors":"R. Locoe","doi":"10.1109/IRWS.2005.1609589","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609589","url":null,"abstract":"Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122084254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609584
M. Impronta, S. Farris, A. Ficola, A. Scorzoni
The isothermal test is a promising wafer-level tool to characterize electromigration also in Cu-damascene metallizations, when a correct temperature determination is employed. In this work an improved feedback algorithm is proposed to reduce the observed resistance instability in the stress phase, when the copper structures are approaching the failure
{"title":"Resistance instability in Cu-damascene structures during the isothermal electromigration test","authors":"M. Impronta, S. Farris, A. Ficola, A. Scorzoni","doi":"10.1109/IRWS.2005.1609584","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609584","url":null,"abstract":"The isothermal test is a promising wafer-level tool to characterize electromigration also in Cu-damascene metallizations, when a correct temperature determination is employed. In this work an improved feedback algorithm is proposed to reduce the observed resistance instability in the stress phase, when the copper structures are approaching the failure","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130193144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609581
F. Marc, Y. Danto
This paper presents an original approach for ageing simulation of electronic circuits and systems. This approach is based on the use of an analogue and mixed signal hardware description language (VHDL-AMS) that make possible a behavioural description of the circuit including electrically-dependant ageing phenomena.
{"title":"First steps toward ageing simulation of complex analogue circuits with behavioural modelling","authors":"F. Marc, Y. Danto","doi":"10.1109/IRWS.2005.1609581","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609581","url":null,"abstract":"This paper presents an original approach for ageing simulation of electronic circuits and systems. This approach is based on the use of an analogue and mixed signal hardware description language (VHDL-AMS) that make possible a behavioural description of the circuit including electrically-dependant ageing phenomena.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609595
Y. Nelson
The special interest group discussed the following topics : stress temperature conditions; Kelvin test structures; via chains; and proper choice of upper and lower metal connections
特别兴趣小组讨论了以下主题:应力温度条件;开尔文测试结构;通过链;正确选择上下金属连接
{"title":"Discussion Groups (DG) and Special Interest Group (SIG) Summary Reports","authors":"Y. Nelson","doi":"10.1109/IRWS.2005.1609595","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609595","url":null,"abstract":"The special interest group discussed the following topics : stress temperature conditions; Kelvin test structures; via chains; and proper choice of upper and lower metal connections","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132399245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609565
Bin Wang, H. Nguyen, A. Horch, Yanjun Ma, R. Paulsen
Some researchers have previously reported that silicide-blocking layers play a key role in retaining charge in embedded DRAM and Flash memory technologies. In this paper, we investigate the retention characteristics for silicided and unsilicided floating gates embedded logic NVM fabricated in a standard 0.25/spl mu/m logic process. In contrast to previous reports, it is found in this work that silicided and unsilicided NVM have equivalent retention for cycled and un-cycled arrays with temperature bake up to 6120 hrs at 135/spl deg/C. As a result, there is more flexibility in optimizing the memory cell area for logic NVM by removing the silicide-blocking layer.
{"title":"Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory","authors":"Bin Wang, H. Nguyen, A. Horch, Yanjun Ma, R. Paulsen","doi":"10.1109/IRWS.2005.1609565","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609565","url":null,"abstract":"Some researchers have previously reported that silicide-blocking layers play a key role in retaining charge in embedded DRAM and Flash memory technologies. In this paper, we investigate the retention characteristics for silicided and unsilicided floating gates embedded logic NVM fabricated in a standard 0.25/spl mu/m logic process. In contrast to previous reports, it is found in this work that silicided and unsilicided NVM have equivalent retention for cycled and un-cycled arrays with temperature bake up to 6120 hrs at 135/spl deg/C. As a result, there is more flexibility in optimizing the memory cell area for logic NVM by removing the silicide-blocking layer.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115237231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609567
G. Ribes, S. Bruyère, D. Roy, C. Parthasarthy, M. Muller, M. Denais, V. Huard, T. Skotnicki, G. Ghibaudo
The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics have been identified to replace the conventional SiO/sub 2/ as gate dielectrics materials. One of the main concerns which could be show-stopper for a successful integration of these new materials is the Vt instability relating to electron trapping. In this paper we discuss the origin of the electron traps. Based on a review of literature results and new experimental data, we demonstrate that this instability can be reduced by process optimization.
{"title":"Physical origin of Vt instabilities in high-k dielectrics and process optimisation","authors":"G. Ribes, S. Bruyère, D. Roy, C. Parthasarthy, M. Muller, M. Denais, V. Huard, T. Skotnicki, G. Ghibaudo","doi":"10.1109/IRWS.2005.1609567","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609567","url":null,"abstract":"The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics have been identified to replace the conventional SiO/sub 2/ as gate dielectrics materials. One of the main concerns which could be show-stopper for a successful integration of these new materials is the Vt instability relating to electron trapping. In this paper we discuss the origin of the electron traps. Based on a review of literature results and new experimental data, we demonstrate that this instability can be reduced by process optimization.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609553
C. Guérin, V. Huard, A. Bravaix, M. Denais, J. Roux, F. Perrier, W. Baks
This work shows that the channel hot carrier (CHC) degradation for a p-MOSFET consists of two different regimes. At low V/sub g/, the degradation is dominated by hot electrons produced by impact ionization. The hot electrons are responsible for the creation of both interface traps and electron traps within the oxide. At high V/sub g/, a NBT-induced hot carrier effect is evidenced as well as an anomalous CHC effect. This work should help understanding the CHC degradation of pMOSFET as well as determining the worst case degradation.
{"title":"Combined effect of NBTI and channel hot carrier effects in pMOSFETs","authors":"C. Guérin, V. Huard, A. Bravaix, M. Denais, J. Roux, F. Perrier, W. Baks","doi":"10.1109/IRWS.2005.1609553","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609553","url":null,"abstract":"This work shows that the channel hot carrier (CHC) degradation for a p-MOSFET consists of two different regimes. At low V/sub g/, the degradation is dominated by hot electrons produced by impact ionization. The hot electrons are responsible for the creation of both interface traps and electron traps within the oxide. At high V/sub g/, a NBT-induced hot carrier effect is evidenced as well as an anomalous CHC effect. This work should help understanding the CHC degradation of pMOSFET as well as determining the worst case degradation.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130537634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609578
P. Gaitonde, S. Gaul, T. Crandell, S. Earles
To incorporate high current electro-static discharge (ESD) conditions, we have extended a NMOS SPICE model to include models of a parasitic BJT, body (substrate) resistance and impact ionization current. The approach taken models the geometry and layout dependence of the NMOS, making the model scalable. The developed model predicts trigger voltages of MOS and BJT qualitatively and with reasonable accuracy. Clamps having longer body to source spacing are seen to trigger the parasitic BJT faster, irrespective of the MOS channel length. The parasitic BJT device parameters do not have significant effect on the clamp turn-on voltage
{"title":"Predictive simulation to improve reliability of a snapback-based NMOS clamp","authors":"P. Gaitonde, S. Gaul, T. Crandell, S. Earles","doi":"10.1109/IRWS.2005.1609578","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609578","url":null,"abstract":"To incorporate high current electro-static discharge (ESD) conditions, we have extended a NMOS SPICE model to include models of a parasitic BJT, body (substrate) resistance and impact ionization current. The approach taken models the geometry and layout dependence of the NMOS, making the model scalable. The developed model predicts trigger voltages of MOS and BJT qualitatively and with reasonable accuracy. Clamps having longer body to source spacing are seen to trigger the parasitic BJT faster, irrespective of the MOS channel length. The parasitic BJT device parameters do not have significant effect on the clamp turn-on voltage","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131365000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609554
S.T. Liu, D. Ioannou, D. Ioannou, M. Flanery, H. Hughes
In this paper we describe NBTI tests and report results for partially depleted (PD) SOI MOSFETs selected from 0.35 and 0.15 /spl mu/m technologies for harsh environment (i.e., space, high temperature, etc.) applications. When studying "pure" NBTI degradation, we find that the results are similar to bulk technologies, and in good agreement with the standard reaction-diffusion (R-D) theory of NBTI. However, when both gate and drain are biased as in a hot carrier injection (HCI) degradation situation, an interesting interaction of HCI and NBTI is observed, which leads to the resolution of the question of worst case HCI stress conditions for p-channel SOI MOSFETs with thin gate oxides.
在本文中，我们描述了部分耗尽(PD) SOI mosfet从0.35和0.15 /spl mu/m技术中选择的NBTI测试和报告结果，用于恶劣环境(即空间，高温等)应用。当研究“纯”NBTI降解时，我们发现结果与本体技术相似，并且与NBTI的标准反应扩散(R-D)理论很好地吻合。然而，当栅极和漏极都偏置时，如在热载流子注入(HCI)降解情况下，观察到HCI和NBTI的有趣相互作用，从而解决了具有薄栅极氧化物的p沟道SOI mosfet的最坏情况HCI应力条件问题。
{"title":"NBTI in SOI p-channel MOS field effect transistors","authors":"S.T. Liu, D. Ioannou, D. Ioannou, M. Flanery, H. Hughes","doi":"10.1109/IRWS.2005.1609554","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609554","url":null,"abstract":"In this paper we describe NBTI tests and report results for partially depleted (PD) SOI MOSFETs selected from 0.35 and 0.15 /spl mu/m technologies for harsh environment (i.e., space, high temperature, etc.) applications. When studying \"pure\" NBTI degradation, we find that the results are similar to bulk technologies, and in good agreement with the standard reaction-diffusion (R-D) theory of NBTI. However, when both gate and drain are biased as in a hot carrier injection (HCI) degradation situation, an interesting interaction of HCI and NBTI is observed, which leads to the resolution of the question of worst case HCI stress conditions for p-channel SOI MOSFETs with thin gate oxides.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122217959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609577
I. Wan, D. Bockelman, Yun Xuan, S. Chen
Infra-red emission microscopy (IREM) has been widely used for physical isolation of several defect mechanisms where "abnormal" photon/thermal emissions are generated. Failures caused by metal shorts, contending nodes or electrical overstress are some of the issues that affect the normal operation of a circuit and result in intense emissions in the near infra-red (NIR) spectrum. IREM has proven successful in locating these faults and in this paper, we expand the usage of this tool by showing its effectiveness in the detection of failures caused by highly resistive nodes. We establish this idea with circuit simulation results and show real Si data that was seen on 65nm process technology products.
{"title":"IREM usage in the detection of highly resistive failures on 65nm products","authors":"I. Wan, D. Bockelman, Yun Xuan, S. Chen","doi":"10.1109/IRWS.2005.1609577","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609577","url":null,"abstract":"Infra-red emission microscopy (IREM) has been widely used for physical isolation of several defect mechanisms where \"abnormal\" photon/thermal emissions are generated. Failures caused by metal shorts, contending nodes or electrical overstress are some of the issues that affect the normal operation of a circuit and result in intense emissions in the near infra-red (NIR) spectrum. IREM has proven successful in locating these faults and in this paper, we expand the usage of this tool by showing its effectiveness in the detection of failures caused by highly resistive nodes. We establish this idea with circuit simulation results and show real Si data that was seen on 65nm process technology products.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122035706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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