Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609576
N. Mathur, Y. Ahn, I. Kouznetov, F. Jenne, J. Fulford
A study on the programming yield of one time programmable (OTP) device based on anti-fuse gate oxide breakdown on p-type and n-type substrates is presented. Charge injection into anti-fuse gate oxide from the substrate during OTP programming can alter device characteristics, which impact the OTP programming yield. Experiments showed higher programming yield with increasing anti-fuse gate read current can be obtained with the OTP device based on anti-fuse gate oxide breakdown on n-type substrate compared to p-type substrate due to less electron-hole pair generation.
{"title":"One time programming device yield study based on anti-fuse gate oxide breakdown on p-type and n-type substrates","authors":"N. Mathur, Y. Ahn, I. Kouznetov, F. Jenne, J. Fulford","doi":"10.1109/IRWS.2005.1609576","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609576","url":null,"abstract":"A study on the programming yield of one time programmable (OTP) device based on anti-fuse gate oxide breakdown on p-type and n-type substrates is presented. Charge injection into anti-fuse gate oxide from the substrate during OTP programming can alter device characteristics, which impact the OTP programming yield. Experiments showed higher programming yield with increasing anti-fuse gate read current can be obtained with the OTP device based on anti-fuse gate oxide breakdown on n-type substrate compared to p-type substrate due to less electron-hole pair generation.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133927545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609597
J. Campbell, C. Parthasarathy
The negative bias temperature instability (NBTI) is a pMOSFET reliability problem that is most often observed as a shift in threshold voltage (V) in devices subject to moderate negative gate biases at moderately elevated temperatures. Despite thefirst observations ofNBTI more than 30 years ago, it has not been become a major concern until the pastfew years. The aggravation of NBTI is due to a scaling-induced increase in effective oxidefield as well as the addition ofnitrogen in the gate dielectric. Many models have been proposed to predict the NBTIphenomenon, but a complete understanding ofthe NBTIphenomenon has proved elusive.
{"title":"IIRW 2005 Discussion Group Summary: NBTI","authors":"J. Campbell, C. Parthasarathy","doi":"10.1109/IRWS.2005.1609597","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609597","url":null,"abstract":"The negative bias temperature instability (NBTI) is a pMOSFET reliability problem that is most often observed as a shift in threshold voltage (V) in devices subject to moderate negative gate biases at moderately elevated temperatures. Despite thefirst observations ofNBTI more than 30 years ago, it has not been become a major concern until the pastfew years. The aggravation of NBTI is due to a scaling-induced increase in effective oxidefield as well as the addition ofnitrogen in the gate dielectric. Many models have been proposed to predict the NBTIphenomenon, but a complete understanding ofthe NBTIphenomenon has proved elusive.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132486697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609552
V. Huard, C. Parthasarathy, M. Denais
This work shows that the recovery of NBTI degradation in ultra-small gate area pMOSFETs presents abrupt steps which are related to the detrapping of one hole. These results can be obtained by using a new approach to monitor the recovery, which is extremely more sensitive than previously proposed methodology. This result opens the way to model the NBTI degradation for ultra-small gate area devices which are main components of SRAM cells.
{"title":"Single-hole detrapping events in pMOSFETs NBTI degradation","authors":"V. Huard, C. Parthasarathy, M. Denais","doi":"10.1109/IRWS.2005.1609552","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609552","url":null,"abstract":"This work shows that the recovery of NBTI degradation in ultra-small gate area pMOSFETs presents abrupt steps which are related to the detrapping of one hole. These results can be obtained by using a new approach to monitor the recovery, which is extremely more sensitive than previously proposed methodology. This result opens the way to model the NBTI degradation for ultra-small gate area devices which are main components of SRAM cells.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609583
X. Federspiel, D. Ney, V. Girault
Several experimental studies reported an increase of the copper resistivity with decreasing interconnects dimensions (Schafft and Suchle, 1992). However, the accuracy of measurement is limited by the knowledge of sample geometry. As a matter of fact, the geometry of resistors issued from advanced damascene process is varying with process parameters (trench height, diffusion barrier thickness, CMP (chemical mechanical polishing) effect). Taking into consideration Mathiessen empirical relation we established a relation between, resistivity, TCR (temperature coefficient of resistance) and metal cross section to develop an accurate methodology to determine thickness and resistivity of damascene copper samples.
{"title":"Accurate method for determination of interconnect cross section","authors":"X. Federspiel, D. Ney, V. Girault","doi":"10.1109/IRWS.2005.1609583","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609583","url":null,"abstract":"Several experimental studies reported an increase of the copper resistivity with decreasing interconnects dimensions (Schafft and Suchle, 1992). However, the accuracy of measurement is limited by the knowledge of sample geometry. As a matter of fact, the geometry of resistors issued from advanced damascene process is varying with process parameters (trench height, diffusion barrier thickness, CMP (chemical mechanical polishing) effect). Taking into consideration Mathiessen empirical relation we established a relation between, resistivity, TCR (temperature coefficient of resistance) and metal cross section to develop an accurate methodology to determine thickness and resistivity of damascene copper samples.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125019587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609566
G. Tao, Jaap Bisschop, S. Nath
The bathtub curve is widely used in the reliability world to illustrate three characteristics of the system (or an IC) failure rate curve: the early failure rate during initial phase of life, the intrinsic random constant failure rate in the use life, and the wear-out phase at the end-of-life (Reddy, 2003). The bottom part is usually characterised by a constant failure rate expressed in FIT (failure in time, which is 1 failure in 109 device hours). As systems become more and more complex, more and more redundancy and EDAC (error detection and correction, also called error correction code ECC) are implemented in order to improve the system robustness and reliability (Slayman, 2003 and Ziegler and Puchner, 2004). By studying the data retention failure rates of Flash products with ECC, we found that the bottom part of the bathtub (used to be characterized by "random constant failure rate") is not flat. We suggest replace the FIT number by a cumulative failure fraction with a certain time stamp.
{"title":"On intrinsic failure rate of products with error correction","authors":"G. Tao, Jaap Bisschop, S. Nath","doi":"10.1109/IRWS.2005.1609566","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609566","url":null,"abstract":"The bathtub curve is widely used in the reliability world to illustrate three characteristics of the system (or an IC) failure rate curve: the early failure rate during initial phase of life, the intrinsic random constant failure rate in the use life, and the wear-out phase at the end-of-life (Reddy, 2003). The bottom part is usually characterised by a constant failure rate expressed in FIT (failure in time, which is 1 failure in 109 device hours). As systems become more and more complex, more and more redundancy and EDAC (error detection and correction, also called error correction code ECC) are implemented in order to improve the system robustness and reliability (Slayman, 2003 and Ziegler and Puchner, 2004). By studying the data retention failure rates of Flash products with ECC, we found that the bottom part of the bathtub (used to be characterized by \"random constant failure rate\") is not flat. We suggest replace the FIT number by a cumulative failure fraction with a certain time stamp.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609599
M. Porter, A. Turner
The group reported that they are using a variety of times, commonly ranging from 5-10 hours, to 24 hours, to as long as 160 hours. The longer times were generally used in high-reliability applications or in situations where companies continue to follow the MIL-STD procedures. The group felt that 160 hours was overkill for most applications. The typical burn-in temperature among the companies represented in the discussion is 125degC to 140degC. In some cases, product burn-in times are reduced as the process and product matures and more field history is accumulated. There were no specific criteria given for how the process is managed, nor what data are required to achieve a reduced time. Many companies use per-product burn-in times, with starting point conditions based upon historical precedent, or upon market segment (e.g. commercial, automotive, industrial). For embedded DRAM, voltage screen at IC probe is used instead of burn-in
{"title":"IIRW 2005 discussion group summary: product reliability","authors":"M. Porter, A. Turner","doi":"10.1109/IRWS.2005.1609599","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609599","url":null,"abstract":"The group reported that they are using a variety of times, commonly ranging from 5-10 hours, to 24 hours, to as long as 160 hours. The longer times were generally used in high-reliability applications or in situations where companies continue to follow the MIL-STD procedures. The group felt that 160 hours was overkill for most applications. The typical burn-in temperature among the companies represented in the discussion is 125degC to 140degC. In some cases, product burn-in times are reduced as the process and product matures and more field history is accumulated. There were no specific criteria given for how the process is managed, nor what data are required to achieve a reduced time. Many companies use per-product burn-in times, with starting point conditions based upon historical precedent, or upon market segment (e.g. commercial, automotive, industrial). For embedded DRAM, voltage screen at IC probe is used instead of burn-in","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128245038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609569
A. Neugroschel, G. Bersuker
Charge trapping in high-k transistor gate stacks shifts the threshold voltage and may affect the channel mobility. Since both electrons and holes may potentially contribute to charge trapping, it is important to determine the polarity of the trapped charge and to relate it to the stress or operating conditions. A constant-voltage stress was applied to nMOSFETs and pMOSFETs and the charge trapping in the gate stack and the interface trap generation was monitored by the DCIV method. Detailed band diagram for each stress condition is used to correlate the measured charge trapping and the interface trap generation/annihilation to the dominant tunneling current component and to delineate the physical mechanisms and charge-trapping pathways.
{"title":"Charge instability in high-k gate stacks with metal and polysilicon electrodes","authors":"A. Neugroschel, G. Bersuker","doi":"10.1109/IRWS.2005.1609569","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609569","url":null,"abstract":"Charge trapping in high-k transistor gate stacks shifts the threshold voltage and may affect the channel mobility. Since both electrons and holes may potentially contribute to charge trapping, it is important to determine the polarity of the trapped charge and to relate it to the stress or operating conditions. A constant-voltage stress was applied to nMOSFETs and pMOSFETs and the charge trapping in the gate stack and the interface trap generation was monitored by the DCIV method. Detailed band diagram for each stress condition is used to correlate the measured charge trapping and the interface trap generation/annihilation to the dominant tunneling current component and to delineate the physical mechanisms and charge-trapping pathways.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609580
M. Bailon, P. Salinas, J.S. Arboleda, J. Miranda
Localization, identification and characterization of EOS-induced defects found in submicron devices were demonstrated using a new FA procedure. IR photon emission and circuit analysis were used for defect localization while spectral profile of photon emission was utilized for defect finger-printing analysis. Finally, frontside and backside FA methods were done to confirm the actual failure mechanism in the device under analysis
{"title":"Characterization of EOS induced defects on submicron devices using 2D spectral imaging","authors":"M. Bailon, P. Salinas, J.S. Arboleda, J. Miranda","doi":"10.1109/IRWS.2005.1609580","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609580","url":null,"abstract":"Localization, identification and characterization of EOS-induced defects found in submicron devices were demonstrated using a new FA procedure. IR photon emission and circuit analysis were used for defect localization while spectral profile of photon emission was utilized for defect finger-printing analysis. Finally, frontside and backside FA methods were done to confirm the actual failure mechanism in the device under analysis","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609560
R. Duschl, R. Vollertsen
The TDDB-power-law model was shown to describe the experimental data for nFET and pFET devices in the direct tunneling regime very well. In this work it is investigated whether it can be extended into the voltage range, where elastic Fowler-Nordheim tunneling dominates. Both nFET and pFET devices are investigated and were found to behave different. For nFET a universal power-law expression is proposed for the entire sub-10 nm range.
{"title":"Voltage acceleration of oxide breakdown in the sub-10 nm Fowler-Nordheim and direct tunneling regime","authors":"R. Duschl, R. Vollertsen","doi":"10.1109/IRWS.2005.1609560","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609560","url":null,"abstract":"The TDDB-power-law model was shown to describe the experimental data for nFET and pFET devices in the direct tunneling regime very well. In this work it is investigated whether it can be extended into the voltage range, where elastic Fowler-Nordheim tunneling dominates. Both nFET and pFET devices are investigated and were found to behave different. For nFET a universal power-law expression is proposed for the entire sub-10 nm range.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133557499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609594
A. Turner
While 90nm and 45nm CMOS matures from the lab to the manufacturing floor, the reliability of the product becomes more important as defect densities and degradation mechanisms that affect microprocessors may not be observable in sufficient quantities or magnitude at the macro level. There is a need to understand that the interaction between design and manufacturing, as it relates to field reliability, is moving beyond test-site measurements and design simulation alone. Only via the integration of reliability methodologies throughout the entire product development cycle will tomorrow's products be successful. Understanding the product reliability and performance metrics through the useful life of the product is imperative. This requires knowledge of the most sensitive circuits and the mechanisms that are most likely to negatively affect them. The most time efficient way to do this is by tracking these metrics through an accelerated life stress and evaluating fails accordingly
{"title":"Product reliability in 90nm CMOS and beyond","authors":"A. Turner","doi":"10.1109/IRWS.2005.1609594","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609594","url":null,"abstract":"While 90nm and 45nm CMOS matures from the lab to the manufacturing floor, the reliability of the product becomes more important as defect densities and degradation mechanisms that affect microprocessors may not be observable in sufficient quantities or magnitude at the macro level. There is a need to understand that the interaction between design and manufacturing, as it relates to field reliability, is moving beyond test-site measurements and design simulation alone. Only via the integration of reliability methodologies throughout the entire product development cycle will tomorrow's products be successful. Understanding the product reliability and performance metrics through the useful life of the product is imperative. This requires knowledge of the most sensitive circuits and the mechanisms that are most likely to negatively affect them. The most time efficient way to do this is by tracking these metrics through an accelerated life stress and evaluating fails accordingly","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123735688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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