Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189200
K. Murakami, M. Ueda, M. Ohmori, I. Ohkura, Y. Horiba, T. Nakano
The new DSAMOS-bipolar compatible devices have been developed by utilizing the high transcoductance / input impedance of DSA MOS transistor and driving capability of bipolar one for large current. In the double diffused technology, dopants were deposited by the ion implanting method, which resulted in the better threshold voltage controllability (ΔV/Vth=0.05) for DSA MOSFET and high current gain (β=800) for npn transistor. High transconductance of 1.3 mΩ3 was obtained with small size transistor (W =300 µm). The optimum value of base dose was determined by the relationship between Vth and ρsb (base sheet resistance for analogue circuit use.
{"title":"Double ion implanted DSAMOS-bipolar devices","authors":"K. Murakami, M. Ueda, M. Ohmori, I. Ohkura, Y. Horiba, T. Nakano","doi":"10.1109/IEDM.1977.189200","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189200","url":null,"abstract":"The new DSAMOS-bipolar compatible devices have been developed by utilizing the high transcoductance / input impedance of DSA MOS transistor and driving capability of bipolar one for large current. In the double diffused technology, dopants were deposited by the ion implanting method, which resulted in the better threshold voltage controllability (ΔV/Vth=0.05) for DSA MOSFET and high current gain (β=800) for npn transistor. High transconductance of 1.3 mΩ3 was obtained with small size transistor (W =300 µm). The optimum value of base dose was determined by the relationship between Vth and ρsb (base sheet resistance for analogue circuit use.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128930916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189219
G. MacMaster, L. Nichols
Raytheon Company, under Naval Electronic Systems Command sponsorship, has conducted a program to develop a high gain crossed-field amplifier. This development program reflected the future needs for high-gain CFA's that would permit lower-powered rf drivers and eliminate the need for high power isolators. Present advantages of the crossed-field amplifier, such as high efficiency and cold cathode operation, were to be retained. The method of obtaining high gain in a crossed-field amplifier was to introduce the rf drive signal at the source of electrons. This was accomplished by forming the secondary emission cathode into a slow-wave structure that will support microwave energy. The traveling wave on the cathode forms the desired space charge spokes at a low energy level. These space charge spokes induce current in the anode circuit. The introduction of rf drive signal onto the cathode also provides a high degree of isolation between the amplified output signal and the rf drive energy. During the present cathode-driven, crossed-field amplifier program, the S-band CFA was operated with an rf gain of 28 dB over a frequency band of 14%. Initial background noise measurements were made using a full 2000 MHz sweep on the spectrum analyzer.
{"title":"High-gain crossed-field amplifier tube","authors":"G. MacMaster, L. Nichols","doi":"10.1109/IEDM.1977.189219","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189219","url":null,"abstract":"Raytheon Company, under Naval Electronic Systems Command sponsorship, has conducted a program to develop a high gain crossed-field amplifier. This development program reflected the future needs for high-gain CFA's that would permit lower-powered rf drivers and eliminate the need for high power isolators. Present advantages of the crossed-field amplifier, such as high efficiency and cold cathode operation, were to be retained. The method of obtaining high gain in a crossed-field amplifier was to introduce the rf drive signal at the source of electrons. This was accomplished by forming the secondary emission cathode into a slow-wave structure that will support microwave energy. The traveling wave on the cathode forms the desired space charge spokes at a low energy level. These space charge spokes induce current in the anode circuit. The introduction of rf drive signal onto the cathode also provides a high degree of isolation between the amplified output signal and the rf drive energy. During the present cathode-driven, crossed-field amplifier program, the S-band CFA was operated with an rf gain of 28 dB over a frequency band of 14%. Initial background noise measurements were made using a full 2000 MHz sweep on the spectrum analyzer.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130186527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189279
T. Toyabe, K. Yamaguchi, S. Asai, M. Mock
Negative resistance characteristics observed at breakdown result in a severe decrease in the highest voltage applicable to short-channel N-MOSFET's. The excess substrate current generated by impact ionization causes a significant voltage drop across the substrate resistance. This current forward-biases the source-substrate junction strongly enough to turn on the junction at relatively low drain voltages because of its positive feed-back effect. This results in the decrease in breakdown voltage and negative resistance characteristics. Based on the above, an accurate breakdown model for MOSFET's is presented. This model is composed of a two-dimensional analysis of the electric field, calculation of the multiplication factor, and feed-back of the resulting potential modification due to the substrate current in the two-dimensional analysis. Calculated current-voltage curves with negative resistance agree excellently with experiments for short-channel N-MOSFET's. The model predicts that P-MOSFET's will be preferable to N-MOSFET's from the breakdown point of view especially for submicron channel lengths.
{"title":"A two-dimensional avalanche breakdown model of submicron MOSFET's","authors":"T. Toyabe, K. Yamaguchi, S. Asai, M. Mock","doi":"10.1109/IEDM.1977.189279","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189279","url":null,"abstract":"Negative resistance characteristics observed at breakdown result in a severe decrease in the highest voltage applicable to short-channel N-MOSFET's. The excess substrate current generated by impact ionization causes a significant voltage drop across the substrate resistance. This current forward-biases the source-substrate junction strongly enough to turn on the junction at relatively low drain voltages because of its positive feed-back effect. This results in the decrease in breakdown voltage and negative resistance characteristics. Based on the above, an accurate breakdown model for MOSFET's is presented. This model is composed of a two-dimensional analysis of the electric field, calculation of the multiplication factor, and feed-back of the resulting potential modification due to the substrate current in the two-dimensional analysis. Calculated current-voltage curves with negative resistance agree excellently with experiments for short-channel N-MOSFET's. The model predicts that P-MOSFET's will be preferable to N-MOSFET's from the breakdown point of view especially for submicron channel lengths.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189178
G. Kamarinos, P. Viktorovitch, S. Cristoloveanu, J. Borel, R. Staderini
The values of recombination parameters (bulk lifetime and surface recombination velocities) of films of Silicon On Sapphire allow the realization of magnetodiodes, which are both very sensitive and compatible with the VLSI Technology. The S. O. S. magnetodiodes we present exhibit an average sensitiveness on the order of some 150 mA/Tesla (10 times the sensitiveness of Hall effect). Besides very low magnetic fields (B = 10-8T = 10γ) are easily detectable.
{"title":"Silicon on sapphire magnetodiodes of high sensitiveness","authors":"G. Kamarinos, P. Viktorovitch, S. Cristoloveanu, J. Borel, R. Staderini","doi":"10.1109/IEDM.1977.189178","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189178","url":null,"abstract":"The values of recombination parameters (bulk lifetime and surface recombination velocities) of films of Silicon On Sapphire allow the realization of magnetodiodes, which are both very sensitive and compatible with the VLSI Technology. The S. O. S. magnetodiodes we present exhibit an average sensitiveness on the order of some 150 mA/Tesla (10 times the sensitiveness of Hall effect). Besides very low magnetic fields (B = 10-8T = 10γ) are easily detectable.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"469 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189240
M. Lietz
Numerical modelling of semiconductor device operation has become a useful tool for obtaining a better understanding of physical behavior and for optimizing device performance. In the field of thyristors only a few aspects of transient processes have so far been described. In this paper, results will be presented of the turnoff behavior of power thyristors, based on a numerical one-dimensional time-dependent model of a p+pnpn+structure. The phenomenological semiconductor equations are solved including realistic mobility dependencies and arbitrary base width, doping profile, carrier lifetime distribution, and current commutation rate. Emphasis is laid on the reverse current phase. It is shown: to what extent the reverse current depletes the base - the building up of the blocking voltage and the corresponding reverse current peak - the reverse recovery phase - the dependencies on lifetime distribution, initial current and current commutation rate, which can partly be expressed by analytical formulae. Conclusions concerning the most favorable lifetime profiles are drawn. The calculations are in good agreement with voltage versus time measurements performed on standard devices.
{"title":"Numerical model of the thyristor turn off","authors":"M. Lietz","doi":"10.1109/IEDM.1977.189240","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189240","url":null,"abstract":"Numerical modelling of semiconductor device operation has become a useful tool for obtaining a better understanding of physical behavior and for optimizing device performance. In the field of thyristors only a few aspects of transient processes have so far been described. In this paper, results will be presented of the turnoff behavior of power thyristors, based on a numerical one-dimensional time-dependent model of a p+pnpn+structure. The phenomenological semiconductor equations are solved including realistic mobility dependencies and arbitrary base width, doping profile, carrier lifetime distribution, and current commutation rate. Emphasis is laid on the reverse current phase. It is shown: to what extent the reverse current depletes the base - the building up of the blocking voltage and the corresponding reverse current peak - the reverse recovery phase - the dependencies on lifetime distribution, initial current and current commutation rate, which can partly be expressed by analytical formulae. Conclusions concerning the most favorable lifetime profiles are drawn. The calculations are in good agreement with voltage versus time measurements performed on standard devices.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122678781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189151
B. Wessels, B. Baliga
A new vertical channel field controlled thyristor structure is described. This device has a surface grid structure with a high channel length to width aspect ratio which simultaneously allows achieving high blocking gains and fast gate turn-off capability. The devices have the capability of blocking more than 1000 volts with an applied grid bias of 32 volts, and simultaneously exhibiting a low forward voltage drop in the on-state. In addition, the surface grid structure allows gate turn-off capability with a cathode current turn-off time of less than 0.5 microseconds.
{"title":"A high gain vertical channel controlled thyristor","authors":"B. Wessels, B. Baliga","doi":"10.1109/IEDM.1977.189151","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189151","url":null,"abstract":"A new vertical channel field controlled thyristor structure is described. This device has a surface grid structure with a high channel length to width aspect ratio which simultaneously allows achieving high blocking gains and fast gate turn-off capability. The devices have the capability of blocking more than 1000 volts with an applied grid bias of 32 volts, and simultaneously exhibiting a low forward voltage drop in the on-state. In addition, the surface grid structure allows gate turn-off capability with a cathode current turn-off time of less than 0.5 microseconds.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189195
L. Ragonese, N. Yang
Contemporary I2L logic gate structures use an in-line topography for the multiple collector npn transistor. Decoupling effects between adjacent segments introduce a spread in the relative performance of the outputs with respect to gain, maximum collector current, and propagation delay. A novel cell layout, which enables the base contact and pnp injector to be symmetricaUy positioned relative to every collector in a multiple collector device, was developed. In controlled experiments, using an industry compatible fabrication process, symmetrical quad output cells demonstrated a factor-of-20 increase in the magnitude of useful npn collector current and the degree of gain uniformity among outputs.
{"title":"Enhanced integrated injection logic performance using novel symmetrical cell topography","authors":"L. Ragonese, N. Yang","doi":"10.1109/IEDM.1977.189195","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189195","url":null,"abstract":"Contemporary I2L logic gate structures use an in-line topography for the multiple collector npn transistor. Decoupling effects between adjacent segments introduce a spread in the relative performance of the outputs with respect to gain, maximum collector current, and propagation delay. A novel cell layout, which enables the base contact and pnp injector to be symmetricaUy positioned relative to every collector in a multiple collector device, was developed. In controlled experiments, using an industry compatible fabrication process, symmetrical quad output cells demonstrated a factor-of-20 increase in the magnitude of useful npn collector current and the degree of gain uniformity among outputs.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133093367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189213
G. Swartz, L. Napoli, N. Klein
Silicon photovoltaic p+nn+solar cells have been developed for use in solar collectors which concentrates the solar illumination 250 to 350 times. The cell efficiency of these layered back-contact cells at a solar concentration of 280 suns (28 watts/cm2) is 15.5 percent. The thick base layer to achieve good quantum efficiency in the violet, the long minority carrier lifetime, the optimized grid structure, and two layer antireflection coating are all combined to produce an efficient solar cell at high solar concentration.
{"title":"Silicon solar cells for use at high solar concentration","authors":"G. Swartz, L. Napoli, N. Klein","doi":"10.1109/IEDM.1977.189213","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189213","url":null,"abstract":"Silicon photovoltaic p+nn+solar cells have been developed for use in solar collectors which concentrates the solar illumination 250 to 350 times. The cell efficiency of these layered back-contact cells at a solar concentration of 280 suns (28 watts/cm2) is 15.5 percent. The thick base layer to achieve good quantum efficiency in the violet, the long minority carrier lifetime, the optimized grid structure, and two layer antireflection coating are all combined to produce an efficient solar cell at high solar concentration.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189293
E. P. Eernisse, C. E. Land, J. Snelling
The concept of using handwriting dynamics for electronic identification is discussed. A piezo-electric sensor pen for obtaining the pen point dynamics during writing is described. Design equations are derived and details of an operating device are presented. Typical output waveforms are shown to demonstrate the operation of the pen and to show the dissimilarities between dynamics of a genuine signature and an attempted forgery.
{"title":"Piezoelectric sensor pen for dynamic signature verification","authors":"E. P. Eernisse, C. E. Land, J. Snelling","doi":"10.1109/IEDM.1977.189293","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189293","url":null,"abstract":"The concept of using handwriting dynamics for electronic identification is discussed. A piezo-electric sensor pen for obtaining the pen point dynamics during writing is described. Design equations are derived and details of an operating device are presented. Typical output waveforms are shown to demonstrate the operation of the pen and to show the dissimilarities between dynamics of a genuine signature and an attempted forgery.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123881973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189140
W. Lynch
The area of an LSI chip depends not only on the minimum dimensions for the lines and spacings, but also on the realignment tolerances that are required in order to either assure or prevent an overlap for features on separate levels. Normal distributions are assumed for the misalignments and the feature sizes. A normalized solution is derived for the nominal size of each feature as a function of the alignment yield and of the standard deviations for misalignment and feature size. Applications and tradeoff examples are discussed. A simple cost model is examined in which it is shown that the larger the chip size the lower the alignment yields should be.
{"title":"The reduction of LSI chip costs by optimizing the alignment yields","authors":"W. Lynch","doi":"10.1109/IEDM.1977.189140","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189140","url":null,"abstract":"The area of an LSI chip depends not only on the minimum dimensions for the lines and spacings, but also on the realignment tolerances that are required in order to either assure or prevent an overlap for features on separate levels. Normal distributions are assumed for the misalignments and the feature sizes. A normalized solution is derived for the nominal size of each feature as a function of the alignment yield and of the standard deviations for misalignment and feature size. Applications and tradeoff examples are discussed. A simple cost model is examined in which it is shown that the larger the chip size the lower the alignment yields should be.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114622487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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