Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189315
T. Tsukada, H. Yamamoto, M. Matsui, Y. Eto, T. Hirai, E. Maruyama
In this paper, the fabrication and characteristics of the linear imaging device which uses an amorphous thin film as a photoconductive detector are described. Since the amorphous film can be made by vacuum deposition, it is possible to fabricate a long, 210 mm, sensor array, which is a key component of a contact type imaging device. A contact type imaging sensor does not require an optical lens system, and this is effective in reducing the overall size of such equipment as facsimile. A prototype of the facsimile equipment was fabricated depositing a sensor film on a fiber glass substrate. This sensor film was made of Se-As-Te chalcogenide glass. LED's were used as light sources to illuminate the original paper. The experimental results confirm that amorphous thin films are applicable to a contact-type linear photosensor array.
{"title":"Linear photosensor array using an amorphous thin film","authors":"T. Tsukada, H. Yamamoto, M. Matsui, Y. Eto, T. Hirai, E. Maruyama","doi":"10.1109/IEDM.1977.189315","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189315","url":null,"abstract":"In this paper, the fabrication and characteristics of the linear imaging device which uses an amorphous thin film as a photoconductive detector are described. Since the amorphous film can be made by vacuum deposition, it is possible to fabricate a long, 210 mm, sensor array, which is a key component of a contact type imaging device. A contact type imaging sensor does not require an optical lens system, and this is effective in reducing the overall size of such equipment as facsimile. A prototype of the facsimile equipment was fabricated depositing a sensor film on a fiber glass substrate. This sensor film was made of Se-As-Te chalcogenide glass. LED's were used as light sources to illuminate the original paper. The experimental results confirm that amorphous thin films are applicable to a contact-type linear photosensor array.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128608979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189166
A. L. Dalisa, B. Singer, R. Liebert
Electrophoretic image displays (EPID) exhibit excellent optical characteristics, good response times, and low power consumption. However, there is no readily accessible voltage threshold in the optical response for an EPID device, and hence standard x-y addressing techniques are not applicable. This paper will describe a practical and reliable technique for providing such a threshold based upon the use of a control electrode. The control electrode design permits x-y addressing at I.C. compatible voltages, line at a time addressing rates of approximately 5 msec per line and high resolution (5 lines/mm). The design and fabrication of prototype 7×9 matrix alphanumeric devices will be described and preliminary performance characteristics will be presented.
{"title":"Matrix addressed electrophoretic displays","authors":"A. L. Dalisa, B. Singer, R. Liebert","doi":"10.1109/IEDM.1977.189166","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189166","url":null,"abstract":"Electrophoretic image displays (EPID) exhibit excellent optical characteristics, good response times, and low power consumption. However, there is no readily accessible voltage threshold in the optical response for an EPID device, and hence standard x-y addressing techniques are not applicable. This paper will describe a practical and reliable technique for providing such a threshold based upon the use of a control electrode. The control electrode design permits x-y addressing at I.C. compatible voltages, line at a time addressing rates of approximately 5 msec per line and high resolution (5 lines/mm). The design and fabrication of prototype 7×9 matrix alphanumeric devices will be described and preliminary performance characteristics will be presented.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124884566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189205
M. Berth, M. Cathelin, G. Durand
This paper describes a technological process well adapted for making high speed GaAs FET integrated circuits. The main features of this technology are : • a completely planar structure obtained by using ion implantation. • a self-allgnment of transistor gates between source and drain contacts. The process described includes the self alignment feature of that developed in our laboratory for microwave submicron gate GaAs MESFET's (1). The dielectric layer needed to insulate the two levels of interconnections can have a detrimental effect on transistors characteristics. This has been avoided by using the proper materials and deposition conditions. The results for different materials will be compared and some figures of merit of NOR-gate circuits will be given.
{"title":"Self-aligned planar technology for GaAs integrated circuits","authors":"M. Berth, M. Cathelin, G. Durand","doi":"10.1109/IEDM.1977.189205","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189205","url":null,"abstract":"This paper describes a technological process well adapted for making high speed GaAs FET integrated circuits. The main features of this technology are : • a completely planar structure obtained by using ion implantation. • a self-allgnment of transistor gates between source and drain contacts. The process described includes the self alignment feature of that developed in our laboratory for microwave submicron gate GaAs MESFET's (1). The dielectric layer needed to insulate the two levels of interconnections can have a detrimental effect on transistors characteristics. This has been avoided by using the proper materials and deposition conditions. The results for different materials will be compared and some figures of merit of NOR-gate circuits will be given.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121185791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189142
T. Russell, T. Leedy, R. L. Mattis
Various electrical alignment test structures were designed to conform to the NBS 2 × N probe pad array and are thus compatible with a class of other modular test structures. The object of this study is to determine the feasibility of this new layout, to compare results with visual alignment test structures, and to establish the limits of resolution. The structures can be used to determine the misalignment of two photomask steps and are applicable to two conducting layers that contact each other at a contact window. The electrical data are displayed as wafer vector maps which are useful in quantifying mask alignment problems.
{"title":"A comparison of electrical and visual alignment test structures for evaluating photomask alignment in integrated circuit manufacturing","authors":"T. Russell, T. Leedy, R. L. Mattis","doi":"10.1109/IEDM.1977.189142","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189142","url":null,"abstract":"Various electrical alignment test structures were designed to conform to the NBS 2 × N probe pad array and are thus compatible with a class of other modular test structures. The object of this study is to determine the feasibility of this new layout, to compare results with visual alignment test structures, and to establish the limits of resolution. The structures can be used to determine the misalignment of two photomask steps and are applicable to two conducting layers that contact each other at a contact window. The electrical data are displayed as wafer vector maps which are useful in quantifying mask alignment problems.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116407165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189291
P. Petersen, R. G. Schulze
The photoconductive properties of copper doped LPE GaP have been investigated. The photoresponse of as-grown surfaces extends from 2.2 to 5.0 eV. Photoconductive gains as high as 105have been measured. The photoconductive response time to low levels of illumination is typically a few milliseconds and the spatial uniformity of the photosignal is less than 10% over distances of 3 mm. The photomechanism has been investigated by optical quenching and by study of the variation in photosignal with photon flux. These data are interpretable with the sensitized photoconductivity model.
{"title":"Photoconductivity in LPE GaP:Cu","authors":"P. Petersen, R. G. Schulze","doi":"10.1109/IEDM.1977.189291","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189291","url":null,"abstract":"The photoconductive properties of copper doped LPE GaP have been investigated. The photoresponse of as-grown surfaces extends from 2.2 to 5.0 eV. Photoconductive gains as high as 105have been measured. The photoconductive response time to low levels of illumination is typically a few milliseconds and the spatial uniformity of the photosignal is less than 10% over distances of 3 mm. The photomechanism has been investigated by optical quenching and by study of the variation in photosignal with photon flux. These data are interpretable with the sensitized photoconductivity model.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"93 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126039949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189154
H. Becke
The development and performance of an 8A/600V gate turn-off device is discussed. The structure is built on high-resistivity n-type material using a uniformly doped, gated p-base. A test array of 8 devices was simultaneously processed on the same wafer; all geometries had approximately equal cathode areas. The cathode width, however, was varied from 2 mils to 20 mils. Switching performance was investigated. Turn-on time was relatively independent of the particular geometry while storage time and fall time decreased with decreasing cathode-finger width. Gate trigger current and forward voltage drop increased with narrowing cathode width, however. Four-hundred nanoseconds rise time and 140 nanoseconds fall time were observed for IT= 8 amperes and VD= 200 volts at Tj= 125°C with the 4-mil-wide cathode geometry.
{"title":"A high-speed, high-voltage EPI base GTO","authors":"H. Becke","doi":"10.1109/IEDM.1977.189154","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189154","url":null,"abstract":"The development and performance of an 8A/600V gate turn-off device is discussed. The structure is built on high-resistivity n-type material using a uniformly doped, gated p-base. A test array of 8 devices was simultaneously processed on the same wafer; all geometries had approximately equal cathode areas. The cathode width, however, was varied from 2 mils to 20 mils. Switching performance was investigated. Turn-on time was relatively independent of the particular geometry while storage time and fall time decreased with decreasing cathode-finger width. Gate trigger current and forward voltage drop increased with narrowing cathode width, however. Four-hundred nanoseconds rise time and 140 nanoseconds fall time were observed for IT= 8 amperes and VD= 200 volts at Tj= 125°C with the 4-mil-wide cathode geometry.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125906155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189193
J. Ruzyllo
The influence of thermal growth conditions on the electrical properties of ultra-thin tunnable silicon dioxide layers on silicon substrate are studied by three independent measuring techniques. It is shown that these properties change considerably with the change in oxidation conditions /temperature, content of water in oxidizing ambient/, although the layers obtained under the different conditions might be of the same thickness. It is proved that in the case of layers discussed in this work only the dry oxidation at the temperature higher than 800°C gives the Si-SiO2structures with sufficiently low densitles of interface and oxide surface charge.
{"title":"Influence of oxidation conditions on electrical properties of ultra-thin SiO2layers","authors":"J. Ruzyllo","doi":"10.1109/IEDM.1977.189193","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189193","url":null,"abstract":"The influence of thermal growth conditions on the electrical properties of ultra-thin tunnable silicon dioxide layers on silicon substrate are studied by three independent measuring techniques. It is shown that these properties change considerably with the change in oxidation conditions /temperature, content of water in oxidizing ambient/, although the layers obtained under the different conditions might be of the same thickness. It is proved that in the case of layers discussed in this work only the dry oxidation at the temperature higher than 800°C gives the Si-SiO2structures with sufficiently low densitles of interface and oxide surface charge.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127496381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189149
K. Morita, T. Yatsuo, M. Okamura, I. Kojima
Large-area, high-voltage thyristors with the ratings of 1500A, 4000V for converters of high-voltage direct current transmission systems have been developed. By improvement in the aluminum diffusion technique, high accuracy of diffusion and long carrier lifetime were attained. To increase the effective conducting area up to eighty percent of the wafer area, the sigma shaped edge contouring technique has been used. A gamma-ray irradiation was used for precise control of the reverse recovery charge. By using a computer aided design which considered the impurity profile, the dynamic characteristics of the device were calculated and the structure was designed.
{"title":"Large-area, high-voltage thyristors for HVDC converter","authors":"K. Morita, T. Yatsuo, M. Okamura, I. Kojima","doi":"10.1109/IEDM.1977.189149","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189149","url":null,"abstract":"Large-area, high-voltage thyristors with the ratings of 1500A, 4000V for converters of high-voltage direct current transmission systems have been developed. By improvement in the aluminum diffusion technique, high accuracy of diffusion and long carrier lifetime were attained. To increase the effective conducting area up to eighty percent of the wafer area, the sigma shaped edge contouring technique has been used. A gamma-ray irradiation was used for precise control of the reverse recovery charge. By using a computer aided design which considered the impurity profile, the dynamic characteristics of the device were calculated and the structure was designed.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131909200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189227
L. Parrillo, G. W. Reutlinger, R. Payne, A. R. Tretola, R. T. Kraetsch
The integrated circuit technology described here has evolved from one incorporating a transistor with a single base implant providing both the active and inactive base regions of the transistor, to one which employs two separate base implants for each region. The sensitivity of the transistor gain to variations in pertinent processing steps is discussed for each procedure. It is found that the double base implantation procedure provides more flexibility in the tailoring and control of transistor gain.
{"title":"The sensitivity of transistor gain to processing variations in an all implanted bipolar technology","authors":"L. Parrillo, G. W. Reutlinger, R. Payne, A. R. Tretola, R. T. Kraetsch","doi":"10.1109/IEDM.1977.189227","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189227","url":null,"abstract":"The integrated circuit technology described here has evolved from one incorporating a transistor with a single base implant providing both the active and inactive base regions of the transistor, to one which employs two separate base implants for each region. The sensitivity of the transistor gain to variations in pertinent processing steps is discussed for each procedure. It is found that the double base implantation procedure provides more flexibility in the tailoring and control of transistor gain.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132018982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189325
A. Carter, R. Goodfellow, R. Davis
High radiance high speed homojunction GaAs and GaInAs VPE LEDs are shown to have frequency responses composed of two parts, a slow response, with cut off at ∼ 100 MHz and a fast response with cut off > 1.5 GHz. These responses are shown to arise from hole recombination in the n-side and electron recombination in the p-side of the junction respectively. The devices are of a sufficiently high radiance that about 80µW can be launched C.W. into a 0.16NA, 85µm core step index fibre at 500MHz, using microlens coupling.
{"title":"High speed GaAs and GaInAs high radiance light emitting diodes","authors":"A. Carter, R. Goodfellow, R. Davis","doi":"10.1109/IEDM.1977.189325","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189325","url":null,"abstract":"High radiance high speed homojunction GaAs and GaInAs VPE LEDs are shown to have frequency responses composed of two parts, a slow response, with cut off at ∼ 100 MHz and a fast response with cut off > 1.5 GHz. These responses are shown to arise from hole recombination in the n-side and electron recombination in the p-side of the junction respectively. The devices are of a sufficiently high radiance that about 80µW can be launched C.W. into a 0.16NA, 85µm core step index fibre at 500MHz, using microlens coupling.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133914873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：