Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189294
J. Nakata, T. Sogo, K. Yamanaka, Y. Mihashi, K. Shirahata
A p-n-p-n temperature-sensitive switching device "Thermosenstor" operatable in the temperature range of -30°C to 150°C has been developed by implanting argon ion to the collector junction of the p-n-p-n structure. Argon ion implantation also permits the device to be less sensitive to the dV/dt triggering as well as to eliminate the on-off switching temperature differential. The construction, characteristics and reliability are described.
{"title":"Temperature-sensitive switching device thermosenstor","authors":"J. Nakata, T. Sogo, K. Yamanaka, Y. Mihashi, K. Shirahata","doi":"10.1109/IEDM.1977.189294","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189294","url":null,"abstract":"A p-n-p-n temperature-sensitive switching device \"Thermosenstor\" operatable in the temperature range of -30°C to 150°C has been developed by implanting argon ion to the collector junction of the p-n-p-n structure. Argon ion implantation also permits the device to be less sensitive to the dV/dt triggering as well as to eliminate the on-off switching temperature differential. The construction, characteristics and reliability are described.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"62 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134226674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189204
R. Zuleeg, J. Notthoff, P. E. Friebertshauser, G. Troeger
Selective ion implantation was utilized to fabricate planar integrated circuits with GaAs enhancement-mode junction field-effect transistors (=E-JFET). A nine-stage ring oscillator was fabricated and served as a test vehicle for assessing the speed-power product for digital applications. Correlation of experimental results with theoretical predictions revealed femto-Joule switching characteristics of short-channel devices with LSI capability. The GaAs depletion-mode metal semiconductor field-effect transistor (=D-MESFET) logic gate performance and IC capability were compared with those of the E-JFET.
{"title":"Femto-Joule, high-speed planar GaAs E-JFET logic","authors":"R. Zuleeg, J. Notthoff, P. E. Friebertshauser, G. Troeger","doi":"10.1109/IEDM.1977.189204","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189204","url":null,"abstract":"Selective ion implantation was utilized to fabricate planar integrated circuits with GaAs enhancement-mode junction field-effect transistors (=E-JFET). A nine-stage ring oscillator was fabricated and served as a test vehicle for assessing the speed-power product for digital applications. Correlation of experimental results with theoretical predictions revealed femto-Joule switching characteristics of short-channel devices with LSI capability. The GaAs depletion-mode metal semiconductor field-effect transistor (=D-MESFET) logic gate performance and IC capability were compared with those of the E-JFET.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133176992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189335
S. Chiang, B. G. Carbajal, G. F. Wakefield
A silicon solar cell was designed which has collecting junctions on both the illuminated and dark sides. The characteristics of the two junctions are interdependent, thus the cell is called a Tandem Junction Cell (TJC). The photoresponse I-V performance of cells was measured with either collection from both sides or collection from only the nonilluminated side. Current collected from both sides of a 100 micrometer thick TJC cell was approximately 46mA/cm2(AMO), with the maximum expected at 30-50 micrometers. Current collected from the nonilluminated side only was 34 mA/cm2for 125 micrometer cell and 45 mA/cm2is expected for 30-50 micrometer thickness. The performance of the TJC is forecast to yield a Vocof 0.6V, Iscof 50 mA/cm2for an efficiency of approximately 18% (AMO, 25°C). Comparison of the experimental and calculated current collection results shows close agreement.
{"title":"High performance thin solar cell","authors":"S. Chiang, B. G. Carbajal, G. F. Wakefield","doi":"10.1109/IEDM.1977.189335","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189335","url":null,"abstract":"A silicon solar cell was designed which has collecting junctions on both the illuminated and dark sides. The characteristics of the two junctions are interdependent, thus the cell is called a Tandem Junction Cell (TJC). The photoresponse I-V performance of cells was measured with either collection from both sides or collection from only the nonilluminated side. Current collected from both sides of a 100 micrometer thick TJC cell was approximately 46mA/cm2(AMO), with the maximum expected at 30-50 micrometers. Current collected from the nonilluminated side only was 34 mA/cm2for 125 micrometer cell and 45 mA/cm2is expected for 30-50 micrometer thickness. The performance of the TJC is forecast to yield a Vocof 0.6V, Iscof 50 mA/cm2for an efficiency of approximately 18% (AMO, 25°C). Comparison of the experimental and calculated current collection results shows close agreement.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189241
D. Houston, M. Adler, E. D. Wolley
A study is made on the effect that various lifetime killing techniques have on: a) the steady state charge distributions within power rectifiers, on b) the open circuit decay of these distributions, and on c) the reverse recovery waveforms for these rectifiers. The charge distributions are measured by free-carrier infrared absorptiont and the results are compared to curves obtained by computer solution of the equations governing charge flow within semiconductors.
{"title":"Measurement and analysis of charge distributions and their decay in fast switching power rectifiers","authors":"D. Houston, M. Adler, E. D. Wolley","doi":"10.1109/IEDM.1977.189241","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189241","url":null,"abstract":"A study is made on the effect that various lifetime killing techniques have on: a) the steady state charge distributions within power rectifiers, on b) the open circuit decay of these distributions, and on c) the reverse recovery waveforms for these rectifiers. The charge distributions are measured by free-carrier infrared absorptiont and the results are compared to curves obtained by computer solution of the equations governing charge flow within semiconductors.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"26 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132454403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189262
M. Kawashima, K. Ohta, S. Kataoka
Foundamental properties of the transferred electron effect of LPE grown GaxIn1-xSb have been measured. Low threshold field, 400-600 V/cm, (0.4 ≤ x ≤ 0.8), low constant domain velocity, 5 × 106cm/sec, (0.55 ≤ x ≤ 0.8 ), and low impact ionization rate in the domain makes this material promising for high speed logic devices. Smaller power-delay poduct, about 1/50 of that of GaAs Gunn logic (20fJ) is expected, using an optimum Ga composition x=0.8.
{"title":"GaxIn1-xSb for high speed transferred electron devices","authors":"M. Kawashima, K. Ohta, S. Kataoka","doi":"10.1109/IEDM.1977.189262","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189262","url":null,"abstract":"Foundamental properties of the transferred electron effect of LPE grown Ga<inf>x</inf>In<inf>1-x</inf>Sb have been measured. Low threshold field, 400-600 V/cm, (0.4 ≤ x ≤ 0.8), low constant domain velocity, 5 × 10<sup>6</sup>cm/sec, (0.55 ≤ x ≤ 0.8 ), and low impact ionization rate in the domain makes this material promising for high speed logic devices. Smaller power-delay poduct, about 1/50 of that of GaAs Gunn logic (20fJ) is expected, using an optimum Ga composition x=0.8.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131865509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189212
J. Fossum, F. Lindholm, C. Sah
This paper describes the physical behavior of a recently proposed device structure, the HLE solar cell [1], that yields substantial increases in the open-circuit voltage and in the power-conversion efficiency of p-n junction silicon solar cells. The structure differs from the conventional cell structure (n+-p) in that it contains a high-low (H-L) junction in the emitter (n+-n-p). For cells having low base resistivities (∼0.1 Ω-cm), efficiency improvements of about 15% at AM1 and about 40% at 50 suns can be expected. The improvement at 50 suns results in an efficiency of about 20% at 27°C.
{"title":"Physics underlying improved efficiency of high-low-junction emitter silicon solar cells","authors":"J. Fossum, F. Lindholm, C. Sah","doi":"10.1109/IEDM.1977.189212","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189212","url":null,"abstract":"This paper describes the physical behavior of a recently proposed device structure, the HLE solar cell [1], that yields substantial increases in the open-circuit voltage and in the power-conversion efficiency of p-n junction silicon solar cells. The structure differs from the conventional cell structure (n+-p) in that it contains a high-low (H-L) junction in the emitter (n+-n-p). For cells having low base resistivities (∼0.1 Ω-cm), efficiency improvements of about 15% at AM1 and about 40% at 50 suns can be expected. The improvement at 50 suns results in an efficiency of about 20% at 27°C.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"1095 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189249
C. Tsironis, H. Beneking
Noise and prebreakdown properties of VPE GaAs MESFETs with and without VPE buffer layer have been investigated. The 1µm gate elements have been produced in the same common manner and with the same geometry starting from the same wafer. With buffer layer no prebreakdown effects are observed. Without buffer layer the instabilities of the DC characteristics, loops and current jumps, as well as the corresponding noise spikes and the noise spectrum can be related to microplasmas activated by avalanche breakdown in the space charge layer of the epi-substrate interface. This effect is located below the drain contact of the MESFETs and is associated by a substrate current flow, no gate current being present. The higher noise factor, also for frequencies higher than X-band, as well as anomalously low values of the breakdown voltage in power devices without buffer layer seems to be affected by that effect.
{"title":"Evidence of avalanche breakdown and microplasma noise in GaAs MESFETs","authors":"C. Tsironis, H. Beneking","doi":"10.1109/IEDM.1977.189249","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189249","url":null,"abstract":"Noise and prebreakdown properties of VPE GaAs MESFETs with and without VPE buffer layer have been investigated. The 1µm gate elements have been produced in the same common manner and with the same geometry starting from the same wafer. With buffer layer no prebreakdown effects are observed. Without buffer layer the instabilities of the DC characteristics, loops and current jumps, as well as the corresponding noise spikes and the noise spectrum can be related to microplasmas activated by avalanche breakdown in the space charge layer of the epi-substrate interface. This effect is located below the drain contact of the MESFETs and is associated by a substrate current flow, no gate current being present. The higher noise factor, also for frequencies higher than X-band, as well as anomalously low values of the breakdown voltage in power devices without buffer layer seems to be affected by that effect.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117104397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189330
F. Luo, D. Davies, W. Hester, T. Brody
The problems encountered in increasing the resolution of a 6" × 6" TFT addressed liquid crystal display from 20 lpi to 30 lpi are described, together with the solutions developed. The major problem relates to the reduced capacitance of the LC element resulting in a lack of frame period storage. Two approaches were utilized: the first consisted of a systematic effort to analyze the factors that influence off "leakage" current in the TFT. As a consequence of this a TFT with leakage current of less than one nanoampere was achieved. The alternate approach was to incorporate an extra 5 pF capacitor in each display element. A layout of the matrix circuit was developed which incorporated the capacitor under the gate bus bar, thereby avoiding a sacrifice in the active area of the display element. Both approaches were successful and good quality displays fabricated. Electrical design considerations, TFT fabrication principles and performance of the resulting 6" × 6" 30 lpi TFT-LC panel will be presented.
{"title":"Performance of a 350 character TFT-LC display panel","authors":"F. Luo, D. Davies, W. Hester, T. Brody","doi":"10.1109/IEDM.1977.189330","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189330","url":null,"abstract":"The problems encountered in increasing the resolution of a 6\" × 6\" TFT addressed liquid crystal display from 20 lpi to 30 lpi are described, together with the solutions developed. The major problem relates to the reduced capacitance of the LC element resulting in a lack of frame period storage. Two approaches were utilized: the first consisted of a systematic effort to analyze the factors that influence off \"leakage\" current in the TFT. As a consequence of this a TFT with leakage current of less than one nanoampere was achieved. The alternate approach was to incorporate an extra 5 pF capacitor in each display element. A layout of the matrix circuit was developed which incorporated the capacitor under the gate bus bar, thereby avoiding a sacrifice in the active area of the display element. Both approaches were successful and good quality displays fabricated. Electrical design considerations, TFT fabrication principles and performance of the resulting 6\" × 6\" 30 lpi TFT-LC panel will be presented.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189276
Z. Pióro
In this paper the results of studies of second breakdown phenomenon in bipolar transistors are presented. Along with this a new feature of second breakdown phenomenon and new method of designing of electronic power circuits based on this feature is discussed.
{"title":"Safe method of designing of power transistors circuits with forward second breakdown taken into consideration","authors":"Z. Pióro","doi":"10.1109/IEDM.1977.189276","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189276","url":null,"abstract":"In this paper the results of studies of second breakdown phenomenon in bipolar transistors are presented. Along with this a new feature of second breakdown phenomenon and new method of designing of electronic power circuits based on this feature is discussed.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124675278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1977.189225
B. Hoefflinger, J. Schneider, G. Zimmer
An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.
{"title":"Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors","authors":"B. Hoefflinger, J. Schneider, G. Zimmer","doi":"10.1109/IEDM.1977.189225","DOIUrl":"https://doi.org/10.1109/IEDM.1977.189225","url":null,"abstract":"An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128389313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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