Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.C-3-02
M. Hasumi
Reduction of optical reflection loss at intermediate region of mechanical stacked samples is discussed in the case of top GaP and bottom Si substrates bonded with epoxy adhesive. Transparent and conductive Indium gallium zinc oxide (IGZO) layers with thicknesses of 102 nm were formed on the bottom surface of GaP and the top surface of Si substrates. The insertion of IGZO layers reduced the optical reflectivity of the stacked sample. It successfully gave high effective optical absorbency for bottom substrates, Aeff of 0.93 for wavelength regions for light in which top GaP substrate was transparent and bottom Si substrate was opaque. High Aeff values were maintained by changing the light incident angle from 0 to 50.
{"title":"Improvement in Effective Optical Absorbency for the Bottom Cells of Mechanical Stacked Multi-Junction Solar Cells","authors":"M. Hasumi","doi":"10.7567/SSDM.2017.C-3-02","DOIUrl":"https://doi.org/10.7567/SSDM.2017.C-3-02","url":null,"abstract":"Reduction of optical reflection loss at intermediate region of mechanical stacked samples is discussed in the case of top GaP and bottom Si substrates bonded with epoxy adhesive. Transparent and conductive Indium gallium zinc oxide (IGZO) layers with thicknesses of 102 nm were formed on the bottom surface of GaP and the top surface of Si substrates. The insertion of IGZO layers reduced the optical reflectivity of the stacked sample. It successfully gave high effective optical absorbency for bottom substrates, Aeff of 0.93 for wavelength regions for light in which top GaP substrate was transparent and bottom Si substrate was opaque. High Aeff values were maintained by changing the light incident angle from 0 to 50.","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79695837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/ssdm.2017.h-3-02
J.M. Song, Sin-Yong Liang, Po-Hao Chiang, S. Huang, Y. Chiu, D. Tarng, C. Hung
{"title":"Enhancement of Direct Cu Bonding via Pulsed Flash Light","authors":"J.M. Song, Sin-Yong Liang, Po-Hao Chiang, S. Huang, Y. Chiu, D. Tarng, C. Hung","doi":"10.7567/ssdm.2017.h-3-02","DOIUrl":"https://doi.org/10.7567/ssdm.2017.h-3-02","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83505099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.N-7-01
S. Matsumoto
{"title":"Removal of reactive-ion-etching damage from n-GaN surface using a photoelectrochemical process","authors":"S. Matsumoto","doi":"10.7567/SSDM.2017.N-7-01","DOIUrl":"https://doi.org/10.7567/SSDM.2017.N-7-01","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89301771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.PS-13-05
J. Pyo
{"title":"Highly Sensitive Double-Gate Thin-Film Transistor pH Sensors with Solution-Processed Carbon-Nanotube Networks Channel and AlO x Gate Insulator","authors":"J. Pyo","doi":"10.7567/SSDM.2017.PS-13-05","DOIUrl":"https://doi.org/10.7567/SSDM.2017.PS-13-05","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87397679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.K-5-01
S. Müller
10 years have passed since ferroelectricity in hafnium oxide was discovered for the first time. This fundamental breakthrough has initiated significant R&D activities in both industry and in academia. This paper summarizes the potential of ferroelectric HfO2 (FE-HfO2) for memory applications with particular focus on highly scaled CMOS technology nodes. It illustrates that FE-HfO2 might finally enable the entrance of ferroelectric memories into mass markets.
{"title":"CMOS Compatible Ferroelectric Devices for Beyond 1X nm Technology Nodes","authors":"S. Müller","doi":"10.7567/SSDM.2017.K-5-01","DOIUrl":"https://doi.org/10.7567/SSDM.2017.K-5-01","url":null,"abstract":"10 years have passed since ferroelectricity in hafnium oxide was discovered for the first time. This fundamental breakthrough has initiated significant R&D activities in both industry and in academia. This paper summarizes the potential of ferroelectric HfO2 (FE-HfO2) for memory applications with particular focus on highly scaled CMOS technology nodes. It illustrates that FE-HfO2 might finally enable the entrance of ferroelectric memories into mass markets.","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89791726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.PS-7-11
P. Zhou, Xuejun Xu, Y. Kanda, S. Matsushita, K. Sawano, T. Maruizumi
{"title":"The Resonant Phenomenon in the PL Spectra Measured in the Tensile-Strained Ge Microbridges","authors":"P. Zhou, Xuejun Xu, Y. Kanda, S. Matsushita, K. Sawano, T. Maruizumi","doi":"10.7567/SSDM.2017.PS-7-11","DOIUrl":"https://doi.org/10.7567/SSDM.2017.PS-7-11","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76784536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.C-3-01
K. Makita, H. Mizuno, R. Oshima, T. Tayagaki, Masaaki Baba, Noboru Yamada, H. Takato, T. Sugaya
Multi-junction (MJ) solar cells have a practical solution to consist with high efficiency and low cost. This paper shows the demonstrations of a GaAs/Si MJ solar cells with mechanical stacking method. Our key technology is the direct bonding using conductive nanoparticle alignment, which is named “Smart Stack” technology. Using this technology, we fabricated an InGaP/GaAs/Si 3-junction solar cell and observed the efficiency of 24.71% (AM1.5g). According to our theoretical prediction, these efficiencies can be improved over 30% under the optimized structure design. In addition, we examined the cost analysis of the GaAs/Si MJ module. Under the low concentration, the cost attains the competitive level (module cost with lens_ <0.4$/W). The obtained results show the possibility of GaAs/ Si MJ solar cells as next generation solar cell.
多结(MJ)太阳能电池具有高效率和低成本的实用性。本文用机械叠层法对GaAs/Si MJ太阳能电池进行了演示。我们的关键技术是利用导电纳米颗粒定向直接键合，被称为“智能堆栈”技术。利用该技术制备了InGaP/GaAs/Si三结太阳能电池，效率达到24.71% (AM1.5g)。根据我们的理论预测，经过优化的结构设计，这些效率可以提高30%以上。此外，我们研究了GaAs/Si MJ模块的成本分析。在低集中度下，成本达到竞争水平(透镜成本<0.4美元/W)。研究结果表明，GaAs/ Si MJ太阳能电池有可能成为下一代太阳能电池。
{"title":"Next-generation High Efficiency and Low Cost GaAs/Si Multijunction Solar Cells with Smart Stack Technology","authors":"K. Makita, H. Mizuno, R. Oshima, T. Tayagaki, Masaaki Baba, Noboru Yamada, H. Takato, T. Sugaya","doi":"10.7567/SSDM.2017.C-3-01","DOIUrl":"https://doi.org/10.7567/SSDM.2017.C-3-01","url":null,"abstract":"Multi-junction (MJ) solar cells have a practical solution to consist with high efficiency and low cost. This paper shows the demonstrations of a GaAs/Si MJ solar cells with mechanical stacking method. Our key technology is the direct bonding using conductive nanoparticle alignment, which is named “Smart Stack” technology. Using this technology, we fabricated an InGaP/GaAs/Si 3-junction solar cell and observed the efficiency of 24.71% (AM1.5g). According to our theoretical prediction, these efficiencies can be improved over 30% under the optimized structure design. In addition, we examined the cost analysis of the GaAs/Si MJ module. Under the low concentration, the cost attains the competitive level (module cost with lens_ <0.4$/W). The obtained results show the possibility of GaAs/ Si MJ solar cells as next generation solar cell.","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78172204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/SSDM.2017.D-1-03
Y. Shih, Meng-Yin Hsu, Y. King, C. Lin
A fully-compatible Via RRAM cell in 16nm CMOS FinFET logic process has been successfully demonstrated for a high-density and low-cost logic nonvolatile memory (NVM) applications. In this new cell, the transition metal layers are form at both sides of a Via, given two storage bits for one via. In addition to its compact cell area (14nmx32nm), the twin-bit Via RRAM cell features low voltage operation, large read window, excellent data retention and cycling capability. As a promising embedded NVM solution, the twin-bit Via RRAM cell is highly scalable with fine alignment and nano-scale feature length become possible in advanced CMOS technologies. Introduction With low-power, high-compatibility and high programming speed, RRAMs are regarded as one of the possible solutions for logic NVM applications under intense investigations. Many different structure of RRAMs with low operation voltage, compact cell size and fast writing speed are reported in many studies [1-2]. Most of these cells are demonstrated in planar CMOS logic processes [3-4] or by incorporating transition metal oxide (TMO) layer in backend of the line processes [5]. With CMOS technology node advancing, the planar logic process has been replaced by 3D FinFET process for enhanced gate control, leading to new challenges for the development of logic NVMs. Novel structures for 3D FinFET process is needed to develop fully-compatible NVM cells. In the study, the twin-bit RRAM with high density, low power and high transition speed is successful implemented in pure 16nm FinFET CMOS logic process. With TMO layers on both sides of a Via, served as the twin resistive switching nodes, a novel RRAM cell has been proposed and demonstrated in this structure. Cell Structure and Operation Principle The proposed twin-bit Via RRAM cell is fabricated by standard FinFET CMOS logic process. The structure of Via RRAM is illustrated in figure 1(a). As shown in the picture, the cell consist of two storage nodes both side of Via1. The other electrode, M1, is then connected to an nchannel FinFET which control the set/reset and read of the selected operation. The TMO layer is consisted of TaON and SiO2 at the sidewall of Vias, sandwiched between Via and Metal electrodes. By placing a single via between closely placed metal 1, the twin-bit RRAM cells are easily formed. Based on previous studies on resistive switching mechanisms in oxygen vacancy based RRAMs [6-7], the low resistance path is formed by applying a large enough electric field across TMO layer, which established a conductive filaments (CF). Reversely, with large reset current through the low resistance path, the existing CF will then be partially broken apart by the recombination of oxygen vacancies. The twin-bit Via RRAM cell is placed in a 2x2 array with two RRAM sharing a single Via between the right and left bit, as illustrated in Figure 1(b). A 2x2 array layout of the twin-bit RRAM in Figure 1(c) showing how the two cells sharing one via connection t
{"title":"Twin-bit Via RRAM in 16nm FinFET Logic Technologies","authors":"Y. Shih, Meng-Yin Hsu, Y. King, C. Lin","doi":"10.7567/SSDM.2017.D-1-03","DOIUrl":"https://doi.org/10.7567/SSDM.2017.D-1-03","url":null,"abstract":"A fully-compatible Via RRAM cell in 16nm CMOS FinFET logic process has been successfully demonstrated for a high-density and low-cost logic nonvolatile memory (NVM) applications. In this new cell, the transition metal layers are form at both sides of a Via, given two storage bits for one via. In addition to its compact cell area (14nmx32nm), the twin-bit Via RRAM cell features low voltage operation, large read window, excellent data retention and cycling capability. As a promising embedded NVM solution, the twin-bit Via RRAM cell is highly scalable with fine alignment and nano-scale feature length become possible in advanced CMOS technologies. Introduction With low-power, high-compatibility and high programming speed, RRAMs are regarded as one of the possible solutions for logic NVM applications under intense investigations. Many different structure of RRAMs with low operation voltage, compact cell size and fast writing speed are reported in many studies [1-2]. Most of these cells are demonstrated in planar CMOS logic processes [3-4] or by incorporating transition metal oxide (TMO) layer in backend of the line processes [5]. With CMOS technology node advancing, the planar logic process has been replaced by 3D FinFET process for enhanced gate control, leading to new challenges for the development of logic NVMs. Novel structures for 3D FinFET process is needed to develop fully-compatible NVM cells. In the study, the twin-bit RRAM with high density, low power and high transition speed is successful implemented in pure 16nm FinFET CMOS logic process. With TMO layers on both sides of a Via, served as the twin resistive switching nodes, a novel RRAM cell has been proposed and demonstrated in this structure. Cell Structure and Operation Principle The proposed twin-bit Via RRAM cell is fabricated by standard FinFET CMOS logic process. The structure of Via RRAM is illustrated in figure 1(a). As shown in the picture, the cell consist of two storage nodes both side of Via1. The other electrode, M1, is then connected to an nchannel FinFET which control the set/reset and read of the selected operation. The TMO layer is consisted of TaON and SiO2 at the sidewall of Vias, sandwiched between Via and Metal electrodes. By placing a single via between closely placed metal 1, the twin-bit RRAM cells are easily formed. Based on previous studies on resistive switching mechanisms in oxygen vacancy based RRAMs [6-7], the low resistance path is formed by applying a large enough electric field across TMO layer, which established a conductive filaments (CF). Reversely, with large reset current through the low resistance path, the existing CF will then be partially broken apart by the recombination of oxygen vacancies. The twin-bit Via RRAM cell is placed in a 2x2 array with two RRAM sharing a single Via between the right and left bit, as illustrated in Figure 1(b). A 2x2 array layout of the twin-bit RRAM in Figure 1(c) showing how the two cells sharing one via connection t","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78412688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/ssdm.2017.g-2-01
H. Hirayama
{"title":"Current Status and Future of III-Nitride Ultraviolet and THz Emitters","authors":"H. Hirayama","doi":"10.7567/ssdm.2017.g-2-01","DOIUrl":"https://doi.org/10.7567/ssdm.2017.g-2-01","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75650185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-28DOI: 10.7567/ssdm.2017.ps-13-02
R. Nezasa
{"title":"Fabrication of a Si Nanowire MOS Capacitor for the Application to Energy Storage Devices","authors":"R. Nezasa","doi":"10.7567/ssdm.2017.ps-13-02","DOIUrl":"https://doi.org/10.7567/ssdm.2017.ps-13-02","url":null,"abstract":"","PeriodicalId":22504,"journal":{"name":"The Japan Society of Applied Physics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74475752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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