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Detection of electron trapping/detrapping in MoS 2 FET by high time-resolved I-V measurement 用高时间分辨I-V测量方法检测MoS 2 FET中的电子捕获/去捕获
Pub Date : 2017-08-08 DOI: 10.7567/ssdm.2017.ps-13-22
K. Taniguchi
For exploring the origin for the interface states in MoS2 FET, the transient response of MOS capacitor to ultra-fast pulsed top gate voltage was studied with high time resolution current measurement system. The difference of time constant originated from trapping and detrapping of electrons on interface states was detected, which cannot be measured in C-V measurement.
为了探索MoS2场效应管中界面态的来源,利用高时间分辨率电流测量系统研究了MOS电容对超快脉冲顶栅电压的瞬态响应。由于电子在界面态上的俘获和脱陷导致了时间常数的差异,这在C-V测量中是无法测量的。
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引用次数: 0
Sodium Dodecyl Sulfate-Functionalized Carbon Nanotube / Polydimethylsiloxane Composites for High Performance Triboelectric Nanogenerator 十二烷基硫酸钠-功能化碳纳米管/聚二甲基硅氧烷复合材料用于高性能摩擦电纳米发电机
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-13-24
N. Ketama
This research presents a fabrication of triboelectric nanogenerator (TENG) using the sodium dodecyl sulfate (SDS)-functionalized carbon nanotube (CNT) / polydimethylsiloxane(PDMS) composites (SDS/CNT/PDMS) as a negative electrode and polyethylene terephthalate / indium tin oxide (PET/ITO) as a positive electrode. The effect of CNT concentration and the SDS concentration were on TENG performance were investigated. Experimental results indicate that the SDS/CNT/PDMS is an effective electrode to enhance the output voltage of TENG with a maximum voltage of 66.8 V enabled an approximately 6-fold improvement in voltage output compared to the pristine PDMS. CNT may help to the high conductivity and flexibility of CNT, resulting in fast charge transfer and fast shape-recovery, while SDS may help to increase charge density and furthermore CNT dispersion.
本研究以十二烷基硫酸钠(SDS)功能化碳纳米管(CNT) /聚二甲基硅氧烷(PDMS)复合材料(SDS/CNT/PDMS)为负极,聚对苯二甲酸乙二醇酯/氧化铟锡(PET/ITO)为正极,制备了摩擦电纳米发电机(TENG)。考察了碳纳米管浓度和SDS浓度对TENG性能的影响。实验结果表明,SDS/CNT/PDMS是提高TENG输出电压的有效电极,最大电压为66.8 V,与原始PDMS相比,输出电压提高了约6倍。碳纳米管可能有助于碳纳米管的高导电性和柔韧性,从而实现快速的电荷转移和快速的形状恢复,而SDS可能有助于增加电荷密度和进一步的碳纳米管分散。
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引用次数: 0
TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation 0.3 V工作时平均亚阈值摆幅小于60 mV/dec的平面单栅硅隧道场效应管的TCAD仿真
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-3-14
K. Kukita, T. Uechi, J. Shimokawa, M. Goto, Y. Yokota, S. Kawanaka, T. Tanamoto, M. Koyama, H. Tanimoto, S. Takagi
TCAD simulations have been performed to optimize well designed planar single-gate silicon (Si) vertical tunneling junction field effect transistor (VTFET) with average subthreshold swing (S.S.) less than 60 mV/dec for 0.3 V (=Vgs=Vds) operation. By scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length Lov, it achieved both on-current (Ion) greater than 1.0 A/m and low average S.S. without pocket doping for forming tunnel junction in conventional VTFET.
利用TCAD仿真优化了设计良好的平面单门硅垂直隧道结场效应晶体管(VTFET),在0.3 V (=Vgs=Vds)工作下,平均亚阈值摆幅(S.S.)小于60 mV/dec。通过缩放等效氧化物厚度(EOT)和增加栅极-源重叠长度Lov,可以在不掺杂口袋的情况下实现大于1.0A/m的导通电流和较低的平均S.S.,从而实现传统VTFET隧道结的形成。
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引用次数: 0
Programming Current Reduction in GeS 2 +Sb 2 Te 3 Based Phase-Change Memory 基于ges2 + sb2te 3相变存储器的编程电流减小
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.A-8-05
J. Kluge, A. Verdy, G. Navarro, S. Blonkowski, V. Sousa, P. Kowalczyk, M. Bernard, N. Bernier, G. Bourgeois, N. Castellani, P. Noé, E. Nowak, L. Perniola
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引用次数: 0
Experimental Investigation of the Contact Resistance of Graphene/MoS2 Interface Treated with O2 Plasma O2等离子体处理石墨烯/MoS2界面接触电阻的实验研究
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-13-20
Q. Lu
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引用次数: 2
Hot-carrier Induced Drastic Off-state Leakage Current Degradation in STI-based N-channel LDMOS 热载流子诱导的si基n沟道LDMOS断态泄漏电流急剧下降
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-3-13
Keita Takahashi, K. Komatsu, Toshihiro Sakamoto, K. Kimura, F. Matsuoka
Abstract In this paper, hot-carrier (HC) induced drastic off-state leakage current (Ioff) degradation for the LDMOS is found and the mechanism is also investigated in detail. Continuous on-state drain current flow of the LDMOS generates the HC which is trapped in the STI, and causes the drastic increase of the Ioff for the LDMOS. Therefore, HC induced drastic Ioff increase should be taken into account for the LDMOS design.
摘要本文发现了热载流子(HC)引起的LDMOS的断态漏电流(Ioff)急剧下降,并对其机理进行了详细的研究。LDMOS的持续导通漏电流产生的HC被困在STI中,导致LDMOS的Ioff急剧增加。因此,在设计LDMOS时应考虑到HC引起的剧烈的off增加。
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引用次数: 0
First-principles study on domain boundary of MoS 2 : Origin of band bending MoS 2畴边界的第一性原理研究:带弯曲的起源
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-13-21
T. Kaneko
Using first-principles calculations based on density functional theory, electronic structure of domain boundary of MoS2 in which same polar edges are faced each other are investigated theoretically. We also find that the up-shift of energy bands at the domain boundaries are caused by charge accumulation. For such change in the energy bands, the defect levels at the domain boundaries play a decisive role.
利用基于密度泛函理论的第一性原理计算,从理论上研究了相同极边相互面对的二硫化钼畴边界的电子结构。我们还发现,畴边界处能带的上移是由电荷积累引起的。对于这种能带变化,畴边界处的缺陷能级起着决定性的作用。
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引用次数: 0
Contact Properties of SWNT TCEs via the Microwave Treatment 微波处理SWNT tce的接触特性
Pub Date : 2017-08-08 DOI: 10.7567/ssdm.2017.ps-13-25
K. H. Kim
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引用次数: 0
Optimizing MOS-Gated Thyristor using Voltage-based Equivalent Circuit Model for Designing Steep Subthreshold Slope PN-Body Tied SOI FET 基于电压等效电路模型优化mos门控晶闸管设计陡亚阈斜率pn体捆扎SOI场效应管
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.E-5-03
D. Ueda
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引用次数: 0
A first principles study on the C=C defects near SiC/SiO 2 interface: Defect passivation by double bond saturation SiC/ sio2界面附近C=C缺陷的第一性原理研究:双键饱和缺陷钝化
Pub Date : 2017-08-08 DOI: 10.7567/SSDM.2017.PS-14-11
N. Tajima
We performed first principles calculations to study the C=C defects near SiC/SiO2 interface, and demonstrated that the intra-gap defect levels could be removed by changing the C=C double bond to a C-C single bond.
通过第一性原理计算研究了SiC/SiO2界面附近的C=C缺陷,并证明了通过将C=C双键改为C-C单键可以消除间隙内的缺陷。
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引用次数: 0
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The Japan Society of Applied Physics
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