Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909633
J. Qayyum, J. Albrecht, J. Papapolymerou, A. Ulusoy
This paper presents a 28-60 GHz multi-band low-noise amplifier (LNA) suitable for Ka-, Q- and V-band applications, which is realized in $0.13-mu m$ SiGe BiCMOS technology. The proposed LNA achieves its multi-band performance by employing a T-type matching topology as inter-stage matching network (IMN). The LNA has a measured gain of 14.5 dB and 14.1 dB, and simulated noise Figure (NF) of 2.4 dB and 3.4 dB at 28 and 60 GHz with a mean NF of 2.9 dB. The input return loss is less than -10 dB from 22-67 GHz. The chip occupies an area of 0.15 mm2t and consumes 27 mW from a 2.5 V power supply. To the authors’ knowledge the realized LNA is superior than any state-of-the-art LNAs in similar silicon technologies.
{"title":"A 28-60 GHz SiGe HBT LNA with 2.4-3.4 dB Noise Figure","authors":"J. Qayyum, J. Albrecht, J. Papapolymerou, A. Ulusoy","doi":"10.23919/EuMIC.2019.8909633","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909633","url":null,"abstract":"This paper presents a 28-60 GHz multi-band low-noise amplifier (LNA) suitable for Ka-, Q- and V-band applications, which is realized in $0.13-mu m$ SiGe BiCMOS technology. The proposed LNA achieves its multi-band performance by employing a T-type matching topology as inter-stage matching network (IMN). The LNA has a measured gain of 14.5 dB and 14.1 dB, and simulated noise Figure (NF) of 2.4 dB and 3.4 dB at 28 and 60 GHz with a mean NF of 2.9 dB. The input return loss is less than -10 dB from 22-67 GHz. The chip occupies an area of 0.15 mm2t and consumes 27 mW from a 2.5 V power supply. To the authors’ knowledge the realized LNA is superior than any state-of-the-art LNAs in similar silicon technologies.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909641
S. Piotrowicz, C. Lacam, N. Michel, M. Oualli, O. Patard, S. Delage, C. Potier, J. Jacquet, J. Nallatamby, M. Prigent, P. Altuntas, E. Chartier, C. Dua, P. Gamarra
This article presents the performances obtained on a $0.15 mu mathrm{m}$ gate length InAlGaN/GaN HEMT technology on SiC substrate. This technology uses a back-barrier buffer layer to ensure the confinement of electrons in the channel, which minimizes variations of the drain current when the HEMT devices are submitted to DC or RF pulses. Measurements of the drain current recovery time are shown when the devices are submitted to VDS, VGS or microwave RF pulses. A comparison with an AlGaN/GaN HEMT structure designed with an iron doped buffer layer is proposed.
本文介绍了在SiC衬底上以$0.15 mu mathm {m}$栅长InAlGaN/GaN HEMT技术所获得的性能。该技术使用后阻挡缓冲层来确保通道中电子的限制，从而最大限度地减少HEMT器件在直流或射频脉冲下漏极电流的变化。当器件被提交到VDS, VGS或微波射频脉冲时，显示漏极电流恢复时间的测量结果。提出了与掺杂铁缓冲层设计的AlGaN/GaN HEMT结构的比较。
{"title":"Drain Current Recovery Time Analyses of InAlGaN/GaN HEMTs Realized with a Back-Barrier Buffer Layer","authors":"S. Piotrowicz, C. Lacam, N. Michel, M. Oualli, O. Patard, S. Delage, C. Potier, J. Jacquet, J. Nallatamby, M. Prigent, P. Altuntas, E. Chartier, C. Dua, P. Gamarra","doi":"10.23919/EuMIC.2019.8909641","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909641","url":null,"abstract":"This article presents the performances obtained on a $0.15 mu mathrm{m}$ gate length InAlGaN/GaN HEMT technology on SiC substrate. This technology uses a back-barrier buffer layer to ensure the confinement of electrons in the channel, which minimizes variations of the drain current when the HEMT devices are submitted to DC or RF pulses. Measurements of the drain current recovery time are shown when the devices are submitted to VDS, VGS or microwave RF pulses. A comparison with an AlGaN/GaN HEMT structure designed with an iron doped buffer layer is proposed.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909513
G. Formicone, J. Custer
An internally matched 70 W class J GaN power amplifier for C-band radar remote sensing applications is demonstrated. The amplifier achieves 50% power added efficiency at 7900 ± 10 MHz, using a pulsed waveform with 30% duty cycle. The amplifier features a segmented matching network inside a metal flange package to synthesize a reactance at the fundamental and operates in class J mode
{"title":"A Segmented Internally-Matched Class J GaN Power Amplifier for High Duty Cycle C-Band Radars","authors":"G. Formicone, J. Custer","doi":"10.23919/EuMIC.2019.8909513","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909513","url":null,"abstract":"An internally matched 70 W class J GaN power amplifier for C-band radar remote sensing applications is demonstrated. The amplifier achieves 50% power added efficiency at 7900 ± 10 MHz, using a pulsed waveform with 30% duty cycle. The amplifier features a segmented matching network inside a metal flange package to synthesize a reactance at the fundamental and operates in class J mode","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131898595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909576
Arnaud Collet, O. Llopis, G. Cibiel, Erie Tournier
A frequency synthesis technique based on the division of a coupled optoelectronic oscillator (COEO) reference is presented. This technique overcomes one of the main issues of the most common frequency synthesis technique, namely the phase locked loop (PLL): the inherent phase noise degradation of frequency multiplication. In order to keep the benefits of the frequency division technique, residual phase noise of the dividers has to be reduced as much as possible. This article discusses the results of two digital dividers, a divider by 2 and a divider by 3, both with a 30 GHz COEO reference.
{"title":"Low Phase Noise Digital Division by 2 and by 3 of a 30 GHz Coupled Optoelectronic Oscillator","authors":"Arnaud Collet, O. Llopis, G. Cibiel, Erie Tournier","doi":"10.23919/EuMIC.2019.8909576","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909576","url":null,"abstract":"A frequency synthesis technique based on the division of a coupled optoelectronic oscillator (COEO) reference is presented. This technique overcomes one of the main issues of the most common frequency synthesis technique, namely the phase locked loop (PLL): the inherent phase noise degradation of frequency multiplication. In order to keep the benefits of the frequency division technique, residual phase noise of the dividers has to be reduced as much as possible. This article discusses the results of two digital dividers, a divider by 2 and a divider by 3, both with a 30 GHz COEO reference.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115733388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909637
Yu-Teng Chang, Tai-Yi Lin, Hsin-Chia Lu
In this paper, we propose a low power wideband CMOS low noise amplifier (LNA) at V-band. This work is the first time using the double-transformer-coupling technique to achieve a wideband design. The major difference between proposed and traditional wideband LNA is the use of double-transformer-coupling technique and T-type matching method to control the upper/lower 3-dB frequencies. In addition, the combination of double transformer and current re-used technique not only can save dc power and die area but also can implement the gm-boost technique to improve the overall transconductance. The peak gain of LNA is 21.6 dB and has a fractional 3-dB bandwidth of 35.2 % which is from 46.5 to 65.8 GHz. Across-frequency ranges from 50 to 66 GHz, the measured the N.F., IP1dB, and IIP3 are better than 7.28 dB, -21.6 dBm and -13.16 dBm, respectively. The total dc power consumption is only 16.3 mW for 1.2 V supply voltage. To our best knowledge, this LNA has the wider fractional bandwidth, lower dc power, more compact die area and excellent FoM at V-band among CMOS LNAs.
{"title":"A Low Power Wideband V-Band LNA Using Double-Transformer-Coupling Technique and T-Type Matching in 90nm CMOS","authors":"Yu-Teng Chang, Tai-Yi Lin, Hsin-Chia Lu","doi":"10.23919/EuMIC.2019.8909637","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909637","url":null,"abstract":"In this paper, we propose a low power wideband CMOS low noise amplifier (LNA) at V-band. This work is the first time using the double-transformer-coupling technique to achieve a wideband design. The major difference between proposed and traditional wideband LNA is the use of double-transformer-coupling technique and T-type matching method to control the upper/lower 3-dB frequencies. In addition, the combination of double transformer and current re-used technique not only can save dc power and die area but also can implement the gm-boost technique to improve the overall transconductance. The peak gain of LNA is 21.6 dB and has a fractional 3-dB bandwidth of 35.2 % which is from 46.5 to 65.8 GHz. Across-frequency ranges from 50 to 66 GHz, the measured the N.F., IP1dB, and IIP3 are better than 7.28 dB, -21.6 dBm and -13.16 dBm, respectively. The total dc power consumption is only 16.3 mW for 1.2 V supply voltage. To our best knowledge, this LNA has the wider fractional bandwidth, lower dc power, more compact die area and excellent FoM at V-band among CMOS LNAs.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115877608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909398
Yanlu Wang, M. Wei, R. Negra
This paper presents an ultralow power 1-bit digitally controlled oscillator (DCO) for the application in high data-rate FSK transmitters. To design a low-power DCO, minimising the loss of the LC tank is very critical. Hence, a high quality factor (Q) multifinger capacitor and a high-Q centre-tapped inductor are proposed and designed. Simulated Q of the capacitor is more than 45 from 70 GHz to 80 GHz. It is at least 4.5 times higher than a typical metal-insulator-metal capacitor (MIMCAP). The proposed DCO based on the designed high-Q passives is fabricated in standard 65 nm CMOS. Measured foSC are 74. 1GHz and 76.7 GHz in the on-and off-state of the switch, respectively. It consumes only 3.15 mW DC power from a supply of 0. 75V which to the authors’ knowledge is the lowest power consumption reported so far in this frequency range.
{"title":"Ultralow Power, 3.15 mW, 76.7 GHz Digitally Controlled Oscillator in 65 nm CMOS for High Data-Rate Application","authors":"Yanlu Wang, M. Wei, R. Negra","doi":"10.23919/EuMIC.2019.8909398","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909398","url":null,"abstract":"This paper presents an ultralow power 1-bit digitally controlled oscillator (DCO) for the application in high data-rate FSK transmitters. To design a low-power DCO, minimising the loss of the LC tank is very critical. Hence, a high quality factor (Q) multifinger capacitor and a high-Q centre-tapped inductor are proposed and designed. Simulated Q of the capacitor is more than 45 from 70 GHz to 80 GHz. It is at least 4.5 times higher than a typical metal-insulator-metal capacitor (MIMCAP). The proposed DCO based on the designed high-Q passives is fabricated in standard 65 nm CMOS. Measured foSC are 74. 1GHz and 76.7 GHz in the on-and off-state of the switch, respectively. It consumes only 3.15 mW DC power from a supply of 0. 75V which to the authors’ knowledge is the lowest power consumption reported so far in this frequency range.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"564 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909666
E. McCune, Q. Diduck
While users of spectrum pay large sums of money for spectrum access, they do not sell spectrum to their customers but rather they market data rates. Developing radio technologies that maximize data rate within a finite spectrum slice is a very important goal to such spectrum access businesses. This requires radios to provide high values of spectrum efficiency (bits per second per Hertz-bandwidth (bps/Hz)). This paper is the first to introduce a conventional Nyquist filtered 4096-QAM signal implemented with a switching-circuit based transmitter. Even by having no circuit linearity in the RF path and using polar modulation, the reported signal quality measurements confirm less than 0.9% error-vector magnitude for this 12 bps/Hz constellation. Signal ACLR is -54dB, peak output power is 2.5 watts, and the transmitter efficiency exceeds 50% when modulated and including all linearization power. The limits of using EVM as a signal quality metric are presented and discussed.
{"title":"4096-QAM Microwave Transmitter Providing Efficiency Exceeding 50% and EVM Below 1%","authors":"E. McCune, Q. Diduck","doi":"10.23919/EuMIC.2019.8909666","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909666","url":null,"abstract":"While users of spectrum pay large sums of money for spectrum access, they do not sell spectrum to their customers but rather they market data rates. Developing radio technologies that maximize data rate within a finite spectrum slice is a very important goal to such spectrum access businesses. This requires radios to provide high values of spectrum efficiency (bits per second per Hertz-bandwidth (bps/Hz)). This paper is the first to introduce a conventional Nyquist filtered 4096-QAM signal implemented with a switching-circuit based transmitter. Even by having no circuit linearity in the RF path and using polar modulation, the reported signal quality measurements confirm less than 0.9% error-vector magnitude for this 12 bps/Hz constellation. Signal ACLR is -54dB, peak output power is 2.5 watts, and the transmitter efficiency exceeds 50% when modulated and including all linearization power. The limits of using EVM as a signal quality metric are presented and discussed.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116899484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909659
F. Barrera, A. Siligaris, B. Blampey, J. González-Jiménez
This paper presents a 4-ways passive power splitter/combiner based on Wilkinson dividers implemented in the BEOL of a conventional 28nm bulk CMOS process achieving better than-20 dB of isolation and 2.5 dB of insertion loss across 25 GHz of band at 140 GHz
{"title":"A D-band 4-ways power splitter/combiner implemented on a 28nm bulk CMOS process","authors":"F. Barrera, A. Siligaris, B. Blampey, J. González-Jiménez","doi":"10.23919/EuMIC.2019.8909659","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909659","url":null,"abstract":"This paper presents a 4-ways passive power splitter/combiner based on Wilkinson dividers implemented in the BEOL of a conventional 28nm bulk CMOS process achieving better than-20 dB of isolation and 2.5 dB of insertion loss across 25 GHz of band at 140 GHz","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909607
C. Wang, Y. Lin, C. Kuo, M. Lee, J. Yao, T. J. Huang, H. Hsu, E. Chang
An enhancement-mode tri-gate InAs HEMT is investigated for low noise application in this paper. The 3-D trigate structure is sidewall-gate-metal connected to InAlAs layers, the gate connection to the InAlAs layers increases their potential to the positive direction with increasing the gate bias, resulting gate control ability enhancement. Compared with planar device, the tri-gate device shows high transconductance and low noise figure. The enhancement-mode tri-gate device exhibits excellent low noise Figure with less than 3.5 dB when the device operation frequency range of 18 GHz to 50 GHz.
{"title":"Study of Enhancement-Mode Tri-Gate InAs HEMTs for Low Noise Application","authors":"C. Wang, Y. Lin, C. Kuo, M. Lee, J. Yao, T. J. Huang, H. Hsu, E. Chang","doi":"10.23919/EuMIC.2019.8909607","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909607","url":null,"abstract":"An enhancement-mode tri-gate InAs HEMT is investigated for low noise application in this paper. The 3-D trigate structure is sidewall-gate-metal connected to InAlAs layers, the gate connection to the InAlAs layers increases their potential to the positive direction with increasing the gate bias, resulting gate control ability enhancement. Compared with planar device, the tri-gate device shows high transconductance and low noise figure. The enhancement-mode tri-gate device exhibits excellent low noise Figure with less than 3.5 dB when the device operation frequency range of 18 GHz to 50 GHz.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129655609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909628
M. Schmidt-Szatowski
Certain industry-standard transistor models exhibit nonreciprocity of capacitances in the subthreshold mode. This behavior violates the law of energy conservation and impedes stability analysis of MMIC circuits, especially class C amplifiers. We circumvented this limitation by introducing a new modeling approach: energy-based capacitance modeling. Instead of modeling capacitances or charges, we model the electrical energy stored in the transistor. From this quantity we derive expressions for charges and capacitances by means of differentiation. We applied this approach to an LDMOS device and achieved very good accuracy, while maintaining charge and energy conservation.
{"title":"Energy-Based Capacitance Modeling for Field-Effect Transistor Stability Analysis","authors":"M. Schmidt-Szatowski","doi":"10.23919/EuMIC.2019.8909628","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909628","url":null,"abstract":"Certain industry-standard transistor models exhibit nonreciprocity of capacitances in the subthreshold mode. This behavior violates the law of energy conservation and impedes stability analysis of MMIC circuits, especially class C amplifiers. We circumvented this limitation by introducing a new modeling approach: energy-based capacitance modeling. Instead of modeling capacitances or charges, we model the electrical energy stored in the transistor. From this quantity we derive expressions for charges and capacitances by means of differentiation. We applied this approach to an LDMOS device and achieved very good accuracy, while maintaining charge and energy conservation.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127544873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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