Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909621
S. Redois, E. Kerhervé, A. Ghiotto, B. Louis, V. Petit, Y. Mancuso
This paper presents a compact quasi inverse class-F highly efficient power amplifier (PA) based on the 130 nm SiGe technology. The purpose is to drive high output power with high power added efficiency (PAE) over the X-band, while ensuring a good amplitude and phase linearity. To do that, a differential cascode topology with low base impedance has been used. Measured results exhibit 51.8% peak PAE with 25.7 dBm output power at 9 GHz. To our knowledge, this PA demonstrates the highest efficiency with linear behaviour among Si-based X-band power amplifiers found in literature.
{"title":"Quasi Inverse Class-F X-Band Highly Efficient Power Amplifier with 51.8% Peak PAE in SiGe","authors":"S. Redois, E. Kerhervé, A. Ghiotto, B. Louis, V. Petit, Y. Mancuso","doi":"10.23919/EuMIC.2019.8909621","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909621","url":null,"abstract":"This paper presents a compact quasi inverse class-F highly efficient power amplifier (PA) based on the 130 nm SiGe technology. The purpose is to drive high output power with high power added efficiency (PAE) over the X-band, while ensuring a good amplitude and phase linearity. To do that, a differential cascode topology with low base impedance has been used. Measured results exhibit 51.8% peak PAE with 25.7 dBm output power at 9 GHz. To our knowledge, this PA demonstrates the highest efficiency with linear behaviour among Si-based X-band power amplifiers found in literature.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134090050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909407
Z. Griffith, M. Urteaga, P. Rowell
We report here a 250-nm InP HBT based wideband power amplifier that operates between 110-190 GHz and fully covers D-band (110-170 GHz). It utilizes 5-gain stages and 2-way on-chip power combining. The amplifier demonstrates 25.2-dB S21 mid-band gain and 68-117 mW output power between 110190 GHz. The fractional bandwidth associated with 1-dB and 3- dB S21 gain roll-off are 35% (54-GHz) and 43% (66.5-GHz), respectively. The fractional large-signal power bandwidth associated with highest power between 110-190 GHz is 53%. Under small, medium, and large-signal operation, the PA is most efficient between 115-185 GHz – at 3-dBm input power, 73-104 mW output power (5.0-7.5% PAE) is demonstrated over this frequency span. This result represents a significant increase to the state-of-the-art for a mm-wave solid-state power amplifier operating across D-band and a significant fraction of G-band in the simultaneously demonstrated metrics of high output power (by 3-4× higher), bandwidth, gain, and gain flatness.
{"title":"A 115-185 GHz 75-115 mW High-Gain PA MMIC in 250-nm InP HBT","authors":"Z. Griffith, M. Urteaga, P. Rowell","doi":"10.23919/EuMIC.2019.8909407","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909407","url":null,"abstract":"We report here a 250-nm InP HBT based wideband power amplifier that operates between 110-190 GHz and fully covers D-band (110-170 GHz). It utilizes 5-gain stages and 2-way on-chip power combining. The amplifier demonstrates 25.2-dB S21 mid-band gain and 68-117 mW output power between 110190 GHz. The fractional bandwidth associated with 1-dB and 3- dB S21 gain roll-off are 35% (54-GHz) and 43% (66.5-GHz), respectively. The fractional large-signal power bandwidth associated with highest power between 110-190 GHz is 53%. Under small, medium, and large-signal operation, the PA is most efficient between 115-185 GHz – at 3-dBm input power, 73-104 mW output power (5.0-7.5% PAE) is demonstrated over this frequency span. This result represents a significant increase to the state-of-the-art for a mm-wave solid-state power amplifier operating across D-band and a significant fraction of G-band in the simultaneously demonstrated metrics of high output power (by 3-4× higher), bandwidth, gain, and gain flatness.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909651
Abdul Ali, J. Yun, H. Ng, D. Kissinger, F. Giannini, P. Colantonio
This paper presents the design of a wideband on-chip dielectric resonator antenna (DRA) operating at sub-THz frequencies. The DRA consists of inverted E-shaped on-chip driver, a low-permittivity supporter, and a dielectric resonator (DR). Substrate integrated waveguide (SIW) cavity backed on-chip antenna with L-probe feeding mechanism is adopted for the driver at 350 GHz. A standard 130-nm SiGe BiCMOS back-end process is employed in its design. The input matching, gain, and radiation efficiency of the on-chip driver are enhanced by placing a supporter and a DR on top of it. From full-EM simulations, the DRA achieves the -10 dB impedance bandwidth of 65 GHz (18.5%) with peak gain of about 10 dBi and radiation efficiency of 75% at 350 GHz. The developed antenna is highly suitable for future broadband front-end systems operating above 300 GHz.
{"title":"Sub-THz On-Chip Dielectric Resonator Antenna with Wideband performance","authors":"Abdul Ali, J. Yun, H. Ng, D. Kissinger, F. Giannini, P. Colantonio","doi":"10.23919/EuMIC.2019.8909651","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909651","url":null,"abstract":"This paper presents the design of a wideband on-chip dielectric resonator antenna (DRA) operating at sub-THz frequencies. The DRA consists of inverted E-shaped on-chip driver, a low-permittivity supporter, and a dielectric resonator (DR). Substrate integrated waveguide (SIW) cavity backed on-chip antenna with L-probe feeding mechanism is adopted for the driver at 350 GHz. A standard 130-nm SiGe BiCMOS back-end process is employed in its design. The input matching, gain, and radiation efficiency of the on-chip driver are enhanced by placing a supporter and a DR on top of it. From full-EM simulations, the DRA achieves the -10 dB impedance bandwidth of 65 GHz (18.5%) with peak gain of about 10 dBi and radiation efficiency of 75% at 350 GHz. The developed antenna is highly suitable for future broadband front-end systems operating above 300 GHz.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132851717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909434
L. Pantoli, D. Spina, D. Romano, G. Antonini, G. Leuzzi, T. Dhaene
This work presents a new method for the analysis of RF and microwave autonomous circuits directly in the time-domain, which is the most effective approach at simulation level to evaluate nonlinear phenomena. For RF and microwave autonomous circuits, time-domain simulations usually experiment convergence problems or numerical inaccuracies due to the presence of distributed elements, preventing de-facto their use. The proposed solution is based on the Vector Fitting algorithm applied directly at circuit level. A case study relative to a RF hybrid oscillator is presented for practical demonstration and evaluation of performance reliability of the proposed method.
{"title":"Time-Domain Analysis of RF and Microwave Autonomous Circuits by Vector Fitting-Based Approach","authors":"L. Pantoli, D. Spina, D. Romano, G. Antonini, G. Leuzzi, T. Dhaene","doi":"10.23919/EuMIC.2019.8909434","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909434","url":null,"abstract":"This work presents a new method for the analysis of RF and microwave autonomous circuits directly in the time-domain, which is the most effective approach at simulation level to evaluate nonlinear phenomena. For RF and microwave autonomous circuits, time-domain simulations usually experiment convergence problems or numerical inaccuracies due to the presence of distributed elements, preventing de-facto their use. The proposed solution is based on the Vector Fitting algorithm applied directly at circuit level. A case study relative to a RF hybrid oscillator is presented for practical demonstration and evaluation of performance reliability of the proposed method.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"303 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909678
K. Reiser, J. Twynam, H. Brech, S. Hardikar, R. Weigel
The influence of eutectic die attach on RF-substrate losses of AlGaN/GaN HEMTs grown on high-resistivity silicon substrates has been studied. A severe degradation in load pull efficiency is observed after die attach. Analyzing this degradation for dies attached to flanges with differing thermal expansion coefficient shows a linear relationship between substrate strain and load pull efficiency. Loss measurements of coplanar waveguides (CPWs) show increasing substrate losses with increasing strain, while the transistor on-resistance remains unaffected. The degradation in load pull efficiency is, therefore, attributed to increased substrate losses. By evaluating the bias dependence of low frequency capacitance measurements together with the bias dependence of CPW characteristics, we show that the increase in substrate loss can be explained by the formation of interface charge at the GaN/Si interface. To the best of our knowledge, this is the first time that GaN transistor efficiency degradation has been shown to correlate with transmission line losses and changes at the GaN/Si interface after eutectic die attach.
{"title":"Increased RF-Losses at the GaN/Si Interface after Eutectic Die Attach","authors":"K. Reiser, J. Twynam, H. Brech, S. Hardikar, R. Weigel","doi":"10.23919/EuMIC.2019.8909678","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909678","url":null,"abstract":"The influence of eutectic die attach on RF-substrate losses of AlGaN/GaN HEMTs grown on high-resistivity silicon substrates has been studied. A severe degradation in load pull efficiency is observed after die attach. Analyzing this degradation for dies attached to flanges with differing thermal expansion coefficient shows a linear relationship between substrate strain and load pull efficiency. Loss measurements of coplanar waveguides (CPWs) show increasing substrate losses with increasing strain, while the transistor on-resistance remains unaffected. The degradation in load pull efficiency is, therefore, attributed to increased substrate losses. By evaluating the bias dependence of low frequency capacitance measurements together with the bias dependence of CPW characteristics, we show that the increase in substrate loss can be explained by the formation of interface charge at the GaN/Si interface. To the best of our knowledge, this is the first time that GaN transistor efficiency degradation has been shown to correlate with transmission line losses and changes at the GaN/Si interface after eutectic die attach.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909459
V. Riess, Paul Stärke, C. Carta, F. Ellinger
A quadrature up-conversion mixer for low-power wireless communication systems is presented. The circuit is based on a six-port junction with reflective loads to modulate a carrier signal at 190 GHz. While most of the previously published six-port up-conversion mixers were fabricated on ceramic substrates and use discrete III–V semiconductors as reflective loads, this circuit uses common-base stages integrated with the six-port junction on a single chip. The circuit was fabricated in a SiGe BiCMOS process and a conversion gain of –3 dB is measured with –10.3 dBm of power from a local oscillator and 36.5 mW of dc power. The –3 dB bandwidth in the baseband is 17 GHz. To the best knowledge of the authors, this is the first demonstration of an integrated six-port up-conversion mixer operating at mm-wave frequencies.
{"title":"An Integrated mm-Wave Quadrature Up-Conversion Mixer Based on a Six-Port Modulator","authors":"V. Riess, Paul Stärke, C. Carta, F. Ellinger","doi":"10.23919/EuMIC.2019.8909459","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909459","url":null,"abstract":"A quadrature up-conversion mixer for low-power wireless communication systems is presented. The circuit is based on a six-port junction with reflective loads to modulate a carrier signal at 190 GHz. While most of the previously published six-port up-conversion mixers were fabricated on ceramic substrates and use discrete III–V semiconductors as reflective loads, this circuit uses common-base stages integrated with the six-port junction on a single chip. The circuit was fabricated in a SiGe BiCMOS process and a conversion gain of –3 dB is measured with –10.3 dBm of power from a local oscillator and 36.5 mW of dc power. The –3 dB bandwidth in the baseband is 17 GHz. To the best knowledge of the authors, this is the first demonstration of an integrated six-port up-conversion mixer operating at mm-wave frequencies.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128852760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909443
C. Potier, J. Jacquet, C. Lacam, N. Michel, C. Dua, M. Oualli, S. Delage, S. Piotrowicz, C. Chang, O. Patard, L. Trinh-Xuan, J. Gruenenpuett, P. Gamarra, P. Altuntas, E. Chartier
This paper presents the measurement results of a MMIC power amplifiers (PA), based on InAlGaN/GaN HEMT technology, for Ka band applications. The three-stages MMIC is operating within a bandwidth of [25-31] GHz and demonstrate over this bandwidth a saturated output power of 40dBm. Each stage uses 8x50μm gate width HEMTs fabricated with a 0.I5μm gate length on 70μm thick SiC substrate.
{"title":"10W Ka Band MMIC Power Amplifiers based on InAlGaN/GaN HEMT Technology","authors":"C. Potier, J. Jacquet, C. Lacam, N. Michel, C. Dua, M. Oualli, S. Delage, S. Piotrowicz, C. Chang, O. Patard, L. Trinh-Xuan, J. Gruenenpuett, P. Gamarra, P. Altuntas, E. Chartier","doi":"10.23919/EuMIC.2019.8909443","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909443","url":null,"abstract":"This paper presents the measurement results of a MMIC power amplifiers (PA), based on InAlGaN/GaN HEMT technology, for Ka band applications. The three-stages MMIC is operating within a bandwidth of [25-31] GHz and demonstrate over this bandwidth a saturated output power of 40dBm. Each stage uses 8x50μm gate width HEMTs fabricated with a 0.I5μm gate length on 70μm thick SiC substrate.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129122166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909586
G. Acri, L. Boccia, N. Corrao, F. Podevin, E. Pistono, T. Lim, E. Isa, P. Ferrari
This work presents a comparative study of conventional and slow wave (SW) transmission lines implemented in an advanced 22-nm CMOS process. Both microstrip (MS) and coplanar waveguides (CPW) were analysed through simulations and measurements. A classical SW approach was used for the implementation of the SW CPWs while the SW effect was generated in the MS lines using bed of nails integrated in the CMOS process. As a proof of concept, the proposed SW MS approach was employed to design a new artificial quarter-wave TL section. The proposed configuration was created loading a meandered MS line with open ended S-MS stubs acting as discrete capacitive loads. Results show that the proposed methodology offers an attractive form factor and good performance.
{"title":"Compact and performing transmission lines for mm-wave circuits design in advanced CMOS technology","authors":"G. Acri, L. Boccia, N. Corrao, F. Podevin, E. Pistono, T. Lim, E. Isa, P. Ferrari","doi":"10.23919/EuMIC.2019.8909586","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909586","url":null,"abstract":"This work presents a comparative study of conventional and slow wave (SW) transmission lines implemented in an advanced 22-nm CMOS process. Both microstrip (MS) and coplanar waveguides (CPW) were analysed through simulations and measurements. A classical SW approach was used for the implementation of the SW CPWs while the SW effect was generated in the MS lines using bed of nails integrated in the CMOS process. As a proof of concept, the proposed SW MS approach was employed to design a new artificial quarter-wave TL section. The proposed configuration was created loading a meandered MS line with open ended S-MS stubs acting as discrete capacitive loads. Results show that the proposed methodology offers an attractive form factor and good performance.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129969336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.23919/EuMIC.2019.8909608
M. Voelkel, M. Dietz, A. Hagelauer, E. M. Hussein, D. Kissinger, R. Weigel
In this paper a 60 GHz monolithic bistatic interferometric radar transceiver for high precision measuring is presented. The integrated transceiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a LNA, a passive six-port structure, detectors, multiplier, multiplexer, power amplifier and a digital interface. The chip has a size of 2330 μm x 1360 μm and a maximum power consumption of 533 mW from a 3.3 V power supply. The circuit provides two frequency inputs of 7.5 and 15 GHz and multiplies them up to 60 GHz at a minimum input power of -20 dBm. The chip delivers a maximum output power of 9 dBm at 61 GHz. The input path is selectable and the output power is adjustable by a digital interface between -23 and 9 dBm at 60 GHz. Also the reference input power of the six-port and the RF input power can be adjusted in a range of 13.2 dB. The minimum input referred P1dB is -24.1 dBm. With a multiplexer, the receiver reference can be separated from the transmitter, which allows the use of both independently from each other. The serial interface is realized in 0.13 μm CMOS logic and consists of a 20 bit shift register, decoder and an analog interface.
{"title":"A Digital Adjustable Fully Integrated Bistatic Interferometric Radar Transceiver at 60 GHz in a 130 nm BiCMOS Technology","authors":"M. Voelkel, M. Dietz, A. Hagelauer, E. M. Hussein, D. Kissinger, R. Weigel","doi":"10.23919/EuMIC.2019.8909608","DOIUrl":"https://doi.org/10.23919/EuMIC.2019.8909608","url":null,"abstract":"In this paper a 60 GHz monolithic bistatic interferometric radar transceiver for high precision measuring is presented. The integrated transceiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a LNA, a passive six-port structure, detectors, multiplier, multiplexer, power amplifier and a digital interface. The chip has a size of 2330 μm x 1360 μm and a maximum power consumption of 533 mW from a 3.3 V power supply. The circuit provides two frequency inputs of 7.5 and 15 GHz and multiplies them up to 60 GHz at a minimum input power of -20 dBm. The chip delivers a maximum output power of 9 dBm at 61 GHz. The input path is selectable and the output power is adjustable by a digital interface between -23 and 9 dBm at 60 GHz. Also the reference input power of the six-port and the RF input power can be adjusted in a range of 13.2 dB. The minimum input referred P1dB is -24.1 dBm. With a multiplexer, the receiver reference can be separated from the transmitter, which allows the use of both independently from each other. The serial interface is realized in 0.13 μm CMOS logic and consists of a 20 bit shift register, decoder and an analog interface.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123739200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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