Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705863
R. Waser, V. Rana, S. Menzel, E. Linn
Redox-Based Resistive Switching Memories (ReRAM), also called nanoionic memories or memristive elements, are widely considered providing a potential leap beyond the limits of Flash (with respect to write speed, write energies) and DRAM (scalability, retention times) as well as energy-efficient approaches to neuromorphic concepts.
{"title":"Energy-efficient redox-based non-volatile memory devices and logic circuits","authors":"R. Waser, V. Rana, S. Menzel, E. Linn","doi":"10.1109/E3S.2013.6705863","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705863","url":null,"abstract":"Redox-Based Resistive Switching Memories (ReRAM), also called nanoionic memories or memristive elements, are widely considered providing a potential leap beyond the limits of Flash (with respect to write speed, write energies) and DRAM (scalability, retention times) as well as energy-efficient approaches to neuromorphic concepts.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131705206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705855
K. Eder
From mobile devices to data centres, energy usage in computing continues to rise and is now a significant part of global energy consumption. Increasing the energy efficiency of computation is a major concern in electronic system engineering and high on the research agenda worldwide. While hardware can be designed to save a modest amount of energy, the potential for savings are far greater at the higher levels of abstraction in the system stack. The greatest savings are expected from energy consumption-aware software. This is because, although energy is consumed by the hardware executing computations, the control over the computation ultimately lies within the software, algorithms and data, i.e. the applications running on the hardware. Experts from Intel [1] expect software that takes full control of the energy-saving features provided by hardware can save three to five times of what conventional software is achieving. Moreover, algorithm selection is critically important - not only does the algorithm need to be the most suitable for solving the problem; it also needs to be a good fit to the hardware [2]. The challenge of energy-efficient computing, therefore, requires understanding the entire system stack, from algorithms and data, down to the computational hardware. Over the last decades, however, software engineering has been moved away from the operation of the hardware through the introduction of several layers of abstraction. While these have many benefits, including portability, increased programmer productivity, and software reuse across hardware platforms, the clear drawback is that many software engineers are now "blissfully unaware" of how algorithms and data, and their respective encoding, influence the energy consumption of a computation when executed on hardware.
{"title":"Energy transparency from hardware to software","authors":"K. Eder","doi":"10.1109/E3S.2013.6705855","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705855","url":null,"abstract":"From mobile devices to data centres, energy usage in computing continues to rise and is now a significant part of global energy consumption. Increasing the energy efficiency of computation is a major concern in electronic system engineering and high on the research agenda worldwide. While hardware can be designed to save a modest amount of energy, the potential for savings are far greater at the higher levels of abstraction in the system stack. The greatest savings are expected from energy consumption-aware software. This is because, although energy is consumed by the hardware executing computations, the control over the computation ultimately lies within the software, algorithms and data, i.e. the applications running on the hardware. Experts from Intel [1] expect software that takes full control of the energy-saving features provided by hardware can save three to five times of what conventional software is achieving. Moreover, algorithm selection is critically important - not only does the algorithm need to be the most suitable for solving the problem; it also needs to be a good fit to the hardware [2]. The challenge of energy-efficient computing, therefore, requires understanding the entire system stack, from algorithms and data, down to the computational hardware. Over the last decades, however, software engineering has been moved away from the operation of the hardware through the introduction of several layers of abstraction. While these have many benefits, including portability, increased programmer productivity, and software reuse across hardware platforms, the clear drawback is that many software engineers are now \"blissfully unaware\" of how algorithms and data, and their respective encoding, influence the energy consumption of a computation when executed on hardware.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705875
E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power consumption of integrated circuits [1]. Current challenges for TFET integration into practical circuit applications include reaching acceptable ION levels, suppressing ambipolar effects, improving output characteristics [2], and simultaneously co-integrating optimized n-and p-type devices. All of these issues are carefully taken into account in this work. Device- and circuit-level design of TFET inverters is proposed, based on co-optimized n-and p-type TFETs integrated on the same InAs/ Al0.05Ga0.95Sb platform. A full-band quantum simulation approach is adopted to properly account for quantum effects which strongly influence TFET device, and hence circuit, performance. This advances the state of the art of TFET-based circuit literature, which is mostly based on simplified TCAD models [3], with rare calibrations against atomistic calculations [4].
{"title":"Full-quantum simulation of heterojunction TFET inverters providing better performance than multi-gate CMOS at sub-0.35V VDD","authors":"E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani","doi":"10.1109/E3S.2013.6705875","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705875","url":null,"abstract":"Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power consumption of integrated circuits [1]. Current challenges for TFET integration into practical circuit applications include reaching acceptable ION levels, suppressing ambipolar effects, improving output characteristics [2], and simultaneously co-integrating optimized n-and p-type devices. All of these issues are carefully taken into account in this work. Device- and circuit-level design of TFET inverters is proposed, based on co-optimized n-and p-type TFETs integrated on the same InAs/ Al0.05Ga0.95Sb platform. A full-band quantum simulation approach is adopted to properly account for quantum effects which strongly influence TFET device, and hence circuit, performance. This advances the state of the art of TFET-based circuit literature, which is mostly based on simplified TCAD models [3], with rare calibrations against atomistic calculations [4].","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128282222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705864
T. Endoh
Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.
{"title":"STT-MRAM and NV-Logic for low power systems","authors":"T. Endoh","doi":"10.1109/E3S.2013.6705864","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705864","url":null,"abstract":"Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705865
M. Sharad, Deliang Fan, K. Yogendra, K. Roy
Emerging spin transfer torque (ST) devices such as lateral spin valves and domain wall magnets may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. This paper reviews our work on ST-based non-Boolean data-processing applications, like neural-networks, which involve analog processing. Integration of such spin-torque devices with charge-based devices like CMOS can lead to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Simulation results for analog image processing and associative computing has shown the possibility of ~100X improvement in energy efficiency as compared to a 15nm CMOS ASIC.
{"title":"Ultra-Low power neuromorphic computing with spin-torque devices","authors":"M. Sharad, Deliang Fan, K. Yogendra, K. Roy","doi":"10.1109/E3S.2013.6705865","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705865","url":null,"abstract":"Emerging spin transfer torque (ST) devices such as lateral spin valves and domain wall magnets may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. This paper reviews our work on ST-based non-Boolean data-processing applications, like neural-networks, which involve analog processing. Integration of such spin-torque devices with charge-based devices like CMOS can lead to highly energy-efficient information processing hardware for applicatons like pattern-matching, neuromorphic-computing, image-processing and data-conversion. Simulation results for analog image processing and associative computing has shown the possibility of ~100X improvement in energy efficiency as compared to a 15nm CMOS ASIC.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115317993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705857
K. Vaidyanathan, K. Gross
Monitoring the dynamic power utilization of enterprise computer servers in large-scale data centers is a non-trivial undertaking. Real-time power monitoring is essential for power management and intelligent cooling provisioning and is motivated by the fact that the energy costs for many classes of servers now exceeds the initial hardware costs for the servers. The conventional approach for dynamic power monitoring requires installing hardware Power Distribution Units (PDUs) for all the servers in a datacenter, which is tedious and costly when newer data centers house up to thousands of servers. PDUs require more space in densely cramped data centers, require disruption of business-critical servers (in existing data centers) for attachment to the PDUs, and diminishes overall data center reliability (additional layer of hardware in series with the servers that can degrade in service). Oracle has introduced an innovation called Intelligent Power Monitoring (IPM), which provides accurate, real-time power utilization for servers as a function of customer load fluctuations, fan speed variations, dynamic reconfiguration events under virtualization tiers, failover events for redundant power supplies, and during times when power management features in the CPUs are performing power-capping and/or thermal-capping roles.
{"title":"Intelligent power monitoring and management for enterprise servers","authors":"K. Vaidyanathan, K. Gross","doi":"10.1109/E3S.2013.6705857","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705857","url":null,"abstract":"Monitoring the dynamic power utilization of enterprise computer servers in large-scale data centers is a non-trivial undertaking. Real-time power monitoring is essential for power management and intelligent cooling provisioning and is motivated by the fact that the energy costs for many classes of servers now exceeds the initial hardware costs for the servers. The conventional approach for dynamic power monitoring requires installing hardware Power Distribution Units (PDUs) for all the servers in a datacenter, which is tedious and costly when newer data centers house up to thousands of servers. PDUs require more space in densely cramped data centers, require disruption of business-critical servers (in existing data centers) for attachment to the PDUs, and diminishes overall data center reliability (additional layer of hardware in series with the servers that can degrade in service). Oracle has introduced an innovation called Intelligent Power Monitoring (IPM), which provides accurate, real-time power utilization for servers as a function of customer load fluctuations, fan speed variations, dynamic reconfiguration events under virtualization tiers, failover events for redundant power supplies, and during times when power management features in the CPUs are performing power-capping and/or thermal-capping roles.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124704881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705882
Ji-Hun Kim, Zack C. Y. Chen, Soonshin Kwon, J. Xiang
Significant physical challenges remain for CMOS technology to decrease Ioff as transistor dimension and power supply voltages continue downscaling. However, a fundamental thermodynamic limit in the subthreshold slope SS = |(∂Vg)/(∂lnId)| = ln10 · kBT/q at >60 mV/dec exists at room temperature. We have designed and demonstrated the first semiconductor nanowires (NWs) and nanoelectromechanical system (NEMS) field effect transistor structure (NW-NEMFET). We have previously demonstrated 0.5 ps intrinsic delay and near ballistic operation in quantum confined semiconductor heterostructure NWFETs with diameters less than 15 nm.[1] The current design uses high performance suspended semiconductor NWs as the conduction channel, while the electrostatic pull-in of the NW towards the gate stack enables abrupt switching to the off-state leading to high frequency, low power nanoelectronics. Simulation shows that compared to planar suspended-gate FET (SGFET) design [2], NW-NEMFET allows zero SS with 1015 on-off ratio and near 1V pull-in voltage due to enhanced 3D capacitive coupling, as well as operation at very-high-frequency (VHF) and even ultra-high-frequency (UHF) due to the NW beams high aspect ratio and small dimensions.
{"title":"Steep subthreshold slope nanowire nanoelectromechanical field-effect transistors (NW-NEMFETs)","authors":"Ji-Hun Kim, Zack C. Y. Chen, Soonshin Kwon, J. Xiang","doi":"10.1109/E3S.2013.6705882","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705882","url":null,"abstract":"Significant physical challenges remain for CMOS technology to decrease Ioff as transistor dimension and power supply voltages continue downscaling. However, a fundamental thermodynamic limit in the subthreshold slope SS = |(∂Vg)/(∂lnId)| = ln10 · kBT/q at >60 mV/dec exists at room temperature. We have designed and demonstrated the first semiconductor nanowires (NWs) and nanoelectromechanical system (NEMS) field effect transistor structure (NW-NEMFET). We have previously demonstrated 0.5 ps intrinsic delay and near ballistic operation in quantum confined semiconductor heterostructure NWFETs with diameters less than 15 nm.[1] The current design uses high performance suspended semiconductor NWs as the conduction channel, while the electrostatic pull-in of the NW towards the gate stack enables abrupt switching to the off-state leading to high frequency, low power nanoelectronics. Simulation shows that compared to planar suspended-gate FET (SGFET) design [2], NW-NEMFET allows zero SS with 1015 on-off ratio and near 1V pull-in voltage due to enhanced 3D capacitive coupling, as well as operation at very-high-frequency (VHF) and even ultra-high-frequency (UHF) due to the NW beams high aspect ratio and small dimensions.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124108753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705872
J. Teherani, Tao Yu, D. Antoniadis, J. Hoyt
Tunneling field-effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of the subthreshold swing for conventional devices enabling lower power electronics. However, as shown in the TFET review by Seabaugh and Zhang [1], experimental subthreshold characteristics have not achieved the steepness of theoretical predictions. Possible explanations for the non-abrupt turn-on of experimental devices include long band-tails (exacerbated by doping) that extend into the semiconductor band gap, mid-gap and interface trap-states, inhomogeneity of the semiconductor composition, strain and/or thickness, and non-optimal electrostatic design of the transistor structure. This paper focuses on improving the electrostatic design of vertical tunneling structures (where tunneling occurs vertically toward the gate), in order to better experimental turn-on characteristics.
{"title":"Electrostatic design of vertical tunneling field-effect transistors","authors":"J. Teherani, Tao Yu, D. Antoniadis, J. Hoyt","doi":"10.1109/E3S.2013.6705872","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705872","url":null,"abstract":"Tunneling field-effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of the subthreshold swing for conventional devices enabling lower power electronics. However, as shown in the TFET review by Seabaugh and Zhang [1], experimental subthreshold characteristics have not achieved the steepness of theoretical predictions. Possible explanations for the non-abrupt turn-on of experimental devices include long band-tails (exacerbated by doping) that extend into the semiconductor band gap, mid-gap and interface trap-states, inhomogeneity of the semiconductor composition, strain and/or thickness, and non-optimal electrostatic design of the transistor structure. This paper focuses on improving the electrostatic design of vertical tunneling structures (where tunneling occurs vertically toward the gate), in order to better experimental turn-on characteristics.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127073959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705866
A. Majumdar
Summary form only given. Access to affordable and reliable energy has been a cornerstone of the world's increasing prosperity and economic growth since the beginning of the industrial revolution about 250 years ago. Since then we have built our energy infrastructure worth several Trillions of dollars, which is an icon of any modern economy. More recently, we have been and will continue to build the infrastructure for communication and computing. However, the energy and information infrastructures are largely separate, ie they really have not been leveraged. In this talk, I will discuss one of several leveraging opportunities. Our grid architecture is about 100 years old, and is a legacy of the innovations Tesla, Edison and their industrial partners introduced. The architecture is based on centralized generation, a transmission system and a distribution network, with one-way electrical power flow. However, solar and wind electricity could easily become the cheapest way to produce electricity within this decade, battery storage will become cheaper as well, and network communication is widely available. None of these features were available 100 years ago. This techno-economic convergence will introduce two significant transitions for our grid - one that will require a layer of communication, computation and control to manage the grid, and the second that will combine centralized and distributed generation and storage. This talk will outline some of the opportunities and challenges in this transition.
{"title":"Leveraging energy & information infrastructures","authors":"A. Majumdar","doi":"10.1109/E3S.2013.6705866","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705866","url":null,"abstract":"Summary form only given. Access to affordable and reliable energy has been a cornerstone of the world's increasing prosperity and economic growth since the beginning of the industrial revolution about 250 years ago. Since then we have built our energy infrastructure worth several Trillions of dollars, which is an icon of any modern economy. More recently, we have been and will continue to build the infrastructure for communication and computing. However, the energy and information infrastructures are largely separate, ie they really have not been leveraged. In this talk, I will discuss one of several leveraging opportunities. Our grid architecture is about 100 years old, and is a legacy of the innovations Tesla, Edison and their industrial partners introduced. The architecture is based on centralized generation, a transmission system and a distribution network, with one-way electrical power flow. However, solar and wind electricity could easily become the cheapest way to produce electricity within this decade, battery storage will become cheaper as well, and network communication is widely available. None of these features were available 100 years ago. This techno-economic convergence will introduce two significant transitions for our grid - one that will require a layer of communication, computation and control to manage the grid, and the second that will combine centralized and distributed generation and storage. This talk will outline some of the opportunities and challenges in this transition.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129564580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705870
K. Tomioka, T. Fukui
Main target in future LSI is to achieve low power consumption while enhancing performance. There are many concerns to lower the power consumption in recent CMOS technologies, such as multi-gate architecture for suppressing short-channel effect and OFF-state leakage current. The state-of-the-art FET offered by the gate structure surely reduces the power dissipation, but the power-scaling will be limited by FET in itself since the reduction in supply voltage in Si-based MOSFETs has some difficulties, such as low carrier mobility under lower electrical field and physically limited subthreshold slope (SS). Especially, utilization of steep subthreshold-slope transistor such as tunnel FETs (TFETs) and impact ionization FETs is important for the low power circuits because physical limitation due to carrier thermal diffusion stops a scaling of the power consumption even if the multi-gate structure and III-Vs are utilized. Thus, another channel materials and transport mechanisms should be addressed mutually in CMOS technologies, and these distinct features should possess good compatibility with the Si-based CMOS. In this regard, heterojunctions formed across the III-V nanowire (NW) and Si would be promising building blocks for the future extended CMOS technologies. Here, we present integration of III-V nanowires on Si by selective-area growth and concept for steep SS transistor using III-V nanowire/Si heterojunctions.
{"title":"III-V/Si heterojunctions for steep subthreshold-slope transistor","authors":"K. Tomioka, T. Fukui","doi":"10.1109/E3S.2013.6705870","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705870","url":null,"abstract":"Main target in future LSI is to achieve low power consumption while enhancing performance. There are many concerns to lower the power consumption in recent CMOS technologies, such as multi-gate architecture for suppressing short-channel effect and OFF-state leakage current. The state-of-the-art FET offered by the gate structure surely reduces the power dissipation, but the power-scaling will be limited by FET in itself since the reduction in supply voltage in Si-based MOSFETs has some difficulties, such as low carrier mobility under lower electrical field and physically limited subthreshold slope (SS). Especially, utilization of steep subthreshold-slope transistor such as tunnel FETs (TFETs) and impact ionization FETs is important for the low power circuits because physical limitation due to carrier thermal diffusion stops a scaling of the power consumption even if the multi-gate structure and III-Vs are utilized. Thus, another channel materials and transport mechanisms should be addressed mutually in CMOS technologies, and these distinct features should possess good compatibility with the Si-based CMOS. In this regard, heterojunctions formed across the III-V nanowire (NW) and Si would be promising building blocks for the future extended CMOS technologies. Here, we present integration of III-V nanowires on Si by selective-area growth and concept for steep SS transistor using III-V nanowire/Si heterojunctions.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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