Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705871
H. Xing, Guangle Zhou, Mingda Li, Yiqing Lu, Rui Li, M. Wistey, P. Fay, D. Jena, A. Seabaugh
Summary form only given. In this talk, I will review some of the recent development of tunnel field effect transistors (TFETs) at Notre Dame [1-8]. Tunnel FETs are promising replacements of Si-MOSFETs beyond 2020 due to their promise to achieve Ion/Ioff > 103 with Ion > 100 uA/um at low supply voltages (up to 0.5 V). To date we have demonstrated Ion/Ioff ~ 106, Ion ~ 180 uA/um, separately, based on III-V heterostructures. Challenges ahead include electrostatic control, defect-assisted tunneling and interface state density and parasitics. More recently, we have started to investigate 2D crystal based TFETs for their promises to realize ultrascaled electronic switches.
只提供摘要形式。在这次演讲中，我将回顾一些在巴黎圣母院隧道场效应晶体管(tfet)的最新发展[1-8]。隧道fet有望在2020年以后取代si - mosfet，因为它们有望在低电源电压(高达0.5 V)下实现离子> 100 uA/um的离子/ off > 103。到目前为止，我们已经分别展示了基于III-V异质结构的离子/ off ~ 106，离子~ 180 uA/um。未来的挑战包括静电控制、缺陷辅助隧道、界面态密度和寄生。最近，我们开始研究基于二维晶体的tfet，因为它们有望实现超尺度电子开关。
{"title":"Tunnel FETs with tunneling normal to the gate","authors":"H. Xing, Guangle Zhou, Mingda Li, Yiqing Lu, Rui Li, M. Wistey, P. Fay, D. Jena, A. Seabaugh","doi":"10.1109/E3S.2013.6705871","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705871","url":null,"abstract":"Summary form only given. In this talk, I will review some of the recent development of tunnel field effect transistors (TFETs) at Notre Dame [1-8]. Tunnel FETs are promising replacements of Si-MOSFETs beyond 2020 due to their promise to achieve I<sub>on</sub>/I<sub>off</sub> > 10<sup>3</sup> with I<sub>on</sub> > 100 uA/um at low supply voltages (up to 0.5 V). To date we have demonstrated I<sub>on</sub>/I<sub>off</sub> ~ 10<sup>6</sup>, I<sub>on</sub> ~ 180 uA/um, separately, based on III-V heterostructures. Challenges ahead include electrostatic control, defect-assisted tunneling and interface state density and parasitics. More recently, we have started to investigate 2D crystal based TFETs for their promises to realize ultrascaled electronic switches.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124790128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705877
R. Jana, G. Snider, D. Jena
Scaling of field-effect transistors (FETs) is limited by the high power dissipation density, and the resulting heat generation in ICs [1]. This is due to the non-scalability of subthreshold slope (SS), i.e. the gate voltage required to change the drain current by an order of magnitude; the value is limited to SS=kTln(10)~60 mV/dec in a classical Boltzmann FET switch [2-3]. Tunneling FETs are being investigated for sub-Boltzmann switching. But even a conventional FET can potentially achieve sub-Boltzmann switching taking advantage of ferroelectric gates materials [3]. It is possible to amplify the internal channel surface potential, Ψs over the applied gate bias voltage, Vg; using negative differential capacitance (NDC) in the gate insulator. The “body factor” then reduces below unity i.e. m = ∂Vg / ∂Ψs <; 1, and hence the subthreshold slope (SS=m×60 mV/dec) can be lowered below 60 mV/dec. In this work, we show that such internal gain mechanism can also exist in piezoelectric gate materials, such as in AIN/GaN heterostructures.
{"title":"Sub-Boltzmann transistors with piezoelectric gate barriers","authors":"R. Jana, G. Snider, D. Jena","doi":"10.1109/E3S.2013.6705877","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705877","url":null,"abstract":"Scaling of field-effect transistors (FETs) is limited by the high power dissipation density, and the resulting heat generation in ICs [1]. This is due to the non-scalability of subthreshold slope (SS), i.e. the gate voltage required to change the drain current by an order of magnitude; the value is limited to SS=kTln(10)~60 mV/dec in a classical Boltzmann FET switch [2-3]. Tunneling FETs are being investigated for sub-Boltzmann switching. But even a conventional FET can potentially achieve sub-Boltzmann switching taking advantage of ferroelectric gates materials [3]. It is possible to amplify the internal channel surface potential, Ψs over the applied gate bias voltage, Vg; using negative differential capacitance (NDC) in the gate insulator. The “body factor” then reduces below unity i.e. m = ∂Vg / ∂Ψs <; 1, and hence the subthreshold slope (SS=m×60 mV/dec) can be lowered below 60 mV/dec. In this work, we show that such internal gain mechanism can also exist in piezoelectric gate materials, such as in AIN/GaN heterostructures.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134105470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705884
A. Krishnamoorthy
Within the past decade, the semiconductor computing industry has developed multicore and multithreaded core processors to overcome the challenges and shrinking benefits of traditional technology scaling. Multichip systems built using these components will require immense amount of off-chip bandwidth and low latency chip-to-chip links at the lowest energy cost possible. Wavelength-division multiplexed (WDM) silicon photonics have the potential to provide a solution for this immense interconnect problem. At Oracle, we are aggressively building a portfolio of active and passive nanophotonic devices, circuits, and multichip packaging with the aim to achieve sub-picojoule per bit communication links between computing elements in a large array “Macrochip”. To achieve ultralow energy consumption will certainly require integrating best-in-breed photonic devices with electronic circuits. While the juxtaposition of silicon photonic devices and VLSI circuits on the same silicon substrate represents the most intimate integration of electronic and photonic technologies, achieving this will require an immense amount of sophistication in design and process integration. Instead, hybrid integration of aggressive components, built on individually optimized technology platforms, is a pragmatic approach to achieving peak performance. Such “photonic bridge” chip components may be used as units in a larger transmitter or receiver array or as drop-in communication physical layer elements in a multi-chip computing node.
{"title":"Efficient optical interconnections for data-center computing systems","authors":"A. Krishnamoorthy","doi":"10.1109/E3S.2013.6705884","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705884","url":null,"abstract":"Within the past decade, the semiconductor computing industry has developed multicore and multithreaded core processors to overcome the challenges and shrinking benefits of traditional technology scaling. Multichip systems built using these components will require immense amount of off-chip bandwidth and low latency chip-to-chip links at the lowest energy cost possible. Wavelength-division multiplexed (WDM) silicon photonics have the potential to provide a solution for this immense interconnect problem. At Oracle, we are aggressively building a portfolio of active and passive nanophotonic devices, circuits, and multichip packaging with the aim to achieve sub-picojoule per bit communication links between computing elements in a large array “Macrochip”. To achieve ultralow energy consumption will certainly require integrating best-in-breed photonic devices with electronic circuits. While the juxtaposition of silicon photonic devices and VLSI circuits on the same silicon substrate represents the most intimate integration of electronic and photonic technologies, achieving this will require an immense amount of sophistication in design and process integration. Instead, hybrid integration of aggressive components, built on individually optimized technology platforms, is a pragmatic approach to achieving peak performance. Such “photonic bridge” chip components may be used as units in a larger transmitter or receiver array or as drop-in communication physical layer elements in a multi-chip computing node.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134601936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705878
M. Rodwell, D. Elias
As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage VDD. With thermally-activated, FETs, the off-state leakage Ioff and target on-current Ion then determine the minimum feasible VDD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high Ion at low Ioff and low VDD is challenging. Subthreshold logic [2] operates at lowVDD, but is slow because of low Ion. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed VDD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing VDD to ~300mV while maintaining large Ion per unit IC die area.
{"title":"Prospects for high-aspect-ratio FinFETs in low-power logic","authors":"M. Rodwell, D. Elias","doi":"10.1109/E3S.2013.6705878","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705878","url":null,"abstract":"As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage VDD. With thermally-activated, FETs, the off-state leakage Ioff and target on-current Ion then determine the minimum feasible VDD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high Ion at low Ioff and low VDD is challenging. Subthreshold logic [2] operates at lowVDD, but is slow because of low Ion. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed VDD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing VDD to ~300mV while maintaining large Ion per unit IC die area.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705885
R. Going, Jodi Loo, Tsu-Jae King-Liu, Ming C. Wu
We demonstrate a monocrystalline 1×8 μm germanium gate photoMOSFET integrated with silicon photonic waveguides and grating coupler operating at over 2.5 GB/s at 1550nm.
{"title":"2.5 GB/s germanium gate photoMOSFET integrated to silicon photonics","authors":"R. Going, Jodi Loo, Tsu-Jae King-Liu, Ming C. Wu","doi":"10.1109/E3S.2013.6705885","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705885","url":null,"abstract":"We demonstrate a monocrystalline 1×8 μm germanium gate photoMOSFET integrated with silicon photonic waveguides and grating coupler operating at over 2.5 GB/s at 1550nm.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116702346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705868
S. Agarwal, E. Yablonovitch
To date, TFET results have been unsatisfying. The best reported subthreshold swings have been measured at a current density of around a nA/um and get significantly worse as the current increases. In order to achieve a better performance, there are fundamental design issues that need to be engineered. We can understand these issues by analyzing the three types of devices shown in Fig 1. The voltage required to operate a TFET can be given by: VDD = VSS × Log(Ion /Ioff)+ VOV. VSS is the subthreshold swing and VOV is the overdrive voltage needed to achieve the desired on-current after threshold. VOV will be determined by the device geometry as shown in Fig 2 [1]. Introducing quantum confinement in the direction of tunneling increases the conductance by 1-2 orders of magnitude at low voltage. VSS is given by the following model [2]: SS = 1/ ηel × (1/SBarrier + ηconf/SDOS)-1 (1) ηel is the electrostatic gate efficiency. ηconf is the quantum confinement efficiency and comes from energy level shifts that occur when the quantum well shape changes with bias. SBarrier represents the steepness in mV/decade that comes from changing the thickness of the tunneling barrier. SDOS is the steepness of the joint density of states (DOS) and represents the rate at which the joint DOS fall off as the band edges are misaligned.
{"title":"Why tunneling FETs don't work, and how to fix it","authors":"S. Agarwal, E. Yablonovitch","doi":"10.1109/E3S.2013.6705868","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705868","url":null,"abstract":"To date, TFET results have been unsatisfying. The best reported subthreshold swings have been measured at a current density of around a nA/um and get significantly worse as the current increases. In order to achieve a better performance, there are fundamental design issues that need to be engineered. We can understand these issues by analyzing the three types of devices shown in Fig 1. The voltage required to operate a TFET can be given by: V<sub>DD</sub> = V<sub>SS</sub> × Log(I<sub>on</sub> /I<sub>off</sub>)+ V<sub>OV</sub>. V<sub>SS</sub> is the subthreshold swing and V<sub>OV</sub> is the overdrive voltage needed to achieve the desired on-current after threshold. V<sub>OV</sub> will be determined by the device geometry as shown in Fig 2 [1]. Introducing quantum confinement in the direction of tunneling increases the conductance by 1-2 orders of magnitude at low voltage. V<sub>SS</sub> is given by the following model [2]: SS = 1/ η<sub>el</sub> × (1/S<sub>Barrier</sub> + η<sub>conf</sub>/S<sub>DOS</sub>)<sup>-1</sup> (1) η<sub>el</sub> is the electrostatic gate efficiency. η<sub>conf</sub> is the quantum confinement efficiency and comes from energy level shifts that occur when the quantum well shape changes with bias. S<sub>Barrier</sub> represents the steepness in mV/decade that comes from changing the thickness of the tunneling barrier. S<sub>DOS</sub> is the steepness of the joint density of states (DOS) and represents the rate at which the joint DOS fall off as the band edges are misaligned.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134080595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705854
J. Shalf
The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency largely dominated by bulk-synchronous algorithms. The trends in computer architecture have turned our model for how to get good performance from computing systems upside-down, and will require rethinking our entire programming environment and algorithm design to be better aligned with the new cost metrics for these emerging hardware architectures. There are already promising avenues of exploration underway to mitigate these effects. Future hardware constraints on bandwidth and memory capacity, together with exponential growth in explicit on-chip parallelism will likely require a mass migration to new algorithms and software architecture that is as broad and disruptive as the migration from vector to parallel computing systems that occurred 15 years go. The challenge is to efficiently express massive parallelism and hierarchical data locality without subjecting the programmer to overwhelming complexity. The author covers how changes in hardware (governed by the fundamental physics of Silicon based CMOS technology) are breaking our existing abstract machine models, and DOE's program to overcome these obstacles to continued performance improvements. He examines potential approaches that range from revolutionary asynchronous and dataflow models of computation to evolutionary extensions to existing APIs and OpenMP directives.
{"title":"Exascale computer architecture adjusting to the “New normal” for computing","authors":"J. Shalf","doi":"10.1109/E3S.2013.6705854","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705854","url":null,"abstract":"The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency largely dominated by bulk-synchronous algorithms. The trends in computer architecture have turned our model for how to get good performance from computing systems upside-down, and will require rethinking our entire programming environment and algorithm design to be better aligned with the new cost metrics for these emerging hardware architectures. There are already promising avenues of exploration underway to mitigate these effects. Future hardware constraints on bandwidth and memory capacity, together with exponential growth in explicit on-chip parallelism will likely require a mass migration to new algorithms and software architecture that is as broad and disruptive as the migration from vector to parallel computing systems that occurred 15 years go. The challenge is to efficiently express massive parallelism and hierarchical data locality without subjecting the programmer to overwhelming complexity. The author covers how changes in hardware (governed by the fundamental physics of Silicon based CMOS technology) are breaking our existing abstract machine models, and DOE's program to overcome these obstacles to continued performance improvements. He examines potential approaches that range from revolutionary asynchronous and dataflow models of computation to evolutionary extensions to existing APIs and OpenMP directives.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705886
M. Eggleston, K. Messer, S. Fortuna, E. Yablonovitch, Ming C. Wu
We present on an optical antenna based nanoLED that is fabricated directly on top of an InP waveguide. Waveguide coupling efficiency of 70% and directional emission is achieved with a Yagi-Uda antenna structure. By using an epitaxial lift-off process, we show that this device could be integrated directly onto a Silicon-photonics substrate.
{"title":"Waveguide-integrated optical antenna nanoLEDs for on-chip communication","authors":"M. Eggleston, K. Messer, S. Fortuna, E. Yablonovitch, Ming C. Wu","doi":"10.1109/E3S.2013.6705886","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705886","url":null,"abstract":"We present on an optical antenna based nanoLED that is fabricated directly on top of an InP waveguide. Waveguide coupling efficiency of 70% and directional emission is achieved with a Yagi-Uda antenna structure. By using an epitaxial lift-off process, we show that this device could be integrated directly onto a Silicon-photonics substrate.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705881
P. Feng
The active search for candidates of an ideal switching device for low-voltage logic and ultralow-power applications has stimulated focused explorations of contact-mode switches (relays) based on micro/nanoelectromechanical systems (MEMS/NEMS) [1-7]. This has been driven by the fundamental advantages that mechanical devices offer, such as ideally abrupt switching with zero off-state leakage, suitable for harsh and extreme environments, and very small footprints (e.g., particularly with NEMS). In pursuing and realizing these advantages, however, significant challenges still remain today: (i) All the high-performance mechanical switches recently demonstrated are still in the MEMS domain [2-5] and are orders of magnitude larger in size or volume (>103 to 104) than the nanoscale devices presented in this work. (ii) Most truly nanoscale contact-mode NEMS switches known to date (often based on various nanowires, cantilevers and nanotubes) still suffer from very short lifetimes.nanoscale contact-mode NEMS switches
{"title":"Nanoelectromechanical switching devices: Scaling toward ultimate energy efficiency and longevity","authors":"P. Feng","doi":"10.1109/E3S.2013.6705881","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705881","url":null,"abstract":"The active search for candidates of an ideal switching device for low-voltage logic and ultralow-power applications has stimulated focused explorations of contact-mode switches (relays) based on micro/nanoelectromechanical systems (MEMS/NEMS) [1-7]. This has been driven by the fundamental advantages that mechanical devices offer, such as ideally abrupt switching with zero off-state leakage, suitable for harsh and extreme environments, and very small footprints (e.g., particularly with NEMS). In pursuing and realizing these advantages, however, significant challenges still remain today: (i) All the high-performance mechanical switches recently demonstrated are still in the MEMS domain [2-5] and are orders of magnitude larger in size or volume (>103 to 104) than the nanoscale devices presented in this work. (ii) Most truly nanoscale contact-mode NEMS switches known to date (often based on various nanowires, cantilevers and nanotubes) still suffer from very short lifetimes.nanoscale contact-mode NEMS switches","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133682800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/E3S.2013.6705856
S. Borkar
Summary form only given. Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, increasing frequency, providing integration capacity to realize novel architectures, and reducing energy to keep power dissipation within limit. The technology treadmill will continue, and one would expect to reach Exascale level performance this decade; however, it's the same Physics that helped you in the past will now pose some barriers-Business as usual will not be an option. The energy and power will pose as a major challenge- an Exascale machine would consume in excess of a Giga-watt! Memory & communication bandwidth with conventional technology would be prohibitive. Orders of magnitude increased parallelism, let alone extreme parallelism due to energy saving techniques, would increase unreliability. And programming system will be posed with even severe challenge of harnessing the performance with concurrency. We will discuss potential solutions in all disciplines, such as circuit design, system architecture, system software, programming system, and resiliency to pave the road towards Exascale performance.
{"title":"Achieving energy efficiency by HW/SW co-design","authors":"S. Borkar","doi":"10.1109/E3S.2013.6705856","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705856","url":null,"abstract":"Summary form only given. Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, increasing frequency, providing integration capacity to realize novel architectures, and reducing energy to keep power dissipation within limit. The technology treadmill will continue, and one would expect to reach Exascale level performance this decade; however, it's the same Physics that helped you in the past will now pose some barriers-Business as usual will not be an option. The energy and power will pose as a major challenge- an Exascale machine would consume in excess of a Giga-watt! Memory & communication bandwidth with conventional technology would be prohibitive. Orders of magnitude increased parallelism, let alone extreme parallelism due to energy saving techniques, would increase unreliability. And programming system will be posed with even severe challenge of harnessing the performance with concurrency. We will discuss potential solutions in all disciplines, such as circuit design, system architecture, system software, programming system, and resiliency to pave the road towards Exascale performance.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126445247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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