Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045012
H. Meyvaert, T. V. Breussegem, M. Steyaert
A fully integrated capacitive DC-DC converter reporting an output power of 1.65W in a standard 90nm Bulk CMOS process is realized. This converter implements a 2:1 voltage step-down conversion from twice the nominal technology supply voltage. Peak power conversion efficiency was measured to be 69%. The chip measures 2.14mm2 including 12nF implemented in standard available MOS capacitors. These baseline MOS capacitors, along with the introduced Flying Well approach and the Intrinsic Charge Recycling approach, result in a maximum power density of 0.77W/mm2. The converter is controllable through an on-chip voltage controlled oscillator (VCO) generating the clock signals for each of the 21 interleaved converter cores of this multiphase implementation. The implemented core interleaving allows for an output voltage ripple smaller than 8% of Vo without any dedicated output smoothing capacitor, saving die area and thus boosting the power density.
{"title":"A monolithic 0.77W/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS","authors":"H. Meyvaert, T. V. Breussegem, M. Steyaert","doi":"10.1109/ESSCIRC.2011.6045012","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045012","url":null,"abstract":"A fully integrated capacitive DC-DC converter reporting an output power of 1.65W in a standard 90nm Bulk CMOS process is realized. This converter implements a 2:1 voltage step-down conversion from twice the nominal technology supply voltage. Peak power conversion efficiency was measured to be 69%. The chip measures 2.14mm2 including 12nF implemented in standard available MOS capacitors. These baseline MOS capacitors, along with the introduced Flying Well approach and the Intrinsic Charge Recycling approach, result in a maximum power density of 0.77W/mm2. The converter is controllable through an on-chip voltage controlled oscillator (VCO) generating the clock signals for each of the 21 interleaved converter cores of this multiphase implementation. The implemented core interleaving allows for an output voltage ripple smaller than 8% of Vo without any dedicated output smoothing capacitor, saving die area and thus boosting the power density.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044954
F. Chouard, S. More, M. Fulde, D. Schmitt-Landsiedel
Stress experiments are presented on analog size devices in inversion and accumulation mode, including relaxing stress phenomena. Based on these data, a general concept to suppress device aging impact on differential amplifier circuits in advanced CMOS technologies is presented and proven experimentally. It is shown that the proposed method also enables to compensate for process variation induced mismatch. Thus it provides analog circuit designers the opportunity to reduce matching related area requirements.
{"title":"An aging suppression and calibration approach for differential amplifiers in advanced CMOS technologies","authors":"F. Chouard, S. More, M. Fulde, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.2011.6044954","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044954","url":null,"abstract":"Stress experiments are presented on analog size devices in inversion and accumulation mode, including relaxing stress phenomena. Based on these data, a general concept to suppress device aging impact on differential amplifier circuits in advanced CMOS technologies is presented and proven experimentally. It is shown that the proposed method also enables to compensate for process variation induced mismatch. Thus it provides analog circuit designers the opportunity to reduce matching related area requirements.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044975
M. Guermandi, R. Cardu, E. Franchi, R. Guerrieri
The IC presented integrates the front-end for EEG and Electrical Impedance Tomography acquisition on the electrode, together with contact impedance monitoring, so as to improve signal quality and functional integration of the two techniques for brain imaging applications. Only 4 wires connect the electrode to the back-end. The readout circuit consumes 1 mW, while the input referred noise for EEG signal acquisition is 0.45 μVRMS between 0.5 and 100 Hz, doubling when both EEG and EIT are acquired simultaneously.
{"title":"Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wire","authors":"M. Guermandi, R. Cardu, E. Franchi, R. Guerrieri","doi":"10.1109/ESSCIRC.2011.6044975","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044975","url":null,"abstract":"The IC presented integrates the front-end for EEG and Electrical Impedance Tomography acquisition on the electrode, together with contact impedance monitoring, so as to improve signal quality and functional integration of the two techniques for brain imaging applications. Only 4 wires connect the electrode to the back-end. The readout circuit consumes 1 mW, while the input referred noise for EEG signal acquisition is 0.45 μVRMS between 0.5 and 100 Hz, doubling when both EEG and EIT are acquired simultaneously.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126906973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045007
Mathieu Egot, B. Martineau, O. Richard, N. Rolland, A. Cathelin, A. Kaiser
A Coupled Oscillator Array (COA) based on 4 differential LC Voltage Controlled Oscillators (VCO) with 21,5GHz central frequency and 15% locking range is presented. It achieves a maximum phase-shift of 100° which makes it suitable for 60GHz WirelessHD™ and WiGig applications with beamforming. The COA is implemented in a 65nm bulk CMOS process and dissipates 24mW from a 1.2 V supply.
{"title":"A 20–23GHz Coupled Oscillators Array in 65nm CMOS for HDR 60GHz beamforming applications","authors":"Mathieu Egot, B. Martineau, O. Richard, N. Rolland, A. Cathelin, A. Kaiser","doi":"10.1109/ESSCIRC.2011.6045007","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045007","url":null,"abstract":"A Coupled Oscillator Array (COA) based on 4 differential LC Voltage Controlled Oscillators (VCO) with 21,5GHz central frequency and 15% locking range is presented. It achieves a maximum phase-shift of 100° which makes it suitable for 60GHz WirelessHD™ and WiGig applications with beamforming. The COA is implemented in a 65nm bulk CMOS process and dissipates 24mW from a 1.2 V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044942
Xiongchuan Huang, P. Harpe, G. Dolmans, H. D. Groot
An ultra-low power wake-up receiver for wireless sensor network applications is presented. The 915MHz OOK receiver is based on the double-sampling RF power detector architecture. Together with an on-chip ADC, the receiver achieves −86dBm sensitivity at 10kbps, while consuming 123μW. Flexible sensitivity / data-rate / power consumption options are also possible. The receiver front-end is fabricated in a 90nm CMOS technology and wire-bonded in a QFN56 package.
{"title":"A 915MHz ultra-low power wake-up receiver with scalable performance and power consumption","authors":"Xiongchuan Huang, P. Harpe, G. Dolmans, H. D. Groot","doi":"10.1109/ESSCIRC.2011.6044942","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044942","url":null,"abstract":"An ultra-low power wake-up receiver for wireless sensor network applications is presented. The 915MHz OOK receiver is based on the double-sampling RF power detector architecture. Together with an on-chip ADC, the receiver achieves −86dBm sensitivity at 10kbps, while consuming 123μW. Flexible sensitivity / data-rate / power consumption options are also possible. The receiver front-end is fabricated in a 90nm CMOS technology and wire-bonded in a QFN56 package.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044889
N. Ickes, Yildiz Sinangil, F. Pappalardo, E. Guidetti, A. Chandrakasan
We describe a voltage-scalable 32b microprocessor system-on-chip (SoC) that provides both moderate peak performance (up to 82.5 MHz at 1.2 V) and extreme energy efficiency (10.2 pJ/cycle at 0.54 V) for applications with limited energy budgets and time varying processing loads. The SoC employs low-voltage 8T SRAMs operating down to an array voltage of 0.4 V. Memory access energy is further reduced by miniature (128 B) latch-based instruction and data caches. On chip clock generation and the ability to boot from a small external serial flash ROM makes for a very small overall system.
{"title":"A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip","authors":"N. Ickes, Yildiz Sinangil, F. Pappalardo, E. Guidetti, A. Chandrakasan","doi":"10.1109/ESSCIRC.2011.6044889","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044889","url":null,"abstract":"We describe a voltage-scalable 32b microprocessor system-on-chip (SoC) that provides both moderate peak performance (up to 82.5 MHz at 1.2 V) and extreme energy efficiency (10.2 pJ/cycle at 0.54 V) for applications with limited energy budgets and time varying processing loads. The SoC employs low-voltage 8T SRAMs operating down to an array voltage of 0.4 V. Memory access energy is further reduced by miniature (128 B) latch-based instruction and data caches. On chip clock generation and the ability to boot from a small external serial flash ROM makes for a very small overall system.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045005
R. Su, S. Lanzisera, K. Pister
An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to increase TDC resolution, and includes digital correction circuitry to resolve issues from clock skew. A .18μm CMOS prototype occupies 500μm × 500μm of area, generates a 900MHz clock from a 10MHz reference, has phase noise of −90dBc/Hz at 1MHz offset and 2.62psrms jitter while consuming 4.2mA from a 1.8V supply.
{"title":"A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells","authors":"R. Su, S. Lanzisera, K. Pister","doi":"10.1109/ESSCIRC.2011.6045005","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045005","url":null,"abstract":"An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to increase TDC resolution, and includes digital correction circuitry to resolve issues from clock skew. A .18μm CMOS prototype occupies 500μm × 500μm of area, generates a 900MHz clock from a 10MHz reference, has phase noise of −90dBc/Hz at 1MHz offset and 2.62psrms jitter while consuming 4.2mA from a 1.8V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126473128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044978
O. Jamin, V. Rambeau, F. Goussin, G. Lebailly
This paper presents a broadband fully integrated high dynamic range RF front-end with a single-inductor programmable RF amplitude equalizer, 45dB variable gain range, 4.5dB NF, 60dB CSO/CTB, and 25dB anti-aliasing protection. It is designed in a 40GHz-ft BiCMOS 0.25μm process, consumes 400mW from a 3.3V supply, and enables a cable full-spectrum receiver to capture >16 channels over an 50MHz–1GHz RF band.
{"title":"An RF front-end for multi-channel direct RF sampling cable receivers","authors":"O. Jamin, V. Rambeau, F. Goussin, G. Lebailly","doi":"10.1109/ESSCIRC.2011.6044978","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044978","url":null,"abstract":"This paper presents a broadband fully integrated high dynamic range RF front-end with a single-inductor programmable RF amplitude equalizer, 45dB variable gain range, 4.5dB NF, 60dB CSO/CTB, and 25dB anti-aliasing protection. It is designed in a 40GHz-ft BiCMOS 0.25μm process, consumes 400mW from a 3.3V supply, and enables a cable full-spectrum receiver to capture >16 channels over an 50MHz–1GHz RF band.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131716144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044927
Andreas Spickermann, D. Durini, A. Süss, W. Ulfig, W. Brockherde, B. Hosticka, S. Schwope, A. Grabmaier
Design and measurement results of a CMOS 128 × 96 pixel sensor are presented, which can be used for three-dimensional (3D) scene reconstruction applications based on indirect time-of-flight (ToF) principle enabled by pulse modulated active laser illumination. The 40μm pitch pixels are based on the novel intrinsic lateral drift-field photodiode (LDPD) that allows for a 30ns complete charge transfer from the photoactive area into the readout node, and accumulation of signal charge over several readout cycles for extended signal-to-noise ratio (SNR). Distance measurements have been performed using a specially developed camera system.
{"title":"CMOS 3D image sensor based on pulse modulated time-of-flight principle and intrinsic lateral drift-field photodiode pixels","authors":"Andreas Spickermann, D. Durini, A. Süss, W. Ulfig, W. Brockherde, B. Hosticka, S. Schwope, A. Grabmaier","doi":"10.1109/ESSCIRC.2011.6044927","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044927","url":null,"abstract":"Design and measurement results of a CMOS 128 × 96 pixel sensor are presented, which can be used for three-dimensional (3D) scene reconstruction applications based on indirect time-of-flight (ToF) principle enabled by pulse modulated active laser illumination. The 40μm pitch pixels are based on the novel intrinsic lateral drift-field photodiode (LDPD) that allows for a 30ns complete charge transfer from the photoactive area into the readout node, and accumulation of signal charge over several readout cycles for extended signal-to-noise ratio (SNR). Distance measurements have been performed using a specially developed camera system.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044949
H. M. Geddada, J. Silva-Martínez, S. Taylor
This paper presents two linear broadband inductorless Low Noise Transconductance Amplifiers (LNTA) featuring high linearities for large signal (P1dB) and small signal (IIP3). The LNTAs utilize the complementary characteristics of NMOS and PMOS transistors to enhance the linearity. First prototype is a fully balanced current reuse LNTA achieving 0.12GHz bandwidth, minimum NF of 3dB, IIP3 of 10.8dBm and P1dB of 0dBm while dissipating 35mW. Second prototype proposes a low power bulk driven LNTA with 20mW of power consumption achieving comparable performances. Each LNTA occupy 0.06mm2 in 45nm CMOS.
{"title":"Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS","authors":"H. M. Geddada, J. Silva-Martínez, S. Taylor","doi":"10.1109/ESSCIRC.2011.6044949","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044949","url":null,"abstract":"This paper presents two linear broadband inductorless Low Noise Transconductance Amplifiers (LNTA) featuring high linearities for large signal (P1dB) and small signal (IIP3). The LNTAs utilize the complementary characteristics of NMOS and PMOS transistors to enhance the linearity. First prototype is a fully balanced current reuse LNTA achieving 0.12GHz bandwidth, minimum NF of 3dB, IIP3 of 10.8dBm and P1dB of 0dBm while dissipating 35mW. Second prototype proposes a low power bulk driven LNTA with 20mW of power consumption achieving comparable performances. Each LNTA occupy 0.06mm2 in 45nm CMOS.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"277 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120985028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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