Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044996
A. Cabrini, F. Gallazzi, G. Torelli
This paper presents a current reference for read and verify operations in multilevel phase-change memories (PCMs). The circuit is able to track the temperature behaviour of the PCM cell current over a temperature range from −40 °C to 80 °C, as is necessary to meet the stringent requirements of multilevel PCM sensing. The proposed scheme is based on an MOS transistor biased in saturation below its zero temperature coefficient (ZTC) point. Only room temperature trimming at wafer sort is required to adjust the value and the temperature dependence of the generated current. Experimental results showed good agreement with experimental data on PCM cells. The error in the programmed temperature coefficient is kept within 10% in any process condition.
{"title":"Current reference scheme for multilevel phase-change memory sensing","authors":"A. Cabrini, F. Gallazzi, G. Torelli","doi":"10.1109/ESSCIRC.2011.6044996","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044996","url":null,"abstract":"This paper presents a current reference for read and verify operations in multilevel phase-change memories (PCMs). The circuit is able to track the temperature behaviour of the PCM cell current over a temperature range from −40 °C to 80 °C, as is necessary to meet the stringent requirements of multilevel PCM sensing. The proposed scheme is based on an MOS transistor biased in saturation below its zero temperature coefficient (ZTC) point. Only room temperature trimming at wafer sort is required to adjust the value and the temperature dependence of the generated current. Experimental results showed good agreement with experimental data on PCM cells. The error in the programmed temperature coefficient is kept within 10% in any process condition.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130862004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044886
P. Harpe, B. Busze, K. Philips, H. D. Groot
This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.
{"title":"A 0.47–1.6mW 5bit 0.5–1GS/s time-interleaved SAR ADC for low-power UWB radios","authors":"P. Harpe, B. Busze, K. Philips, H. D. Groot","doi":"10.1109/ESSCIRC.2011.6044886","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044886","url":null,"abstract":"This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131481281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044965
T. Northemann, R. Schillinger, M. Maurer, Y. Manoli
This paper presents the circuit implementation of an amplitude regulation for the primary mode of gyroscopes based on phase-shifting. Instead of regulating the AC or DC value of the driving stage in order to maintain a constant primary oscillation, this concept introduces a tunable phase delay into the driving loop. The high voltages of the driving stage can be set to a constant value and do not have to be adjusted. The driving stage can be realized with a set of simple switches applying two fixed voltages to the gyroscope for actuation. This reduces the complexity of the circuitry enormously. Measurements reveal that the frequency is held constant with a sigma of 1Hz and the amplitude regulation is within 0.6% of the defined value.
{"title":"Controlling the primary mode of gyroscopes with a phase-based amplitude regulation","authors":"T. Northemann, R. Schillinger, M. Maurer, Y. Manoli","doi":"10.1109/ESSCIRC.2011.6044965","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044965","url":null,"abstract":"This paper presents the circuit implementation of an amplitude regulation for the primary mode of gyroscopes based on phase-shifting. Instead of regulating the AC or DC value of the driving stage in order to maintain a constant primary oscillation, this concept introduces a tunable phase delay into the driving loop. The high voltages of the driving stage can be set to a constant value and do not have to be adjusted. The driving stage can be realized with a set of simple switches applying two fixed voltages to the gyroscope for actuation. This reduces the complexity of the circuitry enormously. Measurements reveal that the frequency is held constant with a sigma of 1Hz and the amplitude regulation is within 0.6% of the defined value.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130228589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044958
F. Cannillo, E. Prefasi, L. Hernández, E. Pun, R. Yazicioglu, C. Hoof
High-resolution Sigma-Delta (∑Δ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-∑Δ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.
{"title":"1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition","authors":"F. Cannillo, E. Prefasi, L. Hernández, E. Pun, R. Yazicioglu, C. Hoof","doi":"10.1109/ESSCIRC.2011.6044958","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044958","url":null,"abstract":"High-resolution Sigma-Delta (∑Δ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-∑Δ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128711886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044936
B. Rooseleer, S. Cosemans, W. Dehaene
This paper presents a 65nm, 256 kbit SRAM memory which achieves both ultra low leakage power and very low active energy consumption at a speed of 850 MHz. Used techniques include divided word and bitlines, local write sense amplifiers, dynamic cell stability and a distributed decoder. In addition, three novel techniques are proposed which decrease power consumption even further. High threshold voltage cells reduce leakage and improve stability. Dual swing signalling on the global bitlines reduces energy without compromising robustness. The decoder uses a new type of dynamic gate to increase speed. The design was fabricated in a low power 65nm CMOS process. Measured performance for this 256 kbit SRAM with 32 bit wordlength is 4.3pJ per access and 25.2 μW leakage power at a speed of 850 MHz.
{"title":"A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link","authors":"B. Rooseleer, S. Cosemans, W. Dehaene","doi":"10.1109/ESSCIRC.2011.6044936","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044936","url":null,"abstract":"This paper presents a 65nm, 256 kbit SRAM memory which achieves both ultra low leakage power and very low active energy consumption at a speed of 850 MHz. Used techniques include divided word and bitlines, local write sense amplifiers, dynamic cell stability and a distributed decoder. In addition, three novel techniques are proposed which decrease power consumption even further. High threshold voltage cells reduce leakage and improve stability. Dual swing signalling on the global bitlines reduces energy without compromising robustness. The decoder uses a new type of dynamic gate to increase speed. The design was fabricated in a low power 65nm CMOS process. Measured performance for this 256 kbit SRAM with 32 bit wordlength is 4.3pJ per access and 25.2 μW leakage power at a speed of 850 MHz.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044981
R. Nguyen, C. Raynaud, A. Cathelin, B. Murmann
A 6.7-ENOB, 500-MS/s pipeline ADC is realized using low-power charge pump-like dynamic gain stages operating with incomplete transient settling. The experimental converter occupies an active area of 0.02 mm2 in 65-nm SOI CMOS and dissipates 5.1 mW from a 1.2-V supply. It achieves an SNDR of 41.5 dB for inputs near Nyquist, corresponding to a figure of merit of 98 fJ/conv.-step.
采用不完全瞬态稳定的低功率电荷泵式动态增益级实现了一个6.7 enob、500 ms /s的流水线ADC。该实验转换器在65nm SOI CMOS中占据0.02 mm2的有源面积，在1.2 v电源下耗散5.1 mW。它在Nyquist附近的输入实现了41.5 dB的SNDR，对应于98 fJ/ conv.step的优值。
{"title":"A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS","authors":"R. Nguyen, C. Raynaud, A. Cathelin, B. Murmann","doi":"10.1109/ESSCIRC.2011.6044981","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044981","url":null,"abstract":"A 6.7-ENOB, 500-MS/s pipeline ADC is realized using low-power charge pump-like dynamic gain stages operating with incomplete transient settling. The experimental converter occupies an active area of 0.02 mm2 in 65-nm SOI CMOS and dissipates 5.1 mW from a 1.2-V supply. It achieves an SNDR of 41.5 dB for inputs near Nyquist, corresponding to a figure of merit of 98 fJ/conv.-step.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127088550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044899
Yuji Osaki, T. Hirose, N. Kuroki, M. Numa
A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit has a distinctive feature in current generation scheme with logic error correction circuit by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low-power operation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse.
{"title":"A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs","authors":"Yuji Osaki, T. Hirose, N. Kuroki, M. Numa","doi":"10.1109/ESSCIRC.2011.6044899","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044899","url":null,"abstract":"A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit has a distinctive feature in current generation scheme with logic error correction circuit by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low-power operation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126764093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044979
Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang
This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.
{"title":"A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement","authors":"Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang","doi":"10.1109/ESSCIRC.2011.6044979","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044979","url":null,"abstract":"This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129013861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044997
Cheng-Yuan Wen, J. Paramesh, L. Pileggi, Jing Li, Sangbum Kim, J. Proesel, C. Lam
This paper describes the design of an offset-minimized CMOS comparator with post-manufacturing calibration using non-volatile phase-change random access memory (PCRAM) cells. The digital calibration technique exploits combinatorial redundancy to reduce overall mismatch by selecting an optimal subset from a population of nominally identical elements. PCRAM cells provide switchable resistances that are employed to configure selection. Fabricated in IBM 90 nm CMOS technology with embedded GST (Ge2Sb2Te5)-based PCRAM mushroom cells, a comparator operating at 1V with total power of 55.42μW and input capacitance of 4.41fF achieve 0.5mV input offset voltage with reconfiguration while the corresponding input offset voltage with traditional random offset sizing is 28.5mV.
{"title":"Post-silicon calibration of analog CMOS using phase-change memory cells","authors":"Cheng-Yuan Wen, J. Paramesh, L. Pileggi, Jing Li, Sangbum Kim, J. Proesel, C. Lam","doi":"10.1109/ESSCIRC.2011.6044997","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044997","url":null,"abstract":"This paper describes the design of an offset-minimized CMOS comparator with post-manufacturing calibration using non-volatile phase-change random access memory (PCRAM) cells. The digital calibration technique exploits combinatorial redundancy to reduce overall mismatch by selecting an optimal subset from a population of nominally identical elements. PCRAM cells provide switchable resistances that are employed to configure selection. Fabricated in IBM 90 nm CMOS technology with embedded GST (Ge2Sb2Te5)-based PCRAM mushroom cells, a comparator operating at 1V with total power of 55.42μW and input capacitance of 4.41fF achieve 0.5mV input offset voltage with reconfiguration while the corresponding input offset voltage with traditional random offset sizing is 28.5mV.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044913
M. Frank
High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes. We review gate-first high-k / metal gate (HKMG) innovations enabling continued device scaling to the 22 and 14 nm nodes and beyond. First, we summarize some of the insight that allowed early HKMG challenges such as equivalent oxide thickness (EOT) and threshold voltage control to be overcome. Then, we discuss HKMG approaches that enable ultimate EOT scaling, pitch scaling via borderless source/drain contact formation, and the fabrication of multi-gate field-effect transistors. Finally, we summarize recent progress in gate stack development for high-mobility channel materials such as germanium and III-V compound semiconductors.
{"title":"High-k/metal gate innovations enabling continued CMOS scaling","authors":"M. Frank","doi":"10.1109/ESSCIRC.2011.6044913","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044913","url":null,"abstract":"High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes. We review gate-first high-k / metal gate (HKMG) innovations enabling continued device scaling to the 22 and 14 nm nodes and beyond. First, we summarize some of the insight that allowed early HKMG challenges such as equivalent oxide thickness (EOT) and threshold voltage control to be overcome. Then, we discuss HKMG approaches that enable ultimate EOT scaling, pitch scaling via borderless source/drain contact formation, and the fabrication of multi-gate field-effect transistors. Finally, we summarize recent progress in gate stack development for high-mobility channel materials such as germanium and III-V compound semiconductors.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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