Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044992
Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, J. Yu, Chen-Yi Lee
This paper presents an all-digital signal component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm2. The required phases of branch signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of −31.06 dB using 64-QAM OFDM signals can be achieved for high-efficiency UMLINC systems.
{"title":"A low power all-digital signal component separator for uneven multi-level LINC systems","authors":"Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, J. Yu, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2011.6044992","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044992","url":null,"abstract":"This paper presents an all-digital signal component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm2. The required phases of branch signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of −31.06 dB using 64-QAM OFDM signals can be achieved for high-efficiency UMLINC systems.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044897
A. Muramatsu, T. Yasufuku, M. Nomura, M. Takamiya, H. Shinohara, T. Sakurai
Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6×7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.
{"title":"12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains","authors":"A. Muramatsu, T. Yasufuku, M. Nomura, M. Takamiya, H. Shinohara, T. Sakurai","doi":"10.1109/ESSCIRC.2011.6044897","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044897","url":null,"abstract":"Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (V<inf>DD</inf>) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6×7 voltage domains. Both high V<inf>DD</inf> (V<inf>DDH</inf>) and low V<inf>DD</inf> (V<inf>DDL</inf>) are supplied to each power domain and either V<inf>DDH</inf> or V<inf>DDL</inf> is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single V<inf>DD</inf> operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044990
Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene
A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.
{"title":"A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS","authors":"Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene","doi":"10.1109/ESSCIRC.2011.6044990","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044990","url":null,"abstract":"A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132885231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044884
Wagdy M. Gaber, P. Wambacq, J. Craninckx, M. Ingels
This paper presents a new approach to reduce the out of band quantization noise of Direct Digital RF Modulators (DDRM). The DDRM is organized in a FIR-like configuration to filter the quantization noise in the RX band directly at RF. To demonstrate the principle, a 0.9 GHz FIR IQ DDRM has been integrated in 130 nm CMOS. The transmitter achieves more than 22 dB reduction in the quantization noise floor to reach −152 dBc/Hz@20 MHz with a 200 KHz baseband tone. The actual DDRM is capable of both amplitude and phase modulation by using a new four-phases IQ architecture. This results in a reduced power consumption and chip area. The transmitter consumes 94 mW from a 2.7 V supply and achieves an average output power of 9.5 dBm. Leakage into the adjacent channel and into the next one of −35 dB and −53 dB, respectively have been measured for a 10 MHz OFDM signal. It also achieves −27.2 dB EVM with a 64QAM input signal.
提出了一种降低直接数字射频调制器(DDRM)带外量化噪声的新方法。DDRM被组织成一个类似fir的配置，直接在射频处过滤RX波段的量化噪声。为了演示该原理，在130 nm CMOS中集成了0.9 GHz FIR IQ DDRM。发射机实现了超过22 dB的量化噪声底降低，达到- 152 dBc/Hz@20 MHz，基带音调为200 KHz。实际的DDRM能够通过使用新的四相IQ架构进行幅度和相位调制。这就降低了功耗和芯片面积。发射机从2.7 V电源消耗94 mW，实现9.5 dBm的平均输出功率。对于10mhz OFDM信号，测量了相邻信道和下一信道的泄漏量分别为−35db和−53db。它还可以在64QAM输入信号下实现−27.2 dB EVM。
{"title":"A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter","authors":"Wagdy M. Gaber, P. Wambacq, J. Craninckx, M. Ingels","doi":"10.1109/ESSCIRC.2011.6044884","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044884","url":null,"abstract":"This paper presents a new approach to reduce the out of band quantization noise of Direct Digital RF Modulators (DDRM). The DDRM is organized in a FIR-like configuration to filter the quantization noise in the RX band directly at RF. To demonstrate the principle, a 0.9 GHz FIR IQ DDRM has been integrated in 130 nm CMOS. The transmitter achieves more than 22 dB reduction in the quantization noise floor to reach −152 dBc/Hz@20 MHz with a 200 KHz baseband tone. The actual DDRM is capable of both amplitude and phase modulation by using a new four-phases IQ architecture. This results in a reduced power consumption and chip area. The transmitter consumes 94 mW from a 2.7 V supply and achieves an average output power of 9.5 dBm. Leakage into the adjacent channel and into the next one of −35 dB and −53 dB, respectively have been measured for a 10 MHz OFDM signal. It also achieves −27.2 dB EVM with a 64QAM input signal.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133746374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044924
A. Villegas, D. Vázquez, E. Peralías, A. Rueda
This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype.
{"title":"A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard","authors":"A. Villegas, D. Vázquez, E. Peralías, A. Rueda","doi":"10.1109/ESSCIRC.2011.6044924","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044924","url":null,"abstract":"This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132121122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044956
Ankesh Jain, Muthusubramanian Venkateswaran, S. Pavan
We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.1
{"title":"A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range","authors":"Ankesh Jain, Muthusubramanian Venkateswaran, S. Pavan","doi":"10.1109/ESSCIRC.2011.6044956","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044956","url":null,"abstract":"We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.1","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134621586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044984
T. Hehn, D. Maurath, F. Hagedorn, Djordje Marinkovic, I. Kuehne, A. Frey, Y. Manoli
This paper presents a fully autonomous, self-adjusting pulsed synchronous charge extractor chip optimized for piezoelectric harvesters with an output voltage from 3V to 18V. The chip which has been fabricated in a 0.35 μm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum piezo output power of 30μW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages from 1.4 V to 5V. The implementation of the improved switching technique increases the chip efficiency by up to 15% compared to the commonly used Synchronous Electric Charge Extraction technique and enables the chip efficiency to reach values of up to 90%.
{"title":"A fully autonomous pulsed synchronous charge extractor for high-voltage piezoelectric harvesters","authors":"T. Hehn, D. Maurath, F. Hagedorn, Djordje Marinkovic, I. Kuehne, A. Frey, Y. Manoli","doi":"10.1109/ESSCIRC.2011.6044984","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044984","url":null,"abstract":"This paper presents a fully autonomous, self-adjusting pulsed synchronous charge extractor chip optimized for piezoelectric harvesters with an output voltage from 3V to 18V. The chip which has been fabricated in a 0.35 μm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum piezo output power of 30μW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages from 1.4 V to 5V. The implementation of the improved switching technique increases the chip efficiency by up to 15% compared to the commonly used Synchronous Electric Charge Extraction technique and enables the chip efficiency to reach values of up to 90%.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117056261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044929
S. Mandai, E. Charbon
This paper proposes a 128-channel column-parallel two-stage time-to-digital converter (TDC) utilizing a time difference amplifier (TDA) and shows measurement results with a 0.35um CMOS process. The 1st stage operates as a coarse TDC, the time residue which is not converted in the 1st stage is amplified by a TDA, then converted by the 2nd stage TDC. As the gain of the time difference amplifier can be adjusted from 8.6 to 21.6, the time resolution of the TDC can be tuned from 22.4ps to 8.9ps. The time resolution variation due to PVT effects is ±12% without compensation, however calibration can be used to compensate for this variation.
{"title":"A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imaging","authors":"S. Mandai, E. Charbon","doi":"10.1109/ESSCIRC.2011.6044929","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044929","url":null,"abstract":"This paper proposes a 128-channel column-parallel two-stage time-to-digital converter (TDC) utilizing a time difference amplifier (TDA) and shows measurement results with a 0.35um CMOS process. The 1st stage operates as a coarse TDC, the time residue which is not converted in the 1st stage is amplified by a TDA, then converted by the 2nd stage TDC. As the gain of the time difference amplifier can be adjusted from 8.6 to 21.6, the time resolution of the TDC can be tuned from 22.4ps to 8.9ps. The time resolution variation due to PVT effects is ±12% without compensation, however calibration can be used to compensate for this variation.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123196196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044963
Hans Danneels, Kristof Coddens, G. Gielen
This paper presents a fully-digital capacitive sensor interface. By directly transforming the sensor value instead of using an intermediate step in the voltage domain, the architecture can cope with very low signal swings. An implementation for barometric pressure sensing with a supply voltage of 0.3 V demonstrates the benefits. With a power consumption of only 270 nW and an acquisition time of 1 ms, an ENOB of 6.1 is obtained, resulting in a FOM of 2.1 pJ/conv for the entire interface. This is at least an order of magnitude better than current state-of-the-art implementations.
{"title":"A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references","authors":"Hans Danneels, Kristof Coddens, G. Gielen","doi":"10.1109/ESSCIRC.2011.6044963","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044963","url":null,"abstract":"This paper presents a fully-digital capacitive sensor interface. By directly transforming the sensor value instead of using an intermediate step in the voltage domain, the architecture can cope with very low signal swings. An implementation for barometric pressure sensing with a supply voltage of 0.3 V demonstrates the benefits. With a power consumption of only 270 nW and an acquisition time of 1 ms, an ENOB of 6.1 is obtained, resulting in a FOM of 2.1 pJ/conv for the entire interface. This is at least an order of magnitude better than current state-of-the-art implementations.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122732952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044968
Liang Rong, F. Jonsson, Lirong Zheng
Using RF Sigma Delta Modulation (RFSDM), a class-D polar amplifier in H-Bridge configuration can work in resonating mode and minimize the switching loss for high efficiency polar transmitters. The high oversampling ratio envelop bit stream created by the low pass RFSDM is phase modulated and digitally mixed with quantized RF carrier to give a modulated RF digital signal. By taking the advantage of high speed and accurate digital CMOS process, this ‘information combination’ architecture can achieve high efficiency and reduce the need for external filter components. A polar power amplifier based on this concept is implemented in 90nm CMOS process and achieved a peak output power of 11.4dBm with 19.3% efficiency at 1.0V power supply. The total area is 0.72mm2 including an on-chip filter matching network designed for 2.4GHz to 2.7GHz band.
{"title":"A 11.4dBm 90nm CMOS H-Bridge resonating polar amplifier using RF Sigma Delta Modulation","authors":"Liang Rong, F. Jonsson, Lirong Zheng","doi":"10.1109/ESSCIRC.2011.6044968","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044968","url":null,"abstract":"Using RF Sigma Delta Modulation (RFSDM), a class-D polar amplifier in H-Bridge configuration can work in resonating mode and minimize the switching loss for high efficiency polar transmitters. The high oversampling ratio envelop bit stream created by the low pass RFSDM is phase modulated and digitally mixed with quantized RF carrier to give a modulated RF digital signal. By taking the advantage of high speed and accurate digital CMOS process, this ‘information combination’ architecture can achieve high efficiency and reduce the need for external filter components. A polar power amplifier based on this concept is implemented in 90nm CMOS process and achieved a peak output power of 11.4dBm with 19.3% efficiency at 1.0V power supply. The total area is 0.72mm2 including an on-chip filter matching network designed for 2.4GHz to 2.7GHz band.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126288562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：