Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044892
Jongmoon Kim, Seokoh Yun, Wonkab Oh, Minsu Kil, Sang-Bock Cho
A true single SoC for UHF Mobile RFID Reader has been implemented in a 0.18μm embedded flash CMOS technology. The SoC includes 900MHz RF transceiver, PA, MODEM, MCU, memory and peripherals with fully compliant ISO/IEC 18000–6C and EPC Global Class1 Gen2 reader protocol. The receiver 1% PER sensitivity is −88dBm at RF input port. The class-A PA is integrated in the transmitter, with 20dBm CW carrier output power. The fully integrated fractional-N frequency synthesizer with a 3.6GHz LC VCO is implemented for low wide band phase noise. The LO phase noise is −104.7dBc/Hz at 100KHz offset frequency and −130.6dBc/Hz at 1MHz offset frequency. The SoC satisfies a multiple-interrogator environment's ACPR requirement of the ISO/IEC 18000–6C standard. In operating Tag read mode, the SoC dissipates 980mW when transmitting a 20dBm CW carrier signal. The die area of the SoC is 17.1mm2, of which 7.6mm2 is used by the 900MHz RF transceiver and PA.
{"title":"A true single SoC for UHF mobile RFID reader","authors":"Jongmoon Kim, Seokoh Yun, Wonkab Oh, Minsu Kil, Sang-Bock Cho","doi":"10.1109/ESSCIRC.2011.6044892","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044892","url":null,"abstract":"A true single SoC for UHF Mobile RFID Reader has been implemented in a 0.18μm embedded flash CMOS technology. The SoC includes 900MHz RF transceiver, PA, MODEM, MCU, memory and peripherals with fully compliant ISO/IEC 18000–6C and EPC Global Class1 Gen2 reader protocol. The receiver 1% PER sensitivity is −88dBm at RF input port. The class-A PA is integrated in the transmitter, with 20dBm CW carrier output power. The fully integrated fractional-N frequency synthesizer with a 3.6GHz LC VCO is implemented for low wide band phase noise. The LO phase noise is −104.7dBc/Hz at 100KHz offset frequency and −130.6dBc/Hz at 1MHz offset frequency. The SoC satisfies a multiple-interrogator environment's ACPR requirement of the ISO/IEC 18000–6C standard. In operating Tag read mode, the SoC dissipates 980mW when transmitting a 20dBm CW carrier signal. The die area of the SoC is 17.1mm2, of which 7.6mm2 is used by the 900MHz RF transceiver and PA.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130407423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044970
S. Jolivet, S. Amiot, Olivier Crand, S. Bertrand, B. Jarry, J. Lintignat
A fully-active tunable RF bandpass filter is presented. It uses a novel positive feedback RC “Rauch” structure, based on a wideband amplifier for high dynamic range purposes. The filter, designed in a BiCMOS 0.25μm technology, exhibits a 10dBm IIP3 requirement and a 15dB noise figure. The quality factor of 3 obtained from 45 to 240MHz guarantees the required full integration of the selectivity for TV silicon tuners over more than two octaves of the VHF band.
{"title":"A high dynamic range fully-active 45–240MHz tunable RF bandpass filter for TV tuners","authors":"S. Jolivet, S. Amiot, Olivier Crand, S. Bertrand, B. Jarry, J. Lintignat","doi":"10.1109/ESSCIRC.2011.6044970","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044970","url":null,"abstract":"A fully-active tunable RF bandpass filter is presented. It uses a novel positive feedback RC “Rauch” structure, based on a wideband amplifier for high dynamic range purposes. The filter, designed in a BiCMOS 0.25μm technology, exhibits a 10dBm IIP3 requirement and a 15dB noise figure. The quality factor of 3 obtained from 45 to 240MHz guarantees the required full integration of the selectivity for TV silicon tuners over more than two octaves of the VHF band.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044898
G. Maderbacher, Thomas Jackum, W. Pribyl, Sylvia Michaelis, Dietrich Michaelis, C. Sandner
This paper presents two fast level shifters with low power consumption used for controlling the output stage of 5 V DC-DC buck converters. The propagation delays of the level shifters in nominal cases are lower than 0.61 ns, which allows controlling the power switches very accurately. The level shifters are very robust against power supply ringing and are evaluated in a DC-DC buck converter test chip in a 65 nm CMOS technology.
{"title":"Fast and robust level shifters in 65 nm CMOS","authors":"G. Maderbacher, Thomas Jackum, W. Pribyl, Sylvia Michaelis, Dietrich Michaelis, C. Sandner","doi":"10.1109/ESSCIRC.2011.6044898","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044898","url":null,"abstract":"This paper presents two fast level shifters with low power consumption used for controlling the output stage of 5 V DC-DC buck converters. The propagation delays of the level shifters in nominal cases are lower than 0.61 ns, which allows controlling the power switches very accurately. The level shifters are very robust against power supply ringing and are evaluated in a DC-DC buck converter test chip in a 65 nm CMOS technology.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044971
Shagun Bajoria, M. Snoeij, V. Schaffer, Mikhail V. Ivanov, Sijia Wang, K. Makinwa
A 36V precision voltage-to-current converter for 0–24mA loops is presented. It utilizes dynamic element matching (DEM) and an auto-calibration technique to achieve low DC inaccuracy (0.2%) and low DEM ripple (0.007%). Measurement results show that the auto-calibration suppresses the DEM ripple by a factor of 14, thus eliminating the need for a bulky off-chip ripple-suppression filter. The prototype chip is implemented in a 0.35μm CMOS process occupying 0.84mm2. It has a quiescent current of 0.5mA and a rise time of 10.2μs for a 1mA–23mA output step.
{"title":"A 36V voltage-to-current converter with dynamic element matching and auto-calibration for AC ripple reduction","authors":"Shagun Bajoria, M. Snoeij, V. Schaffer, Mikhail V. Ivanov, Sijia Wang, K. Makinwa","doi":"10.1109/ESSCIRC.2011.6044971","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044971","url":null,"abstract":"A 36V precision voltage-to-current converter for 0–24mA loops is presented. It utilizes dynamic element matching (DEM) and an auto-calibration technique to achieve low DC inaccuracy (0.2%) and low DEM ripple (0.007%). Measurement results show that the auto-calibration suppresses the DEM ripple by a factor of 14, thus eliminating the need for a bulky off-chip ripple-suppression filter. The prototype chip is implemented in a 0.35μm CMOS process occupying 0.84mm2. It has a quiescent current of 0.5mA and a rise time of 10.2μs for a 1mA–23mA output step.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"568 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116204435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045014
Lianming Li, P. Reynaert, M. Steyaert
A 60 GHz Colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques is realized in 90 nm CMOS. With the Miller capacitance, the tuned-input tuned-output oscillator and the conventional Colpitts oscillator are combined together, thereby solving its start-up issues and improving phase noise performance. Moreover, it is found that the oscillator is robust to the tank mistuning. The proposed oscillator achieves a phase noise of −102 dBc/Hz at 1 MHz offset from 57.6 GHz, consuming 7.2 mW from a power supply of 0.6 V. The tuning range is from 55.8 GHz to 61.1 GHz and the measured single-ended output power is about −7 dBm. Accordingly, the figures-of-merit are FOM −189 and FOMT −188 respectively.
{"title":"A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques","authors":"Lianming Li, P. Reynaert, M. Steyaert","doi":"10.1109/ESSCIRC.2011.6045014","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045014","url":null,"abstract":"A 60 GHz Colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques is realized in 90 nm CMOS. With the Miller capacitance, the tuned-input tuned-output oscillator and the conventional Colpitts oscillator are combined together, thereby solving its start-up issues and improving phase noise performance. Moreover, it is found that the oscillator is robust to the tank mistuning. The proposed oscillator achieves a phase noise of −102 dBc/Hz at 1 MHz offset from 57.6 GHz, consuming 7.2 mW from a power supply of 0.6 V. The tuning range is from 55.8 GHz to 61.1 GHz and the measured single-ended output power is about −7 dBm. Accordingly, the figures-of-merit are FOM −189 and FOMT −188 respectively.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"58-60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116255545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044890
Eduard Roytman, M. Nagarajan, Rahul Shah, Xin Ma, R. Bedard, Kambiz Munshi, R. Iknaian, Fengxiang Cai, Jian Xu, Gayathri Sridharan Devi, Pradeep Vempada
Technology scaling leads to reduction of supply voltage and increase in random device variability and thus creates new challenges for analog design. A complete overhaul of the design approach at system architecture and circuit topology levels is necessary to keep the link robust and tolerant to low supply voltage and random variability challenges. This paper presents key analog circuit architecture techniques employed to implement 6.4GT/s per lane, 14mW/Gbps analog front end high-speed IO interfaces on Poulson — a 32nm next generation Intel Itanium microprocessor [1].
{"title":"Variation tolerant digitally assisted high-speed IO PHY","authors":"Eduard Roytman, M. Nagarajan, Rahul Shah, Xin Ma, R. Bedard, Kambiz Munshi, R. Iknaian, Fengxiang Cai, Jian Xu, Gayathri Sridharan Devi, Pradeep Vempada","doi":"10.1109/ESSCIRC.2011.6044890","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044890","url":null,"abstract":"Technology scaling leads to reduction of supply voltage and increase in random device variability and thus creates new challenges for analog design. A complete overhaul of the design approach at system architecture and circuit topology levels is necessary to keep the link robust and tolerant to low supply voltage and random variability challenges. This paper presents key analog circuit architecture techniques employed to implement 6.4GT/s per lane, 14mW/Gbps analog front end high-speed IO interfaces on Poulson — a 32nm next generation Intel Itanium microprocessor [1].","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126340344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044940
Fabian van Houwelingen, E. V. Tuijl, B. Nauta, M. Vertregt
Radio receivers and transmitters produce distortion products which are high above the noise floor. These products emanate from a combination of a low-order nonlinearity and the narrowband nature of the signal of interest. In this work, a scrambling system is proposed that can be added to a receiver, reducing these distortion products. Continuous time-domain signal manipulation is used to spread the spectral power of a narrowband signal, before it passes through nonlinear receiver circuitry. Digitally the original signal shape is reconstructed. This way, the distortion created by the nonlinearity does not result in dominant tones, improving IP2 and IP3 figures without increasing the intrinsic circuitry linearity, saving power and maintaining flexibility. This topology became possible through using new designs and topologies, which allow signal manipulation using passive components only. Additionally, a new high speed DAC design allows a voltage supply rail to be used as a sub-mV accurate reference. The concept is demonstrated using a software-radio approach, in which the sampling and buffering represents the nonlinear processing. With a 2.2Vpp, diff 100 MHz input signal, the measured distortion products are below −74 dBc. At 1.4 GHz input this number is 60.2 dBc. The scrambling hardware uses 54 mW in a 65nm CMOS process.
{"title":"A narrow-to-wideband scrambling technique increasing software radio receiver linearity","authors":"Fabian van Houwelingen, E. V. Tuijl, B. Nauta, M. Vertregt","doi":"10.1109/ESSCIRC.2011.6044940","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044940","url":null,"abstract":"Radio receivers and transmitters produce distortion products which are high above the noise floor. These products emanate from a combination of a low-order nonlinearity and the narrowband nature of the signal of interest. In this work, a scrambling system is proposed that can be added to a receiver, reducing these distortion products. Continuous time-domain signal manipulation is used to spread the spectral power of a narrowband signal, before it passes through nonlinear receiver circuitry. Digitally the original signal shape is reconstructed. This way, the distortion created by the nonlinearity does not result in dominant tones, improving IP2 and IP3 figures without increasing the intrinsic circuitry linearity, saving power and maintaining flexibility. This topology became possible through using new designs and topologies, which allow signal manipulation using passive components only. Additionally, a new high speed DAC design allows a voltage supply rail to be used as a sub-mV accurate reference. The concept is demonstrated using a software-radio approach, in which the sampling and buffering represents the nonlinear processing. With a 2.2Vpp, diff 100 MHz input signal, the measured distortion products are below −74 dBc. At 1.4 GHz input this number is 60.2 dBc. The scrambling hardware uses 54 mW in a 65nm CMOS process.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130185511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044943
C. Bryant, H. Sjöland
This paper presents an inductorless ultra-low power radio receiver front-end intended for applications such as sensor networks and medical implants. It consists of low noise amplifier, quadrature mixer, and a frequency divider for the generation of quadrature local oscillator signals. The power consumption is just 282μW from a 0.9V supply when it operates in the 915 MHz ISM band It achieves a total gain of 30dB and a noise figure below 9dB. Manufactured in 65nm CMOS, the active area is 0.016mm2. In a 200Ω environment it achieves a −17dB S11 without any external matching network.
{"title":"A 65nm CMOS 282μW 915MHz direct conversion receiver front-end","authors":"C. Bryant, H. Sjöland","doi":"10.1109/ESSCIRC.2011.6044943","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044943","url":null,"abstract":"This paper presents an inductorless ultra-low power radio receiver front-end intended for applications such as sensor networks and medical implants. It consists of low noise amplifier, quadrature mixer, and a frequency divider for the generation of quadrature local oscillator signals. The power consumption is just 282μW from a 0.9V supply when it operates in the 915 MHz ISM band It achieves a total gain of 30dB and a noise figure below 9dB. Manufactured in 65nm CMOS, the active area is 0.016mm2. In a 200Ω environment it achieves a −17dB S11 without any external matching network.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130394090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045004
Chun-Pang Wu, Shengyang Wang, H. Tsao, Jingshown Wu
This paper describes a sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation. Modified phase frequency detector (PFD) and charge pump are utilized to improve the linearity. A delay line with 54ps delay resolution is inserted between the reference signal and PFD to compensate phase errors. At least 13dB fractional spur and quantization noise improvement could be achieved with 300 KHz loop bandwidth at 3.9GHz synthesized frequency in a standard 0.18μm CMOS technology which occupies 1.21×1.23mm2. The improvement can be further enhanced when delay resolution is improved with more advanced process.
{"title":"A 300KHz bandwidth 3.9GHz 0.18μm CMOS fractional-N synthesizer with 13dB broadband phase noise reduction","authors":"Chun-Pang Wu, Shengyang Wang, H. Tsao, Jingshown Wu","doi":"10.1109/ESSCIRC.2011.6045004","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045004","url":null,"abstract":"This paper describes a sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation. Modified phase frequency detector (PFD) and charge pump are utilized to improve the linearity. A delay line with 54ps delay resolution is inserted between the reference signal and PFD to compensate phase errors. At least 13dB fractional spur and quantization noise improvement could be achieved with 300 KHz loop bandwidth at 3.9GHz synthesized frequency in a standard 0.18μm CMOS technology which occupies 1.21×1.23mm2. The improvement can be further enhanced when delay resolution is improved with more advanced process.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044911
P. Bradley
Wireless medical implant technology has been revolutionized in the last 10 years with the introduction of the world-wide Medical Implant Communication Service (MICS 402–405 MHz) and more recently MedRadio (401–406) MHz band. This has enabled the growth of remote monitoring with improved patient care. Recent advances and future developments in this growth area are presented.
{"title":"Wireless medical implant technology — Recent advances and future developments","authors":"P. Bradley","doi":"10.1109/ESSCIRC.2011.6044911","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044911","url":null,"abstract":"Wireless medical implant technology has been revolutionized in the last 10 years with the introduction of the world-wide Medical Implant Communication Service (MICS 402–405 MHz) and more recently MedRadio (401–406) MHz band. This has enabled the growth of remote monitoring with improved patient care. Recent advances and future developments in this growth area are presented.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"79 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130704691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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